1 /*******************************************************************************
2 * File Name: cycfg_clocks.c
3 *
4 * Description:
5 * Clock configuration
6 * This file was automatically generated and should not be modified.
7 * Device Configurator: 2.0.0.1483
8 * Device Support Library (../../../../output/libs/COMPONENT_PSOC6/psoc6pdl): 1.5.0.1837
9 *
10 ********************************************************************************
11 * Copyright 2017-2019 Cypress Semiconductor Corporation
12 * SPDX-License-Identifier: Apache-2.0
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 ********************************************************************************/
26
27 #include "cycfg_clocks.h"
28
29 #if defined (CY_USING_HAL)
30 const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj =
31 {
32 .type = CYHAL_RSC_CLOCK,
33 .block_num = CYBSP_CSD_CLK_DIV_HW,
34 .channel_num = CYBSP_CSD_CLK_DIV_NUM,
35 };
36 #endif //defined (CY_USING_HAL)
37
38
init_cycfg_clocks(void)39 void init_cycfg_clocks(void)
40 {
41 Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
42 Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
43 Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
44 #if defined (CY_USING_HAL)
45 cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
46 #endif //defined (CY_USING_HAL)
47 }
48
