1 /**************************************************************************//**
2 * @file core_sc000.h
3 * @brief CMSIS SC000 Core Peripheral Access Layer Header File
4 * @version V4.30
5 * @date 20. October 2015
6 ******************************************************************************/
7 /* Copyright (c) 2009 - 2015 ARM LIMITED
8
9 All rights reserved.
10 Redistribution and use in source and binary forms, with or without
11 modification, are permitted provided that the following conditions are met:
12 - Redistributions of source code must retain the above copyright
13 notice, this list of conditions and the following disclaimer.
14 - Redistributions in binary form must reproduce the above copyright
15 notice, this list of conditions and the following disclaimer in the
16 documentation and/or other materials provided with the distribution.
17 - Neither the name of ARM nor the names of its contributors may be used
18 to endorse or promote products derived from this software without
19 specific prior written permission.
20 *
21 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
25 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 POSSIBILITY OF SUCH DAMAGE.
32 ---------------------------------------------------------------------------*/
33
34
35 #if defined ( __ICCARM__ )
36 #pragma system_include /* treat file as system include file for MISRA check */
37 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
38 #pragma clang system_header /* treat file as system include file */
39 #endif
40
41 #ifndef __CORE_SC000_H_GENERIC
42 #define __CORE_SC000_H_GENERIC
43
44 #include <stdint.h>
45
46 #ifdef __cplusplus
47 extern "C" {
48 #endif
49
50 /**
51 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
52 CMSIS violates the following MISRA-C:2004 rules:
53
54 \li Required Rule 8.5, object/function definition in header file.<br>
55 Function definitions in header files are used to allow 'inlining'.
56
57 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
58 Unions are used for effective representation of core registers.
59
60 \li Advisory Rule 19.7, Function-like macro defined.<br>
61 Function-like macros are used to allow more efficient code.
62 */
63
64
65 /*******************************************************************************
66 * CMSIS definitions
67 ******************************************************************************/
68 /**
69 \ingroup SC000
70 @{
71 */
72
73 /* CMSIS SC000 definitions */
74 #define __SC000_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
75 #define __SC000_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
76 #define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \
77 __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
78
79 #define __CORTEX_SC (000U) /*!< Cortex secure core */
80
81
82 #if defined ( __CC_ARM )
83 #define __ASM __asm /*!< asm keyword for ARM Compiler */
84 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
85 #define __STATIC_INLINE static __inline
86
87 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
88 #define __ASM __asm /*!< asm keyword for ARM Compiler */
89 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
90 #define __STATIC_INLINE static __inline
91
92 #elif defined ( __GNUC__ )
93 #define __ASM __asm /*!< asm keyword for GNU Compiler */
94 #define __INLINE inline /*!< inline keyword for GNU Compiler */
95 #define __STATIC_INLINE static inline
96
97 #elif defined ( __ICCARM__ )
98 #define __ASM __asm /*!< asm keyword for IAR Compiler */
99 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
100 #define __STATIC_INLINE static inline
101
102 #elif defined ( __TMS470__ )
103 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
104 #define __STATIC_INLINE static inline
105
106 #elif defined ( __TASKING__ )
107 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
108 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
109 #define __STATIC_INLINE static inline
110
111 #elif defined ( __CSMC__ )
112 #define __packed
113 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
114 #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
115 #define __STATIC_INLINE static inline
116
117 #else
118 #error Unknown compiler
119 #endif
120
121 /** __FPU_USED indicates whether an FPU is used or not.
122 This core does not support an FPU at all
123 */
124 #define __FPU_USED 0U
125
126 #if defined ( __CC_ARM )
127 #if defined __TARGET_FPU_VFP
128 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
129 #endif
130
131 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
132 #if defined __ARM_PCS_VFP
133 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
134 #endif
135
136 #elif defined ( __GNUC__ )
137 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
139 #endif
140
141 #elif defined ( __ICCARM__ )
142 #if defined __ARMVFP__
143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
144 #endif
145
146 #elif defined ( __TMS470__ )
147 #if defined __TI_VFP_SUPPORT__
148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149 #endif
150
151 #elif defined ( __TASKING__ )
152 #if defined __FPU_VFP__
153 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
154 #endif
155
156 #elif defined ( __CSMC__ )
157 #if ( __CSMC__ & 0x400U)
158 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
159 #endif
160
161 #endif
162
163 #include "core_cmInstr.h" /* Core Instruction Access */
164 #include "core_cmFunc.h" /* Core Function Access */
165
166 #ifdef __cplusplus
167 }
168 #endif
169
170 #endif /* __CORE_SC000_H_GENERIC */
171
172 #ifndef __CMSIS_GENERIC
173
174 #ifndef __CORE_SC000_H_DEPENDANT
175 #define __CORE_SC000_H_DEPENDANT
176
177 #ifdef __cplusplus
178 extern "C" {
179 #endif
180
181 /* check device defines and use defaults */
182 #if defined __CHECK_DEVICE_DEFINES
183 #ifndef __SC000_REV
184 #define __SC000_REV 0x0000U
185 #warning "__SC000_REV not defined in device header file; using default!"
186 #endif
187
188 #ifndef __MPU_PRESENT
189 #define __MPU_PRESENT 0U
190 #warning "__MPU_PRESENT not defined in device header file; using default!"
191 #endif
192
193 #ifndef __NVIC_PRIO_BITS
194 #define __NVIC_PRIO_BITS 2U
195 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
196 #endif
197
198 #ifndef __Vendor_SysTickConfig
199 #define __Vendor_SysTickConfig 0U
200 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
201 #endif
202 #endif
203
204 /* IO definitions (access restrictions to peripheral registers) */
205 /**
206 \defgroup CMSIS_glob_defs CMSIS Global Defines
207
208 <strong>IO Type Qualifiers</strong> are used
209 \li to specify the access to peripheral variables.
210 \li for automatic generation of peripheral register debug information.
211 */
212 #ifdef __cplusplus
213 #define __I volatile /*!< Defines 'read only' permissions */
214 #else
215 #define __I volatile const /*!< Defines 'read only' permissions */
216 #endif
217 #define __O volatile /*!< Defines 'write only' permissions */
218 #define __IO volatile /*!< Defines 'read / write' permissions */
219
220 /* following defines should be used for structure members */
221 #define __IM volatile const /*! Defines 'read only' structure member permissions */
222 #define __OM volatile /*! Defines 'write only' structure member permissions */
223 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
224
225 /*@} end of group SC000 */
226
227
228
229 /*******************************************************************************
230 * Register Abstraction
231 Core Register contain:
232 - Core Register
233 - Core NVIC Register
234 - Core SCB Register
235 - Core SysTick Register
236 - Core MPU Register
237 ******************************************************************************/
238 /**
239 \defgroup CMSIS_core_register Defines and Type Definitions
240 \brief Type definitions and defines for Cortex-M processor based devices.
241 */
242
243 /**
244 \ingroup CMSIS_core_register
245 \defgroup CMSIS_CORE Status and Control Registers
246 \brief Core Register type definitions.
247 @{
248 */
249
250 /**
251 \brief Union type to access the Application Program Status Register (APSR).
252 */
253 typedef union
254 {
255 struct
256 {
257 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
258 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
259 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
260 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
261 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
262 } b; /*!< Structure used for bit access */
263 uint32_t w; /*!< Type used for word access */
264 } APSR_Type;
265
266 /* APSR Register Definitions */
267 #define APSR_N_Pos 31U /*!< APSR: N Position */
268 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
269
270 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
271 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
272
273 #define APSR_C_Pos 29U /*!< APSR: C Position */
274 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
275
276 #define APSR_V_Pos 28U /*!< APSR: V Position */
277 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
278
279
280 /**
281 \brief Union type to access the Interrupt Program Status Register (IPSR).
282 */
283 typedef union
284 {
285 struct
286 {
287 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
288 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
289 } b; /*!< Structure used for bit access */
290 uint32_t w; /*!< Type used for word access */
291 } IPSR_Type;
292
293 /* IPSR Register Definitions */
294 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
295 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
296
297
298 /**
299 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
300 */
301 typedef union
302 {
303 struct
304 {
305 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
306 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
307 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
308 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
309 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
310 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
311 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
312 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
313 } b; /*!< Structure used for bit access */
314 uint32_t w; /*!< Type used for word access */
315 } xPSR_Type;
316
317 /* xPSR Register Definitions */
318 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
319 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
320
321 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
322 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
323
324 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
325 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
326
327 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
328 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
329
330 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
331 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
332
333 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
334 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
335
336
337 /**
338 \brief Union type to access the Control Registers (CONTROL).
339 */
340 typedef union
341 {
342 struct
343 {
344 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
345 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
346 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
347 } b; /*!< Structure used for bit access */
348 uint32_t w; /*!< Type used for word access */
349 } CONTROL_Type;
350
351 /* CONTROL Register Definitions */
352 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
353 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
354
355 /*@} end of group CMSIS_CORE */
356
357
358 /**
359 \ingroup CMSIS_core_register
360 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
361 \brief Type definitions for the NVIC Registers
362 @{
363 */
364
365 /**
366 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
367 */
368 typedef struct
369 {
370 __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
371 uint32_t RESERVED0[31U];
372 __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
373 uint32_t RSERVED1[31U];
374 __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
375 uint32_t RESERVED2[31U];
376 __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
377 uint32_t RESERVED3[31U];
378 uint32_t RESERVED4[64U];
379 __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
380 } NVIC_Type;
381
382 /*@} end of group CMSIS_NVIC */
383
384
385 /**
386 \ingroup CMSIS_core_register
387 \defgroup CMSIS_SCB System Control Block (SCB)
388 \brief Type definitions for the System Control Block Registers
389 @{
390 */
391
392 /**
393 \brief Structure type to access the System Control Block (SCB).
394 */
395 typedef struct
396 {
397 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
398 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
399 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
400 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
401 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
402 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
403 uint32_t RESERVED0[1U];
404 __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
405 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
406 uint32_t RESERVED1[154U];
407 __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
408 } SCB_Type;
409
410 /* SCB CPUID Register Definitions */
411 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
412 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
413
414 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
415 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
416
417 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
418 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
419
420 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
421 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
422
423 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
424 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
425
426 /* SCB Interrupt Control State Register Definitions */
427 #define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
428 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
429
430 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
431 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
432
433 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
434 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
435
436 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
437 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
438
439 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
440 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
441
442 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
443 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
444
445 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
446 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
447
448 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
449 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
450
451 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
452 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
453
454 /* SCB Interrupt Control State Register Definitions */
455 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
456 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
457
458 /* SCB Application Interrupt and Reset Control Register Definitions */
459 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
460 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
461
462 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
463 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
464
465 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
466 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
467
468 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
469 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
470
471 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
472 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
473
474 /* SCB System Control Register Definitions */
475 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
476 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
477
478 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
479 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
480
481 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
482 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
483
484 /* SCB Configuration Control Register Definitions */
485 #define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
486 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
487
488 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
489 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
490
491 /* SCB System Handler Control and State Register Definitions */
492 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
493 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
494
495 /*@} end of group CMSIS_SCB */
496
497
498 /**
499 \ingroup CMSIS_core_register
500 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
501 \brief Type definitions for the System Control and ID Register not in the SCB
502 @{
503 */
504
505 /**
506 \brief Structure type to access the System Control and ID Register not in the SCB.
507 */
508 typedef struct
509 {
510 uint32_t RESERVED0[2U];
511 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
512 } SCnSCB_Type;
513
514 /* Auxiliary Control Register Definitions */
515 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
516 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
517
518 /*@} end of group CMSIS_SCnotSCB */
519
520
521 /**
522 \ingroup CMSIS_core_register
523 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
524 \brief Type definitions for the System Timer Registers.
525 @{
526 */
527
528 /**
529 \brief Structure type to access the System Timer (SysTick).
530 */
531 typedef struct
532 {
533 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
534 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
535 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
536 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
537 } SysTick_Type;
538
539 /* SysTick Control / Status Register Definitions */
540 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
541 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
542
543 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
544 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
545
546 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
547 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
548
549 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
550 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
551
552 /* SysTick Reload Register Definitions */
553 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
554 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
555
556 /* SysTick Current Register Definitions */
557 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
558 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
559
560 /* SysTick Calibration Register Definitions */
561 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
562 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
563
564 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
565 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
566
567 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
568 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
569
570 /*@} end of group CMSIS_SysTick */
571
572 #if (__MPU_PRESENT == 1U)
573 /**
574 \ingroup CMSIS_core_register
575 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
576 \brief Type definitions for the Memory Protection Unit (MPU)
577 @{
578 */
579
580 /**
581 \brief Structure type to access the Memory Protection Unit (MPU).
582 */
583 typedef struct
584 {
585 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
586 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
587 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
588 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
589 __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
590 } MPU_Type;
591
592 /* MPU Type Register Definitions */
593 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
594 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
595
596 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
597 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
598
599 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
600 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
601
602 /* MPU Control Register Definitions */
603 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
604 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
605
606 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
607 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
608
609 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
610 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
611
612 /* MPU Region Number Register Definitions */
613 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
614 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
615
616 /* MPU Region Base Address Register Definitions */
617 #define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */
618 #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
619
620 #define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
621 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
622
623 #define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
624 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
625
626 /* MPU Region Attribute and Size Register Definitions */
627 #define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
628 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
629
630 #define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
631 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
632
633 #define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
634 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
635
636 #define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
637 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
638
639 #define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
640 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
641
642 #define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
643 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
644
645 #define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
646 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
647
648 #define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
649 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
650
651 #define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
652 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
653
654 #define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
655 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
656
657 /*@} end of group CMSIS_MPU */
658 #endif
659
660
661 /**
662 \ingroup CMSIS_core_register
663 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
664 \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
665 Therefore they are not covered by the SC000 header file.
666 @{
667 */
668 /*@} end of group CMSIS_CoreDebug */
669
670
671 /**
672 \ingroup CMSIS_core_register
673 \defgroup CMSIS_core_bitfield Core register bit field macros
674 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
675 @{
676 */
677
678 /**
679 \brief Mask and shift a bit field value for use in a register bit range.
680 \param[in] field Name of the register bit field.
681 \param[in] value Value of the bit field.
682 \return Masked and shifted value.
683 */
684 #define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
685
686 /**
687 \brief Mask and shift a register value to extract a bit filed value.
688 \param[in] field Name of the register bit field.
689 \param[in] value Value of register.
690 \return Masked and shifted bit field value.
691 */
692 #define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
693
694 /*@} end of group CMSIS_core_bitfield */
695
696
697 /**
698 \ingroup CMSIS_core_register
699 \defgroup CMSIS_core_base Core Definitions
700 \brief Definitions for base addresses, unions, and structures.
701 @{
702 */
703
704 /* Memory mapping of SC000 Hardware */
705 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
706 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
707 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
708 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
709
710 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
711 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
712 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
713 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
714
715 #if (__MPU_PRESENT == 1U)
716 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
717 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
718 #endif
719
720 /*@} */
721
722
723
724 /*******************************************************************************
725 * Hardware Abstraction Layer
726 Core Function Interface contains:
727 - Core NVIC Functions
728 - Core SysTick Functions
729 - Core Register Access Functions
730 ******************************************************************************/
731 /**
732 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
733 */
734
735
736
737 /* ########################## NVIC functions #################################### */
738 /**
739 \ingroup CMSIS_Core_FunctionInterface
740 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
741 \brief Functions that manage interrupts and exceptions via the NVIC.
742 @{
743 */
744
745 /* Interrupt Priorities are WORD accessible only under ARMv6M */
746 /* The following MACROS handle generation of the register offset and byte masks */
747 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
748 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
749 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
750
751
752 /**
753 \brief Enable External Interrupt
754 \details Enables a device-specific interrupt in the NVIC interrupt controller.
755 \param [in] IRQn External interrupt number. Value cannot be negative.
756 */
NVIC_EnableIRQ(IRQn_Type IRQn)757 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
758 {
759 NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
760 }
761
762
763 /**
764 \brief Disable External Interrupt
765 \details Disables a device-specific interrupt in the NVIC interrupt controller.
766 \param [in] IRQn External interrupt number. Value cannot be negative.
767 */
NVIC_DisableIRQ(IRQn_Type IRQn)768 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
769 {
770 NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
771 }
772
773
774 /**
775 \brief Get Pending Interrupt
776 \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
777 \param [in] IRQn Interrupt number.
778 \return 0 Interrupt status is not pending.
779 \return 1 Interrupt status is pending.
780 */
NVIC_GetPendingIRQ(IRQn_Type IRQn)781 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
782 {
783 return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
784 }
785
786
787 /**
788 \brief Set Pending Interrupt
789 \details Sets the pending bit of an external interrupt.
790 \param [in] IRQn Interrupt number. Value cannot be negative.
791 */
NVIC_SetPendingIRQ(IRQn_Type IRQn)792 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
793 {
794 NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
795 }
796
797
798 /**
799 \brief Clear Pending Interrupt
800 \details Clears the pending bit of an external interrupt.
801 \param [in] IRQn External interrupt number. Value cannot be negative.
802 */
NVIC_ClearPendingIRQ(IRQn_Type IRQn)803 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
804 {
805 NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
806 }
807
808
809 /**
810 \brief Set Interrupt Priority
811 \details Sets the priority of an interrupt.
812 \note The priority cannot be set for every core interrupt.
813 \param [in] IRQn Interrupt number.
814 \param [in] priority Priority to set.
815 */
NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)816 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
817 {
818 if ((int32_t)(IRQn) < 0)
819 {
820 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
821 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
822 }
823 else
824 {
825 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
826 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
827 }
828 }
829
830
831 /**
832 \brief Get Interrupt Priority
833 \details Reads the priority of an interrupt.
834 The interrupt number can be positive to specify an external (device specific) interrupt,
835 or negative to specify an internal (core) interrupt.
836 \param [in] IRQn Interrupt number.
837 \return Interrupt Priority.
838 Value is aligned automatically to the implemented priority bits of the microcontroller.
839 */
NVIC_GetPriority(IRQn_Type IRQn)840 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
841 {
842
843 if ((int32_t)(IRQn) < 0)
844 {
845 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
846 }
847 else
848 {
849 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
850 }
851 }
852
853
854 /**
855 \brief System Reset
856 \details Initiates a system reset request to reset the MCU.
857 */
NVIC_SystemReset(void)858 __STATIC_INLINE void NVIC_SystemReset(void)
859 {
860 __DSB(); /* Ensure all outstanding memory accesses included
861 buffered write are completed before reset */
862 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
863 SCB_AIRCR_SYSRESETREQ_Msk);
864 __DSB(); /* Ensure completion of memory access */
865
866 for(;;) /* wait until reset */
867 {
868 __NOP();
869 }
870 }
871
872 /*@} end of CMSIS_Core_NVICFunctions */
873
874
875
876 /* ################################## SysTick function ############################################ */
877 /**
878 \ingroup CMSIS_Core_FunctionInterface
879 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
880 \brief Functions that configure the System.
881 @{
882 */
883
884 #if (__Vendor_SysTickConfig == 0U)
885
886 /**
887 \brief System Tick Configuration
888 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
889 Counter is in free running mode to generate periodic interrupts.
890 \param [in] ticks Number of ticks between two interrupts.
891 \return 0 Function succeeded.
892 \return 1 Function failed.
893 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
894 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
895 must contain a vendor-specific implementation of this function.
896 */
SysTick_Config(uint32_t ticks)897 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
898 {
899 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
900 {
901 return (1UL); /* Reload value impossible */
902 }
903
904 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
905 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
906 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
907 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
908 SysTick_CTRL_TICKINT_Msk |
909 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
910 return (0UL); /* Function successful */
911 }
912
913 #endif
914
915 /*@} end of CMSIS_Core_SysTickFunctions */
916
917
918
919
920 #ifdef __cplusplus
921 }
922 #endif
923
924 #endif /* __CORE_SC000_H_DEPENDANT */
925
926 #endif /* __CMSIS_GENERIC */
927
