1 /** 2 * \file 3 * 4 * \brief Instance description for ADC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_ADC_INSTANCE_ 30 #define _SAML21_ADC_INSTANCE_ 31 32 /* ========== Register definition for ADC peripheral ========== */ 33 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 34 #define REG_ADC_CTRLA (0x43000C00) /**< \brief (ADC) Control A */ 35 #define REG_ADC_CTRLB (0x43000C01) /**< \brief (ADC) Control B */ 36 #define REG_ADC_REFCTRL (0x43000C02) /**< \brief (ADC) Reference Control */ 37 #define REG_ADC_EVCTRL (0x43000C03) /**< \brief (ADC) Event Control */ 38 #define REG_ADC_INTENCLR (0x43000C04) /**< \brief (ADC) Interrupt Enable Clear */ 39 #define REG_ADC_INTENSET (0x43000C05) /**< \brief (ADC) Interrupt Enable Set */ 40 #define REG_ADC_INTFLAG (0x43000C06) /**< \brief (ADC) Interrupt Flag Status and Clear */ 41 #define REG_ADC_SEQSTATUS (0x43000C07) /**< \brief (ADC) Sequence Status */ 42 #define REG_ADC_INPUTCTRL (0x43000C08) /**< \brief (ADC) Input Control */ 43 #define REG_ADC_CTRLC (0x43000C0A) /**< \brief (ADC) Control C */ 44 #define REG_ADC_AVGCTRL (0x43000C0C) /**< \brief (ADC) Average Control */ 45 #define REG_ADC_SAMPCTRL (0x43000C0D) /**< \brief (ADC) Sample Time Control */ 46 #define REG_ADC_WINLT (0x43000C0E) /**< \brief (ADC) Window Monitor Lower Threshold */ 47 #define REG_ADC_WINUT (0x43000C10) /**< \brief (ADC) Window Monitor Upper Threshold */ 48 #define REG_ADC_GAINCORR (0x43000C12) /**< \brief (ADC) Gain Correction */ 49 #define REG_ADC_OFFSETCORR (0x43000C14) /**< \brief (ADC) Offset Correction */ 50 #define REG_ADC_SWTRIG (0x43000C18) /**< \brief (ADC) Software Trigger */ 51 #define REG_ADC_DBGCTRL (0x43000C1C) /**< \brief (ADC) Debug Control */ 52 #define REG_ADC_SYNCBUSY (0x43000C20) /**< \brief (ADC) Synchronization Busy */ 53 #define REG_ADC_RESULT (0x43000C24) /**< \brief (ADC) Result */ 54 #define REG_ADC_SEQCTRL (0x43000C28) /**< \brief (ADC) Sequence Control */ 55 #define REG_ADC_CALIB (0x43000C2C) /**< \brief (ADC) Calibration */ 56 #else 57 #define REG_ADC_CTRLA (*(RwReg8 *)0x43000C00UL) /**< \brief (ADC) Control A */ 58 #define REG_ADC_CTRLB (*(RwReg8 *)0x43000C01UL) /**< \brief (ADC) Control B */ 59 #define REG_ADC_REFCTRL (*(RwReg8 *)0x43000C02UL) /**< \brief (ADC) Reference Control */ 60 #define REG_ADC_EVCTRL (*(RwReg8 *)0x43000C03UL) /**< \brief (ADC) Event Control */ 61 #define REG_ADC_INTENCLR (*(RwReg8 *)0x43000C04UL) /**< \brief (ADC) Interrupt Enable Clear */ 62 #define REG_ADC_INTENSET (*(RwReg8 *)0x43000C05UL) /**< \brief (ADC) Interrupt Enable Set */ 63 #define REG_ADC_INTFLAG (*(RwReg8 *)0x43000C06UL) /**< \brief (ADC) Interrupt Flag Status and Clear */ 64 #define REG_ADC_SEQSTATUS (*(RoReg8 *)0x43000C07UL) /**< \brief (ADC) Sequence Status */ 65 #define REG_ADC_INPUTCTRL (*(RwReg16*)0x43000C08UL) /**< \brief (ADC) Input Control */ 66 #define REG_ADC_CTRLC (*(RwReg16*)0x43000C0AUL) /**< \brief (ADC) Control C */ 67 #define REG_ADC_AVGCTRL (*(RwReg8 *)0x43000C0CUL) /**< \brief (ADC) Average Control */ 68 #define REG_ADC_SAMPCTRL (*(RwReg8 *)0x43000C0DUL) /**< \brief (ADC) Sample Time Control */ 69 #define REG_ADC_WINLT (*(RwReg16*)0x43000C0EUL) /**< \brief (ADC) Window Monitor Lower Threshold */ 70 #define REG_ADC_WINUT (*(RwReg16*)0x43000C10UL) /**< \brief (ADC) Window Monitor Upper Threshold */ 71 #define REG_ADC_GAINCORR (*(RwReg16*)0x43000C12UL) /**< \brief (ADC) Gain Correction */ 72 #define REG_ADC_OFFSETCORR (*(RwReg16*)0x43000C14UL) /**< \brief (ADC) Offset Correction */ 73 #define REG_ADC_SWTRIG (*(RwReg8 *)0x43000C18UL) /**< \brief (ADC) Software Trigger */ 74 #define REG_ADC_DBGCTRL (*(RwReg8 *)0x43000C1CUL) /**< \brief (ADC) Debug Control */ 75 #define REG_ADC_SYNCBUSY (*(RoReg16*)0x43000C20UL) /**< \brief (ADC) Synchronization Busy */ 76 #define REG_ADC_RESULT (*(RoReg16*)0x43000C24UL) /**< \brief (ADC) Result */ 77 #define REG_ADC_SEQCTRL (*(RwReg *)0x43000C28UL) /**< \brief (ADC) Sequence Control */ 78 #define REG_ADC_CALIB (*(RwReg16*)0x43000C2CUL) /**< \brief (ADC) Calibration */ 79 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 /* ========== Instance parameters for ADC peripheral ========== */ 82 #define ADC_DMAC_ID_RESRDY 37 // index of DMA RESRDY trigger 83 #define ADC_EXTCHANNEL_MSB 19 // Number of external channels 84 #define ADC_GCLK_ID 30 // index of Generic Clock 85 #define ADC_RESULT_BITS 16 // Size of RESULT.RESULT bitfield 86 #define ADC_RESULT_MSB 15 // Size of Result 87 88 #endif /* _SAML21_ADC_INSTANCE_ */ 89
