1 /** 2 * \file 3 * 4 * \brief SPI Slave Async related functionality declaration. 5 * 6 * Copyright (C) 2015 Atmel Corporation. All rights reserved. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above copyright notice, 16 * this list of conditions and the following disclaimer. 17 * 18 * 2. Redistributions in binary form must reproduce the above copyright notice, 19 * this list of conditions and the following disclaimer in the documentation 20 * and/or other materials provided with the distribution. 21 * 22 * 3. The name of Atmel may not be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * 4. This software may only be redistributed and used in connection with an 26 * Atmel microcontroller product. 27 * 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 * 40 * \asf_license_stop 41 * 42 */ 43 44 #ifndef _HPL_SPI_M_ASYNC_H_INCLUDED 45 #define _HPL_SPI_M_ASYNC_H_INCLUDED 46 47 #include <hpl_spi.h> 48 #include <hpl_spi_async.h> 49 50 /** 51 * \addtogroup hpl_spi HPL SPI 52 * 53 * 54 *@{ 55 */ 56 57 #ifdef __cplusplus 58 extern "C" { 59 #endif 60 61 /** Uses common SPI async device driver. */ 62 #define _spi_m_async_dev _spi_async_dev 63 64 #define _spi_m_async_dev_cb_type _spi_async_dev_cb_type 65 66 /** Uses common SPI async device driver complete callback type. */ 67 #define _spi_m_async_dev_cb_complete_t _spi_async_dev_cb_complete_t 68 69 /** Uses common SPI async device driver transfer callback type. */ 70 #define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t 71 72 /** 73 * \brief Initialize SPI for access with interrupts 74 * It will load default hardware configuration and software struct. 75 * \param[in, out] dev Pointer to the SPI device instance. 76 * \param[in] hw Pointer to the hardware base. 77 * \retval ERR_INVALID_ARG Input parameter problem. 78 * \retval ERR_BUSY SPI hardware not ready (resetting). 79 * \retval ERR_DENIED SPI has been enabled. 80 * \retval 0 Operation done successfully. 81 */ 82 int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); 83 84 /** 85 * \brief Initialize SPI for access with interrupts 86 * Disable, reset the hardware and the software struct. 87 * \param[in, out] dev Pointer to the SPI device instance. 88 * \return Operation status. 89 * \retval 0 Operation done successfully. 90 */ 91 int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); 92 93 /** 94 * \brief Enable SPI for access with interrupts 95 * Enable the SPI and enable callback generation of receive and error 96 * interrupts. 97 * \param[in, out] dev Pointer to the SPI device instance. 98 * \return Operation status. 99 * \retval ERR_INVALID_ARG Input parameter problem. 100 * \retval ERR_BUSY SPI hardware not ready (resetting). 101 * \retval 0 Operation done successfully. 102 */ 103 int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); 104 105 /** 106 * \brief Disable SPI for access without interrupts 107 * Disable SPI and interrupts. Deactivate all CS pins if works as master. 108 * \param[in, out] dev Pointer to the SPI device instance. 109 * \return Operation status. 110 * \retval 0 Operation done successfully. 111 */ 112 int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); 113 114 /** 115 * \brief Set SPI transfer mode 116 * Set SPI transfer mode (\ref spi_transfer_mode), 117 * which controls clock polarity and clock phase. 118 * Mode 0: leading edge is rising edge, data sample on leading edge. 119 * Mode 1: leading edge is rising edge, data sample on trailing edge. 120 * Mode 2: leading edge is falling edge, data sample on leading edge. 121 * Mode 3: leading edge is falling edge, data sample on trailing edge. 122 * \param[in, out] dev Pointer to the SPI device instance. 123 * \param[in] mode The SPI transfer mode. 124 * \return Operation status. 125 * \retval ERR_BUSY SPI is not ready to accept new setting. 126 * \retval 0 Operation done successfully. 127 */ 128 int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); 129 130 /** 131 * \brief Set SPI baudrate 132 * \param[in, out] dev Pointer to the SPI device instance. 133 * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on 134 * how it's generated. 135 * \return Operation status. 136 * \retval ERR_BUSY SPI is not ready to accept new setting. 137 * \retval 0 Operation done successfully. 138 */ 139 int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); 140 141 /** 142 * \brief Set SPI baudrate 143 * \param[in, out] dev Pointer to the SPI device instance. 144 * \param[in] char_size The character size, see \ref spi_char_size. 145 * \return Operation status. 146 * \retval ERR_INVALID_ARG The character size is not supported. 147 * \retval ERR_BUSY SPI is not ready to accept new setting. 148 * \retval 0 Operation done successfully. 149 */ 150 int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); 151 152 /** 153 * \brief Set SPI data order 154 * \param[in, out] dev Pointer to the SPI device instance. 155 * \param[in] dord SPI data order (LSB/MSB first). 156 * \return Operation status. 157 * \retval ERR_INVALID_ARG The character size is not supported. 158 * \retval ERR_BUSY SPI is not ready to accept new setting. 159 * \retval 0 Operation done successfully. 160 */ 161 int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); 162 163 /** 164 * \brief Enable interrupt on character output 165 * 166 * Enable interrupt when a new character can be written 167 * to the SPI device. 168 * 169 * \param[in] dev Pointer to the SPI device instance 170 * \param[in] state true = enable output interrupt 171 * false = disable output interrupt 172 * 173 * \return Status code 174 * \retval 0 Ok status 175 */ 176 int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); 177 178 /** 179 * \brief Enable interrupt on character input 180 * 181 * Enable interrupt when a new character is ready to be 182 * read from the SPI device. 183 * 184 * \param[in] dev Pointer to the SPI device instance 185 * \param[in] state true = enable input interrupts 186 * false = disable input interrupt 187 * 188 * \return Status code 189 * \retvat 0 OK Status 190 */ 191 int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); 192 193 /** 194 * \brief Enable interrupt on Slave Select (SS) rising 195 * 196 * \param[in] dev Pointer to the SPI device instance 197 * \param[in] state true = enable input interrupts 198 * false = disable input interrupt 199 * 200 * \return Status code 201 * \retvat 0 OK Status 202 */ 203 int32_t _spi_m_async_enable_ss_detect(struct _spi_m_async_dev *dev, bool state); 204 205 /** 206 * \brief Read one character to SPI device instance 207 * \param[in, out] dev Pointer to the SPI device instance. 208 * 209 * \return Character read from SPI module 210 */ 211 uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); 212 213 /** 214 * \brief Write one character to assigned buffer 215 * \param[in, out] dev Pointer to the SPI device instance. 216 * \param[in] data 217 * 218 * \return Status code of write operation 219 * \retval 0 Write operation OK 220 */ 221 int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); 222 223 /** 224 * \brief Register the SPI device callback 225 * \param[in, out] dev Pointer to the SPI device instance. 226 * \param[in] cb_type The callback type. 227 * \param[in] func The callback function to register. NULL to disable callback. 228 * \return Always 0. 229 */ 230 int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, 231 const FUNC_PTR func); 232 233 /** 234 * \brief Enable/disable SPI master interrupt 235 * 236 * param[in] device The pointer to SPI master device instance 237 * param[in] type The type of interrupt to disable/enable if applicable 238 * param[in] state Enable or disable 239 */ 240 void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, 241 const bool state); 242 243 #ifdef __cplusplus 244 } 245 #endif 246 247 /**@}*/ 248 #endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ 249
