1 /**
2   ******************************************************************************
3   * @file    stm32l152xc.h
4   * @author  MCD Application Team
5   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
6   *          This file contains all the peripheral register's definitions, bits
7   *          definitions and memory mapping for STM32L1xx devices.
8   *
9   *          This file contains:
10   *           - Data structures and the address mapping for all peripherals
11   *           - Peripheral's registers declarations and bits definition
12   *           - Macros to access peripheral�s registers hardware
13   *
14   ******************************************************************************
15   * @attention
16   *
17   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
18   *
19   * Redistribution and use in source and binary forms, with or without modification,
20   * are permitted provided that the following conditions are met:
21   *   1. Redistributions of source code must retain the above copyright notice,
22   *      this list of conditions and the following disclaimer.
23   *   2. Redistributions in binary form must reproduce the above copyright notice,
24   *      this list of conditions and the following disclaimer in the documentation
25   *      and/or other materials provided with the distribution.
26   *   3. Neither the name of STMicroelectronics nor the names of its contributors
27   *      may be used to endorse or promote products derived from this software
28   *      without specific prior written permission.
29   *
30   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
31   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
32   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
33   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
34   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
35   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
36   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
37   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
38   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40   *
41   ******************************************************************************
42   */
43 
44 /** @addtogroup CMSIS
45   * @{
46   */
47 
48 /** @addtogroup stm32l152xc
49   * @{
50   */
51 
52 #ifndef __STM32L152xC_H
53 #define __STM32L152xC_H
54 
55 #ifdef __cplusplus
56  extern "C" {
57 #endif
58 
59 
60   /** @addtogroup Configuration_section_for_CMSIS
61   * @{
62   */
63 /**
64   * @brief Configuration of the Cortex-M3 Processor and Core Peripherals
65  */
66 #define __CM3_REV                 0x200U /*!< Cortex-M3 Revision r2p0                  */
67 #define __MPU_PRESENT             1U     /*!< STM32L1xx provides MPU                          */
68 #define __NVIC_PRIO_BITS          4U     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
69 #define __Vendor_SysTickConfig    0U     /*!< Set to 1 if different SysTick Config is used */
70 
71 /**
72   * @}
73   */
74 
75 /** @addtogroup Peripheral_interrupt_number_definition
76   * @{
77   */
78 
79 /**
80  * @brief STM32L1xx Interrupt Number Definition, according to the selected device
81  *        in @ref Library_configuration_section
82  */
83 
84  /*!< Interrupt Number Definition */
85 typedef enum
86 {
87 /******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
88   NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
89   HardFault_IRQn              = -13,    /*!< 3 Cortex-M3 Hard Fault Interrupt                        */
90   MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
91   BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
92   UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
93   SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
94   DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
95   PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
96   SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
97 
98 /******  STM32L specific Interrupt Numbers ***********************************************************/
99   WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
100   PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
101   TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
102   RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
103   FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
104   RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
105   EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
106   EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
107   EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
108   EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
109   EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
110   DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
111   DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
112   DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
113   DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
114   DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
115   DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
116   DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
117   ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
118   USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
119   USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
120   DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
121   COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
122   EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
123   LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
124   TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
125   TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
126   TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
127   TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
128   TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
129   TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
130   I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
131   I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
132   I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
133   I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
134   SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
135   SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
136   USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
137   USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
138   USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
139   EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
140   RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
141   USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
142   TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
143   TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
144   TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
145   SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
146   DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
147   DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
148   DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
149   DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
150   DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
151   COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
152 } IRQn_Type;
153 
154 /**
155   * @}
156   */
157 
158 #include "core_cm3.h"
159 #include "system_stm32l1xx.h"
160 #include <stdint.h>
161 
162 /** @addtogroup Peripheral_registers_structures
163   * @{
164   */
165 
166 /**
167   * @brief Analog to Digital Converter
168   */
169 
170 typedef struct
171 {
172   __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
173   __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
174   __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
175   __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
176   __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
177   __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
178   __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
179   __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
180   __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
181   __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
182   __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
183   __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
184   __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
185   __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
186   __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
187   __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
188   __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
189   __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
190   __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
191   __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
192   __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
193   __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
194   __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
195   uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
196 } ADC_TypeDef;
197 
198 typedef struct
199 {
200   __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
201   __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
202 } ADC_Common_TypeDef;
203 
204 /**
205   * @brief Comparator
206   */
207 
208 typedef struct
209 {
210   __IO uint32_t CSR;         /*!< COMP control and status register, Address offset: 0x00 */
211 } COMP_TypeDef;
212 
213 typedef struct
214 {
215   __IO uint32_t CSR;         /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
216 } COMP_Common_TypeDef;
217 
218 /**
219   * @brief CRC calculation unit
220   */
221 
222 typedef struct
223 {
224   __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
225   __IO uint8_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
226   uint8_t       RESERVED0;    /*!< Reserved,                                    Address offset: 0x05 */
227   uint16_t      RESERVED1;    /*!< Reserved,                                    Address offset: 0x06 */
228   __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */
229 } CRC_TypeDef;
230 
231 /**
232   * @brief Digital to Analog Converter
233   */
234 
235 typedef struct
236 {
237   __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
238   __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
239   __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
240   __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
241   __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
242   __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
243   __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
244   __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
245   __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
246   __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
247   __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
248   __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
249   __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
250   __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
251 } DAC_TypeDef;
252 
253 /**
254   * @brief Debug MCU
255   */
256 
257 typedef struct
258 {
259   __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
260   __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
261   __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
262   __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
263 }DBGMCU_TypeDef;
264 
265 /**
266   * @brief DMA Controller
267   */
268 
269 typedef struct
270 {
271   __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
272   __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
273   __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
274   __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
275 } DMA_Channel_TypeDef;
276 
277 typedef struct
278 {
279   __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
280   __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
281 } DMA_TypeDef;
282 
283 /**
284   * @brief External Interrupt/Event Controller
285   */
286 
287 typedef struct
288 {
289   __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
290   __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
291   __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
292   __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
293   __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
294   __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
295 } EXTI_TypeDef;
296 
297 /**
298   * @brief FLASH Registers
299   */
300 typedef struct
301 {
302   __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
303   __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
304   __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
305   __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
306   __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
307   __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
308   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
309   __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
310   __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
311   uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
312   __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
313 } FLASH_TypeDef;
314 
315 /**
316   * @brief Option Bytes Registers
317   */
318 typedef struct
319 {
320   __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
321   __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
322   __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
323   __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
324   __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
325   __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
326 } OB_TypeDef;
327 
328 /**
329   * @brief Operational Amplifier (OPAMP)
330   */
331 typedef struct
332 {
333   __IO uint32_t CSR;          /*!< OPAMP control and status register,                 Address offset: 0x00 */
334   __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */
335   __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
336 } OPAMP_TypeDef;
337 
338 typedef struct
339 {
340   __IO uint32_t CSR;          /*!< OPAMP control and status register, used for bits common to several OPAMP instances,              Address offset: 0x00 */
341   __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode, used for bits common to several OPAMP instances, Address offset: 0x04 */
342 } OPAMP_Common_TypeDef;
343 
344 /**
345   * @brief General Purpose IO
346   */
347 
348 typedef struct
349 {
350   __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
351   __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
352   __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
353   __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
354   __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
355   __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
356   __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
357   __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
358   __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
359   __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
360 } GPIO_TypeDef;
361 
362 /**
363   * @brief SysTem Configuration
364   */
365 
366 typedef struct
367 {
368   __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
369   __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
370   __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
371 } SYSCFG_TypeDef;
372 
373 /**
374   * @brief Inter-integrated Circuit Interface
375   */
376 
377 typedef struct
378 {
379   __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
380   __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
381   __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
382   __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
383   __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
384   __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
385   __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
386   __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
387   __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
388 } I2C_TypeDef;
389 
390 /**
391   * @brief Independent WATCHDOG
392   */
393 
394 typedef struct
395 {
396   __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
397   __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
398   __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
399   __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
400 } IWDG_TypeDef;
401 
402 /**
403   * @brief LCD
404   */
405 
406 typedef struct
407 {
408   __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
409   __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
410   __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
411   __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
412   uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
413   __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
414 } LCD_TypeDef;
415 
416 /**
417   * @brief Power Control
418   */
419 
420 typedef struct
421 {
422   __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
423   __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
424 } PWR_TypeDef;
425 
426 /**
427   * @brief Reset and Clock Control
428   */
429 
430 typedef struct
431 {
432   __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
433   __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
434   __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
435   __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
436   __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
437   __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
438   __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
439   __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
440   __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
441   __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
442   __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
443   __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
444   __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
445   __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
446 } RCC_TypeDef;
447 
448 /**
449   * @brief Routing Interface
450   */
451 
452 typedef struct
453 {
454   __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
455   __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
456   __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
457   __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
458   __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
459   __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
460   uint32_t RESERVED1;       /*!< Reserved, 0x18                                                                  */
461   __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
462   __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
463   __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
464   __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
465   __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
466   __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
467   __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
468   __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
469   __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
470 } RI_TypeDef;
471 
472 /**
473   * @brief Real-Time Clock
474   */
475 typedef struct
476 {
477   __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
478   __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
479   __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
480   __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
481   __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
482   __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
483   __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
484   __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
485   __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
486   __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
487   __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
488   __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
489   __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
490   __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
491   __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
492   __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
493   __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
494   __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
495   __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
496   uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
497   __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
498   __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
499   __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
500   __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
501   __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
502   __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
503   __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
504   __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
505   __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
506   __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
507   __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
508   __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
509   __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
510   __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
511   __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
512   __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
513   __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
514   __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
515   __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
516   __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
517   __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
518   __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
519   __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
520   __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
521   __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
522   __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
523   __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
524   __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
525   __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
526   __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
527   __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
528   __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
529 } RTC_TypeDef;
530 
531 /**
532   * @brief Serial Peripheral Interface
533   */
534 
535 typedef struct
536 {
537   __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
538   __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
539   __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
540   __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
541   __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
542   __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
543   __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
544   __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
545   __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
546 } SPI_TypeDef;
547 
548 /**
549   * @brief TIM
550   */
551 typedef struct
552 {
553   __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
554   __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
555   __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
556   __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
557   __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
558   __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
559   __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
560   __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
561   __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
562   __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
563   __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
564   __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
565   uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */
566   __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */
567   __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */
568   __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
569   __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
570   uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */
571   __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
572   __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
573   __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
574 } TIM_TypeDef;
575 /**
576   * @brief Universal Synchronous Asynchronous Receiver Transmitter
577   */
578 
579 typedef struct
580 {
581   __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
582   __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
583   __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
584   __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
585   __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
586   __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
587   __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
588 } USART_TypeDef;
589 
590 /**
591   * @brief Universal Serial Bus Full Speed Device
592   */
593 
594 typedef struct
595 {
596   __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */
597   __IO uint16_t RESERVED0;       /*!< Reserved */
598   __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
599   __IO uint16_t RESERVED1;       /*!< Reserved */
600   __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
601   __IO uint16_t RESERVED2;       /*!< Reserved */
602   __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */
603   __IO uint16_t RESERVED3;       /*!< Reserved */
604   __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
605   __IO uint16_t RESERVED4;       /*!< Reserved */
606   __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
607   __IO uint16_t RESERVED5;       /*!< Reserved */
608   __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
609   __IO uint16_t RESERVED6;       /*!< Reserved */
610   __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
611   __IO uint16_t RESERVED7[17];   /*!< Reserved */
612   __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
613   __IO uint16_t RESERVED8;       /*!< Reserved */
614   __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
615   __IO uint16_t RESERVED9;       /*!< Reserved */
616   __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
617   __IO uint16_t RESERVEDA;       /*!< Reserved */
618   __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
619   __IO uint16_t RESERVEDB;       /*!< Reserved */
620   __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
621   __IO uint16_t RESERVEDC;       /*!< Reserved */
622 } USB_TypeDef;
623 
624 /**
625   * @brief Window WATCHDOG
626   */
627 typedef struct
628 {
629   __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
630   __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
631   __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
632 } WWDG_TypeDef;
633 
634 /**
635   * @brief Universal Serial Bus Full Speed Device
636   */
637 /**
638   * @}
639   */
640 
641 /** @addtogroup Peripheral_memory_map
642   * @{
643   */
644 
645 #define FLASH_BASE            ((uint32_t)0x08000000U)              /*!< FLASH base address in the alias region */
646 #define FLASH_EEPROM_BASE     ((uint32_t)(FLASH_BASE + 0x80000U))  /*!< FLASH EEPROM base address in the alias region */
647 #define SRAM_BASE             ((uint32_t)0x20000000U)              /*!< SRAM base address in the alias region */
648 #define PERIPH_BASE           ((uint32_t)0x40000000U)              /*!< Peripheral base address in the alias region */
649 #define SRAM_BB_BASE          ((uint32_t)0x22000000U)              /*!< SRAM base address in the bit-band region */
650 #define PERIPH_BB_BASE        ((uint32_t)0x42000000U)              /*!< Peripheral base address in the bit-band region */
651 #define FLASH_END             ((uint32_t)0x0803FFFFU)              /*!< Program end FLASH address for Cat3 */
652 #define FLASH_EEPROM_END      ((uint32_t)0x08081FFFU)              /*!< FLASH EEPROM end address (8KB) */
653 
654 /*!< Peripheral memory map */
655 #define APB1PERIPH_BASE       PERIPH_BASE
656 #define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000U)
657 #define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000U)
658 
659 /*!< APB1 peripherals */
660 #define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000U)
661 #define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400U)
662 #define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800U)
663 #define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00U)
664 #define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000U)
665 #define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400U)
666 #define LCD_BASE              (APB1PERIPH_BASE + 0x00002400U)
667 #define RTC_BASE              (APB1PERIPH_BASE + 0x00002800U)
668 #define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00U)
669 #define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000U)
670 #define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800U)
671 #define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00U)
672 #define USART2_BASE           (APB1PERIPH_BASE + 0x00004400U)
673 #define USART3_BASE           (APB1PERIPH_BASE + 0x00004800U)
674 #define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400U)
675 #define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800U)
676 
677 /* USB device FS */
678 #define USB_BASE              (APB1PERIPH_BASE + 0x00005C00U) /*!< USB_IP Peripheral Registers base address */
679 #define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000U) /*!< USB_IP Packet Memory Area base address */
680 
681 /* USB device FS SRAM */
682 #define PWR_BASE              (APB1PERIPH_BASE + 0x00007000U)
683 #define DAC_BASE              (APB1PERIPH_BASE + 0x00007400U)
684 #define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00U)
685 #define RI_BASE               (APB1PERIPH_BASE + 0x00007C04U)
686 #define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5CU)
687 
688 /*!< APB2 peripherals */
689 #define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000U)
690 #define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400U)
691 #define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800U)
692 #define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00U)
693 #define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000U)
694 #define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400U)
695 #define ADC_BASE              (APB2PERIPH_BASE + 0x00002700U)
696 #define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000U)
697 #define USART1_BASE           (APB2PERIPH_BASE + 0x00003800U)
698 
699 /*!< AHB peripherals */
700 #define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000U)
701 #define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400U)
702 #define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800U)
703 #define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00U)
704 #define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000U)
705 #define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400U)
706 #define CRC_BASE              (AHBPERIPH_BASE + 0x00003000U)
707 #define RCC_BASE              (AHBPERIPH_BASE + 0x00003800U)
708 #define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00U) /*!< FLASH registers base address */
709 #define OB_BASE               ((uint32_t)0x1FF80000U)        /*!< FLASH Option Bytes base address */
710 #define FLASHSIZE_BASE        ((uint32_t)0x1FF800CCU)        /*!< FLASH Size register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
711 #define UID_BASE              ((uint32_t)0x1FF800D0U)        /*!< Unique device ID register base address for Cat.3, Cat.4, Cat.5 and Cat.6 devices */
712 #define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000U)
713 #define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008U)
714 #define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001CU)
715 #define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030U)
716 #define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044U)
717 #define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058U)
718 #define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006CU)
719 #define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080U)
720 #define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400U)
721 #define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008U)
722 #define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001CU)
723 #define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030U)
724 #define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044U)
725 #define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058U)
726 #define DBGMCU_BASE           ((uint32_t)0xE0042000U)     /*!< Debug MCU registers base address */
727 
728 /**
729   * @}
730   */
731 
732 /** @addtogroup Peripheral_declaration
733   * @{
734   */
735 
736 #define TIM2                ((TIM_TypeDef *) TIM2_BASE)
737 #define TIM3                ((TIM_TypeDef *) TIM3_BASE)
738 #define TIM4                ((TIM_TypeDef *) TIM4_BASE)
739 #define TIM5                ((TIM_TypeDef *) TIM5_BASE)
740 #define TIM6                ((TIM_TypeDef *) TIM6_BASE)
741 #define TIM7                ((TIM_TypeDef *) TIM7_BASE)
742 #define LCD                 ((LCD_TypeDef *) LCD_BASE)
743 #define RTC                 ((RTC_TypeDef *) RTC_BASE)
744 #define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
745 #define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
746 #define SPI2                ((SPI_TypeDef *) SPI2_BASE)
747 #define SPI3                ((SPI_TypeDef *) SPI3_BASE)
748 #define USART2              ((USART_TypeDef *) USART2_BASE)
749 #define USART3              ((USART_TypeDef *) USART3_BASE)
750 #define I2C1                ((I2C_TypeDef *) I2C1_BASE)
751 #define I2C2                ((I2C_TypeDef *) I2C2_BASE)
752 /* USB device FS */
753 #define USB                   ((USB_TypeDef *) USB_BASE)
754 /* USB device FS SRAM */
755 #define PWR                 ((PWR_TypeDef *) PWR_BASE)
756 
757 #define DAC1                ((DAC_TypeDef *) DAC_BASE)
758 /* Legacy define */
759 #define DAC                 DAC1
760 
761 #define COMP                ((COMP_TypeDef *) COMP_BASE)                 /* COMP generic instance include bits of COMP1 and COMP2 mixed in the same register */
762 #define COMP1               ((COMP_TypeDef *) COMP_BASE)                 /* COMP1 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
763 #define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001U)) /* COMP2 instance definition to differentiate COMP1 and COMP2, not to be used to access comparator register */
764 #define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP_BASE)          /* COMP common instance definition to access comparator register bits used by both comparator instances (window mode) */
765 
766 #define RI                  ((RI_TypeDef *) RI_BASE)
767 
768 #define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
769 #define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
770 #define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001U))
771 #define OPAMP12_COMMON      ((OPAMP_Common_TypeDef *) OPAMP_BASE)
772 #define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
773 #define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
774 #define TIM9                ((TIM_TypeDef *) TIM9_BASE)
775 #define TIM10               ((TIM_TypeDef *) TIM10_BASE)
776 #define TIM11               ((TIM_TypeDef *) TIM11_BASE)
777 
778 #define ADC1                ((ADC_TypeDef *) ADC1_BASE)
779 #define ADC1_COMMON         ((ADC_Common_TypeDef *) ADC_BASE)
780 /* Legacy defines */
781 #define ADC                 ADC1_COMMON
782 
783 #define SPI1                ((SPI_TypeDef *) SPI1_BASE)
784 #define USART1              ((USART_TypeDef *) USART1_BASE)
785 #define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
786 #define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
787 #define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
788 #define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
789 #define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
790 #define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
791 #define CRC                 ((CRC_TypeDef *) CRC_BASE)
792 #define RCC                 ((RCC_TypeDef *) RCC_BASE)
793 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
794 #define OB                  ((OB_TypeDef *) OB_BASE)
795 #define DMA1                ((DMA_TypeDef *) DMA1_BASE)
796 #define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
797 #define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
798 #define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
799 #define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
800 #define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
801 #define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
802 #define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
803 #define DMA2                ((DMA_TypeDef *) DMA2_BASE)
804 #define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
805 #define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
806 #define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
807 #define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
808 #define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
809 #define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
810 
811  /**
812   * @}
813   */
814 
815 /** @addtogroup Exported_constants
816   * @{
817   */
818 
819 /** @addtogroup Peripheral_Registers_Bits_Definition
820   * @{
821   */
822 
823 /******************************************************************************/
824 /*                         Peripheral Registers Bits Definition               */
825 /******************************************************************************/
826 /******************************************************************************/
827 /*                                                                            */
828 /*                      Analog to Digital Converter (ADC)                     */
829 /*                                                                            */
830 /******************************************************************************/
831 
832 /********************  Bit definition for ADC_SR register  ********************/
833 #define ADC_SR_AWD_Pos                       (0U)
834 #define ADC_SR_AWD_Msk                       (0x1U << ADC_SR_AWD_Pos)          /*!< 0x00000001 */
835 #define ADC_SR_AWD                           ADC_SR_AWD_Msk                    /*!< ADC analog watchdog 1 flag */
836 #define ADC_SR_EOCS_Pos                      (1U)
837 #define ADC_SR_EOCS_Msk                      (0x1U << ADC_SR_EOCS_Pos)         /*!< 0x00000002 */
838 #define ADC_SR_EOCS                          ADC_SR_EOCS_Msk                   /*!< ADC group regular end of unitary conversion or end of sequence conversions flag */
839 #define ADC_SR_JEOS_Pos                      (2U)
840 #define ADC_SR_JEOS_Msk                      (0x1U << ADC_SR_JEOS_Pos)         /*!< 0x00000004 */
841 #define ADC_SR_JEOS                          ADC_SR_JEOS_Msk                   /*!< ADC group injected end of sequence conversions flag */
842 #define ADC_SR_JSTRT_Pos                     (3U)
843 #define ADC_SR_JSTRT_Msk                     (0x1U << ADC_SR_JSTRT_Pos)        /*!< 0x00000008 */
844 #define ADC_SR_JSTRT                         ADC_SR_JSTRT_Msk                  /*!< ADC group injected conversion start flag */
845 #define ADC_SR_STRT_Pos                      (4U)
846 #define ADC_SR_STRT_Msk                      (0x1U << ADC_SR_STRT_Pos)         /*!< 0x00000010 */
847 #define ADC_SR_STRT                          ADC_SR_STRT_Msk                   /*!< ADC group regular conversion start flag */
848 #define ADC_SR_OVR_Pos                       (5U)
849 #define ADC_SR_OVR_Msk                       (0x1U << ADC_SR_OVR_Pos)          /*!< 0x00000020 */
850 #define ADC_SR_OVR                           ADC_SR_OVR_Msk                    /*!< ADC group regular overrun flag */
851 #define ADC_SR_ADONS_Pos                     (6U)
852 #define ADC_SR_ADONS_Msk                     (0x1U << ADC_SR_ADONS_Pos)        /*!< 0x00000040 */
853 #define ADC_SR_ADONS                         ADC_SR_ADONS_Msk                  /*!< ADC ready flag */
854 #define ADC_SR_RCNR_Pos                      (8U)
855 #define ADC_SR_RCNR_Msk                      (0x1U << ADC_SR_RCNR_Pos)         /*!< 0x00000100 */
856 #define ADC_SR_RCNR                          ADC_SR_RCNR_Msk                   /*!< ADC group regular not ready flag */
857 #define ADC_SR_JCNR_Pos                      (9U)
858 #define ADC_SR_JCNR_Msk                      (0x1U << ADC_SR_JCNR_Pos)         /*!< 0x00000200 */
859 #define ADC_SR_JCNR                          ADC_SR_JCNR_Msk                   /*!< ADC group injected not ready flag */
860 
861 /* Legacy defines */
862 #define  ADC_SR_EOC                          (ADC_SR_EOCS)
863 #define  ADC_SR_JEOC                         (ADC_SR_JEOS)
864 
865 /*******************  Bit definition for ADC_CR1 register  ********************/
866 #define ADC_CR1_AWDCH_Pos                    (0U)
867 #define ADC_CR1_AWDCH_Msk                    (0x1FU << ADC_CR1_AWDCH_Pos)      /*!< 0x0000001F */
868 #define ADC_CR1_AWDCH                        ADC_CR1_AWDCH_Msk                 /*!< ADC analog watchdog 1 monitored channel selection */
869 #define ADC_CR1_AWDCH_0                      (0x01U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000001 */
870 #define ADC_CR1_AWDCH_1                      (0x02U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000002 */
871 #define ADC_CR1_AWDCH_2                      (0x04U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000004 */
872 #define ADC_CR1_AWDCH_3                      (0x08U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000008 */
873 #define ADC_CR1_AWDCH_4                      (0x10U << ADC_CR1_AWDCH_Pos)      /*!< 0x00000010 */
874 
875 #define ADC_CR1_EOCSIE_Pos                   (5U)
876 #define ADC_CR1_EOCSIE_Msk                   (0x1U << ADC_CR1_EOCSIE_Pos)      /*!< 0x00000020 */
877 #define ADC_CR1_EOCSIE                       ADC_CR1_EOCSIE_Msk                /*!< ADC group regular end of unitary conversion or end of sequence conversions interrupt */
878 #define ADC_CR1_AWDIE_Pos                    (6U)
879 #define ADC_CR1_AWDIE_Msk                    (0x1U << ADC_CR1_AWDIE_Pos)       /*!< 0x00000040 */
880 #define ADC_CR1_AWDIE                        ADC_CR1_AWDIE_Msk                 /*!< ADC analog watchdog 1 interrupt */
881 #define ADC_CR1_JEOSIE_Pos                   (7U)
882 #define ADC_CR1_JEOSIE_Msk                   (0x1U << ADC_CR1_JEOSIE_Pos)      /*!< 0x00000080 */
883 #define ADC_CR1_JEOSIE                       ADC_CR1_JEOSIE_Msk                /*!< ADC group injected end of sequence conversions interrupt */
884 #define ADC_CR1_SCAN_Pos                     (8U)
885 #define ADC_CR1_SCAN_Msk                     (0x1U << ADC_CR1_SCAN_Pos)        /*!< 0x00000100 */
886 #define ADC_CR1_SCAN                         ADC_CR1_SCAN_Msk                  /*!< ADC scan mode */
887 #define ADC_CR1_AWDSGL_Pos                   (9U)
888 #define ADC_CR1_AWDSGL_Msk                   (0x1U << ADC_CR1_AWDSGL_Pos)      /*!< 0x00000200 */
889 #define ADC_CR1_AWDSGL                       ADC_CR1_AWDSGL_Msk                /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
890 #define ADC_CR1_JAUTO_Pos                    (10U)
891 #define ADC_CR1_JAUTO_Msk                    (0x1U << ADC_CR1_JAUTO_Pos)       /*!< 0x00000400 */
892 #define ADC_CR1_JAUTO                        ADC_CR1_JAUTO_Msk                 /*!< ADC group injected automatic trigger mode */
893 #define ADC_CR1_DISCEN_Pos                   (11U)
894 #define ADC_CR1_DISCEN_Msk                   (0x1U << ADC_CR1_DISCEN_Pos)      /*!< 0x00000800 */
895 #define ADC_CR1_DISCEN                       ADC_CR1_DISCEN_Msk                /*!< ADC group regular sequencer discontinuous mode */
896 #define ADC_CR1_JDISCEN_Pos                  (12U)
897 #define ADC_CR1_JDISCEN_Msk                  (0x1U << ADC_CR1_JDISCEN_Pos)     /*!< 0x00001000 */
898 #define ADC_CR1_JDISCEN                      ADC_CR1_JDISCEN_Msk               /*!< ADC group injected sequencer discontinuous mode */
899 
900 #define ADC_CR1_DISCNUM_Pos                  (13U)
901 #define ADC_CR1_DISCNUM_Msk                  (0x7U << ADC_CR1_DISCNUM_Pos)     /*!< 0x0000E000 */
902 #define ADC_CR1_DISCNUM                      ADC_CR1_DISCNUM_Msk               /*!< ADC group regular sequencer discontinuous number of ranks */
903 #define ADC_CR1_DISCNUM_0                    (0x1U << ADC_CR1_DISCNUM_Pos)     /*!< 0x00002000 */
904 #define ADC_CR1_DISCNUM_1                    (0x2U << ADC_CR1_DISCNUM_Pos)     /*!< 0x00004000 */
905 #define ADC_CR1_DISCNUM_2                    (0x4U << ADC_CR1_DISCNUM_Pos)     /*!< 0x00008000 */
906 
907 #define ADC_CR1_PDD_Pos                      (16U)
908 #define ADC_CR1_PDD_Msk                      (0x1U << ADC_CR1_PDD_Pos)         /*!< 0x00010000 */
909 #define ADC_CR1_PDD                          ADC_CR1_PDD_Msk                   /*!< ADC power down during auto delay phase */
910 #define ADC_CR1_PDI_Pos                      (17U)
911 #define ADC_CR1_PDI_Msk                      (0x1U << ADC_CR1_PDI_Pos)         /*!< 0x00020000 */
912 #define ADC_CR1_PDI                          ADC_CR1_PDI_Msk                   /*!< ADC power down during idle phase */
913 
914 #define ADC_CR1_JAWDEN_Pos                   (22U)
915 #define ADC_CR1_JAWDEN_Msk                   (0x1U << ADC_CR1_JAWDEN_Pos)      /*!< 0x00400000 */
916 #define ADC_CR1_JAWDEN                       ADC_CR1_JAWDEN_Msk                /*!< ADC analog watchdog 1 enable on scope ADC group injected */
917 #define ADC_CR1_AWDEN_Pos                    (23U)
918 #define ADC_CR1_AWDEN_Msk                    (0x1U << ADC_CR1_AWDEN_Pos)       /*!< 0x00800000 */
919 #define ADC_CR1_AWDEN                        ADC_CR1_AWDEN_Msk                 /*!< ADC analog watchdog 1 enable on scope ADC group regular */
920 
921 #define ADC_CR1_RES_Pos                      (24U)
922 #define ADC_CR1_RES_Msk                      (0x3U << ADC_CR1_RES_Pos)         /*!< 0x03000000 */
923 #define ADC_CR1_RES                          ADC_CR1_RES_Msk                   /*!< ADC resolution */
924 #define ADC_CR1_RES_0                        (0x1U << ADC_CR1_RES_Pos)         /*!< 0x01000000 */
925 #define ADC_CR1_RES_1                        (0x2U << ADC_CR1_RES_Pos)         /*!< 0x02000000 */
926 
927 #define ADC_CR1_OVRIE_Pos                    (26U)
928 #define ADC_CR1_OVRIE_Msk                    (0x1U << ADC_CR1_OVRIE_Pos)       /*!< 0x04000000 */
929 #define ADC_CR1_OVRIE                        ADC_CR1_OVRIE_Msk                 /*!< ADC group regular overrun interrupt */
930 
931 /* Legacy defines */
932 #define  ADC_CR1_EOCIE                       (ADC_CR1_EOCSIE)
933 #define  ADC_CR1_JEOCIE                      (ADC_CR1_JEOSIE)
934 
935 /*******************  Bit definition for ADC_CR2 register  ********************/
936 #define ADC_CR2_ADON_Pos                     (0U)
937 #define ADC_CR2_ADON_Msk                     (0x1U << ADC_CR2_ADON_Pos)        /*!< 0x00000001 */
938 #define ADC_CR2_ADON                         ADC_CR2_ADON_Msk                  /*!< ADC enable */
939 #define ADC_CR2_CONT_Pos                     (1U)
940 #define ADC_CR2_CONT_Msk                     (0x1U << ADC_CR2_CONT_Pos)        /*!< 0x00000002 */
941 #define ADC_CR2_CONT                         ADC_CR2_CONT_Msk                  /*!< ADC group regular continuous conversion mode */
942 #define ADC_CR2_CFG_Pos                      (2U)
943 #define ADC_CR2_CFG_Msk                      (0x1U << ADC_CR2_CFG_Pos)         /*!< 0x00000004 */
944 #define ADC_CR2_CFG                          ADC_CR2_CFG_Msk                   /*!< ADC channels bank selection */
945 
946 #define ADC_CR2_DELS_Pos                     (4U)
947 #define ADC_CR2_DELS_Msk                     (0x7U << ADC_CR2_DELS_Pos)        /*!< 0x00000070 */
948 #define ADC_CR2_DELS                         ADC_CR2_DELS_Msk                  /*!< ADC auto delay selection */
949 #define ADC_CR2_DELS_0                       (0x1U << ADC_CR2_DELS_Pos)        /*!< 0x00000010 */
950 #define ADC_CR2_DELS_1                       (0x2U << ADC_CR2_DELS_Pos)        /*!< 0x00000020 */
951 #define ADC_CR2_DELS_2                       (0x4U << ADC_CR2_DELS_Pos)        /*!< 0x00000040 */
952 
953 #define ADC_CR2_DMA_Pos                      (8U)
954 #define ADC_CR2_DMA_Msk                      (0x1U << ADC_CR2_DMA_Pos)         /*!< 0x00000100 */
955 #define ADC_CR2_DMA                          ADC_CR2_DMA_Msk                   /*!< ADC DMA transfer enable */
956 #define ADC_CR2_DDS_Pos                      (9U)
957 #define ADC_CR2_DDS_Msk                      (0x1U << ADC_CR2_DDS_Pos)         /*!< 0x00000200 */
958 #define ADC_CR2_DDS                          ADC_CR2_DDS_Msk                   /*!< ADC DMA transfer configuration */
959 #define ADC_CR2_EOCS_Pos                     (10U)
960 #define ADC_CR2_EOCS_Msk                     (0x1U << ADC_CR2_EOCS_Pos)        /*!< 0x00000400 */
961 #define ADC_CR2_EOCS                         ADC_CR2_EOCS_Msk                  /*!< ADC end of unitary or end of sequence conversions selection */
962 #define ADC_CR2_ALIGN_Pos                    (11U)
963 #define ADC_CR2_ALIGN_Msk                    (0x1U << ADC_CR2_ALIGN_Pos)       /*!< 0x00000800 */
964 #define ADC_CR2_ALIGN                        ADC_CR2_ALIGN_Msk                 /*!< ADC data alignement */
965 
966 #define ADC_CR2_JEXTSEL_Pos                  (16U)
967 #define ADC_CR2_JEXTSEL_Msk                  (0xFU << ADC_CR2_JEXTSEL_Pos)     /*!< 0x000F0000 */
968 #define ADC_CR2_JEXTSEL                      ADC_CR2_JEXTSEL_Msk               /*!< ADC group injected external trigger source */
969 #define ADC_CR2_JEXTSEL_0                    (0x1U << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00010000 */
970 #define ADC_CR2_JEXTSEL_1                    (0x2U << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00020000 */
971 #define ADC_CR2_JEXTSEL_2                    (0x4U << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00040000 */
972 #define ADC_CR2_JEXTSEL_3                    (0x8U << ADC_CR2_JEXTSEL_Pos)     /*!< 0x00080000 */
973 
974 #define ADC_CR2_JEXTEN_Pos                   (20U)
975 #define ADC_CR2_JEXTEN_Msk                   (0x3U << ADC_CR2_JEXTEN_Pos)      /*!< 0x00300000 */
976 #define ADC_CR2_JEXTEN                       ADC_CR2_JEXTEN_Msk                /*!< ADC group injected external trigger polarity */
977 #define ADC_CR2_JEXTEN_0                     (0x1U << ADC_CR2_JEXTEN_Pos)      /*!< 0x00100000 */
978 #define ADC_CR2_JEXTEN_1                     (0x2U << ADC_CR2_JEXTEN_Pos)      /*!< 0x00200000 */
979 
980 #define ADC_CR2_JSWSTART_Pos                 (22U)
981 #define ADC_CR2_JSWSTART_Msk                 (0x1U << ADC_CR2_JSWSTART_Pos)    /*!< 0x00400000 */
982 #define ADC_CR2_JSWSTART                     ADC_CR2_JSWSTART_Msk              /*!< ADC group injected conversion start */
983 
984 #define ADC_CR2_EXTSEL_Pos                   (24U)
985 #define ADC_CR2_EXTSEL_Msk                   (0xFU << ADC_CR2_EXTSEL_Pos)      /*!< 0x0F000000 */
986 #define ADC_CR2_EXTSEL                       ADC_CR2_EXTSEL_Msk                /*!< ADC group regular external trigger source */
987 #define ADC_CR2_EXTSEL_0                     (0x1U << ADC_CR2_EXTSEL_Pos)      /*!< 0x01000000 */
988 #define ADC_CR2_EXTSEL_1                     (0x2U << ADC_CR2_EXTSEL_Pos)      /*!< 0x02000000 */
989 #define ADC_CR2_EXTSEL_2                     (0x4U << ADC_CR2_EXTSEL_Pos)      /*!< 0x04000000 */
990 #define ADC_CR2_EXTSEL_3                     (0x8U << ADC_CR2_EXTSEL_Pos)      /*!< 0x08000000 */
991 
992 #define ADC_CR2_EXTEN_Pos                    (28U)
993 #define ADC_CR2_EXTEN_Msk                    (0x3U << ADC_CR2_EXTEN_Pos)       /*!< 0x30000000 */
994 #define ADC_CR2_EXTEN                        ADC_CR2_EXTEN_Msk                 /*!< ADC group regular external trigger polarity */
995 #define ADC_CR2_EXTEN_0                      (0x1U << ADC_CR2_EXTEN_Pos)       /*!< 0x10000000 */
996 #define ADC_CR2_EXTEN_1                      (0x2U << ADC_CR2_EXTEN_Pos)       /*!< 0x20000000 */
997 
998 #define ADC_CR2_SWSTART_Pos                  (30U)
999 #define ADC_CR2_SWSTART_Msk                  (0x1U << ADC_CR2_SWSTART_Pos)     /*!< 0x40000000 */
1000 #define ADC_CR2_SWSTART                      ADC_CR2_SWSTART_Msk               /*!< ADC group regular conversion start */
1001 
1002 /******************  Bit definition for ADC_SMPR1 register  *******************/
1003 #define ADC_SMPR1_SMP20_Pos                  (0U)
1004 #define ADC_SMPR1_SMP20_Msk                  (0x7U << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000007 */
1005 #define ADC_SMPR1_SMP20                      ADC_SMPR1_SMP20_Msk               /*!< ADC channel 20 sampling time selection */
1006 #define ADC_SMPR1_SMP20_0                    (0x1U << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000001 */
1007 #define ADC_SMPR1_SMP20_1                    (0x2U << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000002 */
1008 #define ADC_SMPR1_SMP20_2                    (0x4U << ADC_SMPR1_SMP20_Pos)     /*!< 0x00000004 */
1009 
1010 #define ADC_SMPR1_SMP21_Pos                  (3U)
1011 #define ADC_SMPR1_SMP21_Msk                  (0x7U << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000038 */
1012 #define ADC_SMPR1_SMP21                      ADC_SMPR1_SMP21_Msk               /*!< ADC channel 21 sampling time selection */
1013 #define ADC_SMPR1_SMP21_0                    (0x1U << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000008 */
1014 #define ADC_SMPR1_SMP21_1                    (0x2U << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000010 */
1015 #define ADC_SMPR1_SMP21_2                    (0x4U << ADC_SMPR1_SMP21_Pos)     /*!< 0x00000020 */
1016 
1017 #define ADC_SMPR1_SMP22_Pos                  (6U)
1018 #define ADC_SMPR1_SMP22_Msk                  (0x7U << ADC_SMPR1_SMP22_Pos)     /*!< 0x000001C0 */
1019 #define ADC_SMPR1_SMP22                      ADC_SMPR1_SMP22_Msk               /*!< ADC channel 22 sampling time selection */
1020 #define ADC_SMPR1_SMP22_0                    (0x1U << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000040 */
1021 #define ADC_SMPR1_SMP22_1                    (0x2U << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000080 */
1022 #define ADC_SMPR1_SMP22_2                    (0x4U << ADC_SMPR1_SMP22_Pos)     /*!< 0x00000100 */
1023 
1024 #define ADC_SMPR1_SMP23_Pos                  (9U)
1025 #define ADC_SMPR1_SMP23_Msk                  (0x7U << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000E00 */
1026 #define ADC_SMPR1_SMP23                      ADC_SMPR1_SMP23_Msk               /*!< ADC channel 23 sampling time selection */
1027 #define ADC_SMPR1_SMP23_0                    (0x1U << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000200 */
1028 #define ADC_SMPR1_SMP23_1                    (0x2U << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000400 */
1029 #define ADC_SMPR1_SMP23_2                    (0x4U << ADC_SMPR1_SMP23_Pos)     /*!< 0x00000800 */
1030 
1031 #define ADC_SMPR1_SMP24_Pos                  (12U)
1032 #define ADC_SMPR1_SMP24_Msk                  (0x7U << ADC_SMPR1_SMP24_Pos)     /*!< 0x00007000 */
1033 #define ADC_SMPR1_SMP24                      ADC_SMPR1_SMP24_Msk               /*!< ADC channel 24 sampling time selection */
1034 #define ADC_SMPR1_SMP24_0                    (0x1U << ADC_SMPR1_SMP24_Pos)     /*!< 0x00001000 */
1035 #define ADC_SMPR1_SMP24_1                    (0x2U << ADC_SMPR1_SMP24_Pos)     /*!< 0x00002000 */
1036 #define ADC_SMPR1_SMP24_2                    (0x4U << ADC_SMPR1_SMP24_Pos)     /*!< 0x00004000 */
1037 
1038 #define ADC_SMPR1_SMP25_Pos                  (15U)
1039 #define ADC_SMPR1_SMP25_Msk                  (0x7U << ADC_SMPR1_SMP25_Pos)     /*!< 0x00038000 */
1040 #define ADC_SMPR1_SMP25                      ADC_SMPR1_SMP25_Msk               /*!< ADC channel 25 sampling time selection */
1041 #define ADC_SMPR1_SMP25_0                    (0x1U << ADC_SMPR1_SMP25_Pos)     /*!< 0x00008000 */
1042 #define ADC_SMPR1_SMP25_1                    (0x2U << ADC_SMPR1_SMP25_Pos)     /*!< 0x00010000 */
1043 #define ADC_SMPR1_SMP25_2                    (0x4U << ADC_SMPR1_SMP25_Pos)     /*!< 0x00020000 */
1044 
1045 #define ADC_SMPR1_SMP26_Pos                  (18U)
1046 #define ADC_SMPR1_SMP26_Msk                  (0x7U << ADC_SMPR1_SMP26_Pos)     /*!< 0x001C0000 */
1047 #define ADC_SMPR1_SMP26                      ADC_SMPR1_SMP26_Msk               /*!< ADC channel 26 sampling time selection */
1048 #define ADC_SMPR1_SMP26_0                    (0x1U << ADC_SMPR1_SMP26_Pos)     /*!< 0x00040000 */
1049 #define ADC_SMPR1_SMP26_1                    (0x2U << ADC_SMPR1_SMP26_Pos)     /*!< 0x00080000 */
1050 #define ADC_SMPR1_SMP26_2                    (0x4U << ADC_SMPR1_SMP26_Pos)     /*!< 0x00100000 */
1051 
1052 /******************  Bit definition for ADC_SMPR2 register  *******************/
1053 #define ADC_SMPR2_SMP10_Pos                  (0U)
1054 #define ADC_SMPR2_SMP10_Msk                  (0x7U << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000007 */
1055 #define ADC_SMPR2_SMP10                      ADC_SMPR2_SMP10_Msk               /*!< ADC channel 10 sampling time selection */
1056 #define ADC_SMPR2_SMP10_0                    (0x1U << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000001 */
1057 #define ADC_SMPR2_SMP10_1                    (0x2U << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000002 */
1058 #define ADC_SMPR2_SMP10_2                    (0x4U << ADC_SMPR2_SMP10_Pos)     /*!< 0x00000004 */
1059 
1060 #define ADC_SMPR2_SMP11_Pos                  (3U)
1061 #define ADC_SMPR2_SMP11_Msk                  (0x7U << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000038 */
1062 #define ADC_SMPR2_SMP11                      ADC_SMPR2_SMP11_Msk               /*!< ADC channel 11 sampling time selection */
1063 #define ADC_SMPR2_SMP11_0                    (0x1U << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000008 */
1064 #define ADC_SMPR2_SMP11_1                    (0x2U << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000010 */
1065 #define ADC_SMPR2_SMP11_2                    (0x4U << ADC_SMPR2_SMP11_Pos)     /*!< 0x00000020 */
1066 
1067 #define ADC_SMPR2_SMP12_Pos                  (6U)
1068 #define ADC_SMPR2_SMP12_Msk                  (0x7U << ADC_SMPR2_SMP12_Pos)     /*!< 0x000001C0 */
1069 #define ADC_SMPR2_SMP12                      ADC_SMPR2_SMP12_Msk               /*!< ADC channel 12 sampling time selection */
1070 #define ADC_SMPR2_SMP12_0                    (0x1U << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000040 */
1071 #define ADC_SMPR2_SMP12_1                    (0x2U << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000080 */
1072 #define ADC_SMPR2_SMP12_2                    (0x4U << ADC_SMPR2_SMP12_Pos)     /*!< 0x00000100 */
1073 
1074 #define ADC_SMPR2_SMP13_Pos                  (9U)
1075 #define ADC_SMPR2_SMP13_Msk                  (0x7U << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000E00 */
1076 #define ADC_SMPR2_SMP13                      ADC_SMPR2_SMP13_Msk               /*!< ADC channel 13 sampling time selection */
1077 #define ADC_SMPR2_SMP13_0                    (0x1U << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000200 */
1078 #define ADC_SMPR2_SMP13_1                    (0x2U << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000400 */
1079 #define ADC_SMPR2_SMP13_2                    (0x4U << ADC_SMPR2_SMP13_Pos)     /*!< 0x00000800 */
1080 
1081 #define ADC_SMPR2_SMP14_Pos                  (12U)
1082 #define ADC_SMPR2_SMP14_Msk                  (0x7U << ADC_SMPR2_SMP14_Pos)     /*!< 0x00007000 */
1083 #define ADC_SMPR2_SMP14                      ADC_SMPR2_SMP14_Msk               /*!< ADC channel 14 sampling time selection */
1084 #define ADC_SMPR2_SMP14_0                    (0x1U << ADC_SMPR2_SMP14_Pos)     /*!< 0x00001000 */
1085 #define ADC_SMPR2_SMP14_1                    (0x2U << ADC_SMPR2_SMP14_Pos)     /*!< 0x00002000 */
1086 #define ADC_SMPR2_SMP14_2                    (0x4U << ADC_SMPR2_SMP14_Pos)     /*!< 0x00004000 */
1087 
1088 #define ADC_SMPR2_SMP15_Pos                  (15U)
1089 #define ADC_SMPR2_SMP15_Msk                  (0x7U << ADC_SMPR2_SMP15_Pos)     /*!< 0x00038000 */
1090 #define ADC_SMPR2_SMP15                      ADC_SMPR2_SMP15_Msk               /*!< ADC channel 5 sampling time selection */
1091 #define ADC_SMPR2_SMP15_0                    (0x1U << ADC_SMPR2_SMP15_Pos)     /*!< 0x00008000 */
1092 #define ADC_SMPR2_SMP15_1                    (0x2U << ADC_SMPR2_SMP15_Pos)     /*!< 0x00010000 */
1093 #define ADC_SMPR2_SMP15_2                    (0x4U << ADC_SMPR2_SMP15_Pos)     /*!< 0x00020000 */
1094 
1095 #define ADC_SMPR2_SMP16_Pos                  (18U)
1096 #define ADC_SMPR2_SMP16_Msk                  (0x7U << ADC_SMPR2_SMP16_Pos)     /*!< 0x001C0000 */
1097 #define ADC_SMPR2_SMP16                      ADC_SMPR2_SMP16_Msk               /*!< ADC channel 16 sampling time selection */
1098 #define ADC_SMPR2_SMP16_0                    (0x1U << ADC_SMPR2_SMP16_Pos)     /*!< 0x00040000 */
1099 #define ADC_SMPR2_SMP16_1                    (0x2U << ADC_SMPR2_SMP16_Pos)     /*!< 0x00080000 */
1100 #define ADC_SMPR2_SMP16_2                    (0x4U << ADC_SMPR2_SMP16_Pos)     /*!< 0x00100000 */
1101 
1102 #define ADC_SMPR2_SMP17_Pos                  (21U)
1103 #define ADC_SMPR2_SMP17_Msk                  (0x7U << ADC_SMPR2_SMP17_Pos)     /*!< 0x00E00000 */
1104 #define ADC_SMPR2_SMP17                      ADC_SMPR2_SMP17_Msk               /*!< ADC channel 17 sampling time selection */
1105 #define ADC_SMPR2_SMP17_0                    (0x1U << ADC_SMPR2_SMP17_Pos)     /*!< 0x00200000 */
1106 #define ADC_SMPR2_SMP17_1                    (0x2U << ADC_SMPR2_SMP17_Pos)     /*!< 0x00400000 */
1107 #define ADC_SMPR2_SMP17_2                    (0x4U << ADC_SMPR2_SMP17_Pos)     /*!< 0x00800000 */
1108 
1109 #define ADC_SMPR2_SMP18_Pos                  (24U)
1110 #define ADC_SMPR2_SMP18_Msk                  (0x7U << ADC_SMPR2_SMP18_Pos)     /*!< 0x07000000 */
1111 #define ADC_SMPR2_SMP18                      ADC_SMPR2_SMP18_Msk               /*!< ADC channel 18 sampling time selection */
1112 #define ADC_SMPR2_SMP18_0                    (0x1U << ADC_SMPR2_SMP18_Pos)     /*!< 0x01000000 */
1113 #define ADC_SMPR2_SMP18_1                    (0x2U << ADC_SMPR2_SMP18_Pos)     /*!< 0x02000000 */
1114 #define ADC_SMPR2_SMP18_2                    (0x4U << ADC_SMPR2_SMP18_Pos)     /*!< 0x04000000 */
1115 
1116 #define ADC_SMPR2_SMP19_Pos                  (27U)
1117 #define ADC_SMPR2_SMP19_Msk                  (0x7U << ADC_SMPR2_SMP19_Pos)     /*!< 0x38000000 */
1118 #define ADC_SMPR2_SMP19                      ADC_SMPR2_SMP19_Msk               /*!< ADC channel 19 sampling time selection */
1119 #define ADC_SMPR2_SMP19_0                    (0x1U << ADC_SMPR2_SMP19_Pos)     /*!< 0x08000000 */
1120 #define ADC_SMPR2_SMP19_1                    (0x2U << ADC_SMPR2_SMP19_Pos)     /*!< 0x10000000 */
1121 #define ADC_SMPR2_SMP19_2                    (0x4U << ADC_SMPR2_SMP19_Pos)     /*!< 0x20000000 */
1122 
1123 /******************  Bit definition for ADC_SMPR3 register  *******************/
1124 #define ADC_SMPR3_SMP0_Pos                   (0U)
1125 #define ADC_SMPR3_SMP0_Msk                   (0x7U << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000007 */
1126 #define ADC_SMPR3_SMP0                       ADC_SMPR3_SMP0_Msk                /*!< ADC channel 0 sampling time selection */
1127 #define ADC_SMPR3_SMP0_0                     (0x1U << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000001 */
1128 #define ADC_SMPR3_SMP0_1                     (0x2U << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000002 */
1129 #define ADC_SMPR3_SMP0_2                     (0x4U << ADC_SMPR3_SMP0_Pos)      /*!< 0x00000004 */
1130 
1131 #define ADC_SMPR3_SMP1_Pos                   (3U)
1132 #define ADC_SMPR3_SMP1_Msk                   (0x7U << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000038 */
1133 #define ADC_SMPR3_SMP1                       ADC_SMPR3_SMP1_Msk                /*!< ADC channel 1 sampling time selection */
1134 #define ADC_SMPR3_SMP1_0                     (0x1U << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000008 */
1135 #define ADC_SMPR3_SMP1_1                     (0x2U << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000010 */
1136 #define ADC_SMPR3_SMP1_2                     (0x4U << ADC_SMPR3_SMP1_Pos)      /*!< 0x00000020 */
1137 
1138 #define ADC_SMPR3_SMP2_Pos                   (6U)
1139 #define ADC_SMPR3_SMP2_Msk                   (0x7U << ADC_SMPR3_SMP2_Pos)      /*!< 0x000001C0 */
1140 #define ADC_SMPR3_SMP2                       ADC_SMPR3_SMP2_Msk                /*!< ADC channel 2 sampling time selection */
1141 #define ADC_SMPR3_SMP2_0                     (0x1U << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000040 */
1142 #define ADC_SMPR3_SMP2_1                     (0x2U << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000080 */
1143 #define ADC_SMPR3_SMP2_2                     (0x4U << ADC_SMPR3_SMP2_Pos)      /*!< 0x00000100 */
1144 
1145 #define ADC_SMPR3_SMP3_Pos                   (9U)
1146 #define ADC_SMPR3_SMP3_Msk                   (0x7U << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000E00 */
1147 #define ADC_SMPR3_SMP3                       ADC_SMPR3_SMP3_Msk                /*!< ADC channel 3 sampling time selection */
1148 #define ADC_SMPR3_SMP3_0                     (0x1U << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000200 */
1149 #define ADC_SMPR3_SMP3_1                     (0x2U << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000400 */
1150 #define ADC_SMPR3_SMP3_2                     (0x4U << ADC_SMPR3_SMP3_Pos)      /*!< 0x00000800 */
1151 
1152 #define ADC_SMPR3_SMP4_Pos                   (12U)
1153 #define ADC_SMPR3_SMP4_Msk                   (0x7U << ADC_SMPR3_SMP4_Pos)      /*!< 0x00007000 */
1154 #define ADC_SMPR3_SMP4                       ADC_SMPR3_SMP4_Msk                /*!< ADC channel 4 sampling time selection */
1155 #define ADC_SMPR3_SMP4_0                     (0x1U << ADC_SMPR3_SMP4_Pos)      /*!< 0x00001000 */
1156 #define ADC_SMPR3_SMP4_1                     (0x2U << ADC_SMPR3_SMP4_Pos)      /*!< 0x00002000 */
1157 #define ADC_SMPR3_SMP4_2                     (0x4U << ADC_SMPR3_SMP4_Pos)      /*!< 0x00004000 */
1158 
1159 #define ADC_SMPR3_SMP5_Pos                   (15U)
1160 #define ADC_SMPR3_SMP5_Msk                   (0x7U << ADC_SMPR3_SMP5_Pos)      /*!< 0x00038000 */
1161 #define ADC_SMPR3_SMP5                       ADC_SMPR3_SMP5_Msk                /*!< ADC channel 5 sampling time selection */
1162 #define ADC_SMPR3_SMP5_0                     (0x1U << ADC_SMPR3_SMP5_Pos)      /*!< 0x00008000 */
1163 #define ADC_SMPR3_SMP5_1                     (0x2U << ADC_SMPR3_SMP5_Pos)      /*!< 0x00010000 */
1164 #define ADC_SMPR3_SMP5_2                     (0x4U << ADC_SMPR3_SMP5_Pos)      /*!< 0x00020000 */
1165 
1166 #define ADC_SMPR3_SMP6_Pos                   (18U)
1167 #define ADC_SMPR3_SMP6_Msk                   (0x7U << ADC_SMPR3_SMP6_Pos)      /*!< 0x001C0000 */
1168 #define ADC_SMPR3_SMP6                       ADC_SMPR3_SMP6_Msk                /*!< ADC channel 6 sampling time selection */
1169 #define ADC_SMPR3_SMP6_0                     (0x1U << ADC_SMPR3_SMP6_Pos)      /*!< 0x00040000 */
1170 #define ADC_SMPR3_SMP6_1                     (0x2U << ADC_SMPR3_SMP6_Pos)      /*!< 0x00080000 */
1171 #define ADC_SMPR3_SMP6_2                     (0x4U << ADC_SMPR3_SMP6_Pos)      /*!< 0x00100000 */
1172 
1173 #define ADC_SMPR3_SMP7_Pos                   (21U)
1174 #define ADC_SMPR3_SMP7_Msk                   (0x7U << ADC_SMPR3_SMP7_Pos)      /*!< 0x00E00000 */
1175 #define ADC_SMPR3_SMP7                       ADC_SMPR3_SMP7_Msk                /*!< ADC channel 7 sampling time selection */
1176 #define ADC_SMPR3_SMP7_0                     (0x1U << ADC_SMPR3_SMP7_Pos)      /*!< 0x00200000 */
1177 #define ADC_SMPR3_SMP7_1                     (0x2U << ADC_SMPR3_SMP7_Pos)      /*!< 0x00400000 */
1178 #define ADC_SMPR3_SMP7_2                     (0x4U << ADC_SMPR3_SMP7_Pos)      /*!< 0x00800000 */
1179 
1180 #define ADC_SMPR3_SMP8_Pos                   (24U)
1181 #define ADC_SMPR3_SMP8_Msk                   (0x7U << ADC_SMPR3_SMP8_Pos)      /*!< 0x07000000 */
1182 #define ADC_SMPR3_SMP8                       ADC_SMPR3_SMP8_Msk                /*!< ADC channel 8 sampling time selection */
1183 #define ADC_SMPR3_SMP8_0                     (0x1U << ADC_SMPR3_SMP8_Pos)      /*!< 0x01000000 */
1184 #define ADC_SMPR3_SMP8_1                     (0x2U << ADC_SMPR3_SMP8_Pos)      /*!< 0x02000000 */
1185 #define ADC_SMPR3_SMP8_2                     (0x4U << ADC_SMPR3_SMP8_Pos)      /*!< 0x04000000 */
1186 
1187 #define ADC_SMPR3_SMP9_Pos                   (27U)
1188 #define ADC_SMPR3_SMP9_Msk                   (0x7U << ADC_SMPR3_SMP9_Pos)      /*!< 0x38000000 */
1189 #define ADC_SMPR3_SMP9                       ADC_SMPR3_SMP9_Msk                /*!< ADC channel 9 sampling time selection */
1190 #define ADC_SMPR3_SMP9_0                     (0x1U << ADC_SMPR3_SMP9_Pos)      /*!< 0x08000000 */
1191 #define ADC_SMPR3_SMP9_1                     (0x2U << ADC_SMPR3_SMP9_Pos)      /*!< 0x10000000 */
1192 #define ADC_SMPR3_SMP9_2                     (0x4U << ADC_SMPR3_SMP9_Pos)      /*!< 0x20000000 */
1193 
1194 /******************  Bit definition for ADC_JOFR1 register  *******************/
1195 #define ADC_JOFR1_JOFFSET1_Pos               (0U)
1196 #define ADC_JOFR1_JOFFSET1_Msk               (0xFFFU << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */
1197 #define ADC_JOFR1_JOFFSET1                   ADC_JOFR1_JOFFSET1_Msk            /*!< ADC group injected sequencer rank 1 offset value */
1198 
1199 /******************  Bit definition for ADC_JOFR2 register  *******************/
1200 #define ADC_JOFR2_JOFFSET2_Pos               (0U)
1201 #define ADC_JOFR2_JOFFSET2_Msk               (0xFFFU << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */
1202 #define ADC_JOFR2_JOFFSET2                   ADC_JOFR2_JOFFSET2_Msk            /*!< ADC group injected sequencer rank 2 offset value */
1203 
1204 /******************  Bit definition for ADC_JOFR3 register  *******************/
1205 #define ADC_JOFR3_JOFFSET3_Pos               (0U)
1206 #define ADC_JOFR3_JOFFSET3_Msk               (0xFFFU << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */
1207 #define ADC_JOFR3_JOFFSET3                   ADC_JOFR3_JOFFSET3_Msk            /*!< ADC group injected sequencer rank 3 offset value */
1208 
1209 /******************  Bit definition for ADC_JOFR4 register  *******************/
1210 #define ADC_JOFR4_JOFFSET4_Pos               (0U)
1211 #define ADC_JOFR4_JOFFSET4_Msk               (0xFFFU << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */
1212 #define ADC_JOFR4_JOFFSET4                   ADC_JOFR4_JOFFSET4_Msk            /*!< ADC group injected sequencer rank 4 offset value */
1213 
1214 /*******************  Bit definition for ADC_HTR register  ********************/
1215 #define ADC_HTR_HT_Pos                       (0U)
1216 #define ADC_HTR_HT_Msk                       (0xFFFU << ADC_HTR_HT_Pos)        /*!< 0x00000FFF */
1217 #define ADC_HTR_HT                           ADC_HTR_HT_Msk                    /*!< ADC analog watchdog 1 threshold high */
1218 
1219 /*******************  Bit definition for ADC_LTR register  ********************/
1220 #define ADC_LTR_LT_Pos                       (0U)
1221 #define ADC_LTR_LT_Msk                       (0xFFFU << ADC_LTR_LT_Pos)        /*!< 0x00000FFF */
1222 #define ADC_LTR_LT                           ADC_LTR_LT_Msk                    /*!< ADC analog watchdog 1 threshold low */
1223 
1224 /*******************  Bit definition for ADC_SQR1 register  *******************/
1225 #define ADC_SQR1_L_Pos                       (20U)
1226 #define ADC_SQR1_L_Msk                       (0x1FU << ADC_SQR1_L_Pos)         /*!< 0x01F00000 */
1227 #define ADC_SQR1_L                           ADC_SQR1_L_Msk                    /*!< ADC group regular sequencer scan length */
1228 #define ADC_SQR1_L_0                         (0x01U << ADC_SQR1_L_Pos)         /*!< 0x00100000 */
1229 #define ADC_SQR1_L_1                         (0x02U << ADC_SQR1_L_Pos)         /*!< 0x00200000 */
1230 #define ADC_SQR1_L_2                         (0x04U << ADC_SQR1_L_Pos)         /*!< 0x00400000 */
1231 #define ADC_SQR1_L_3                         (0x08U << ADC_SQR1_L_Pos)         /*!< 0x00800000 */
1232 #define ADC_SQR1_L_4                         (0x10U << ADC_SQR1_L_Pos)         /*!< 0x01000000 */
1233 
1234 #define ADC_SQR1_SQ28_Pos                    (15U)
1235 #define ADC_SQR1_SQ28_Msk                    (0x1FU << ADC_SQR1_SQ28_Pos)      /*!< 0x000F8000 */
1236 #define ADC_SQR1_SQ28                        ADC_SQR1_SQ28_Msk                 /*!< ADC group regular sequencer rank 28 */
1237 #define ADC_SQR1_SQ28_0                      (0x01U << ADC_SQR1_SQ28_Pos)      /*!< 0x00008000 */
1238 #define ADC_SQR1_SQ28_1                      (0x02U << ADC_SQR1_SQ28_Pos)      /*!< 0x00010000 */
1239 #define ADC_SQR1_SQ28_2                      (0x04U << ADC_SQR1_SQ28_Pos)      /*!< 0x00020000 */
1240 #define ADC_SQR1_SQ28_3                      (0x08U << ADC_SQR1_SQ28_Pos)      /*!< 0x00040000 */
1241 #define ADC_SQR1_SQ28_4                      (0x10U << ADC_SQR1_SQ28_Pos)      /*!< 0x00080000 */
1242 
1243 #define ADC_SQR1_SQ27_Pos                    (10U)
1244 #define ADC_SQR1_SQ27_Msk                    (0x1FU << ADC_SQR1_SQ27_Pos)      /*!< 0x00007C00 */
1245 #define ADC_SQR1_SQ27                        ADC_SQR1_SQ27_Msk                 /*!< ADC group regular sequencer rank 27 */
1246 #define ADC_SQR1_SQ27_0                      (0x01U << ADC_SQR1_SQ27_Pos)      /*!< 0x00000400 */
1247 #define ADC_SQR1_SQ27_1                      (0x02U << ADC_SQR1_SQ27_Pos)      /*!< 0x00000800 */
1248 #define ADC_SQR1_SQ27_2                      (0x04U << ADC_SQR1_SQ27_Pos)      /*!< 0x00001000 */
1249 #define ADC_SQR1_SQ27_3                      (0x08U << ADC_SQR1_SQ27_Pos)      /*!< 0x00002000 */
1250 #define ADC_SQR1_SQ27_4                      (0x10U << ADC_SQR1_SQ27_Pos)      /*!< 0x00004000 */
1251 
1252 #define ADC_SQR1_SQ26_Pos                    (5U)
1253 #define ADC_SQR1_SQ26_Msk                    (0x1FU << ADC_SQR1_SQ26_Pos)      /*!< 0x000003E0 */
1254 #define ADC_SQR1_SQ26                        ADC_SQR1_SQ26_Msk                 /*!< ADC group regular sequencer rank 26 */
1255 #define ADC_SQR1_SQ26_0                      (0x01U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000020 */
1256 #define ADC_SQR1_SQ26_1                      (0x02U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000040 */
1257 #define ADC_SQR1_SQ26_2                      (0x04U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000080 */
1258 #define ADC_SQR1_SQ26_3                      (0x08U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000100 */
1259 #define ADC_SQR1_SQ26_4                      (0x10U << ADC_SQR1_SQ26_Pos)      /*!< 0x00000200 */
1260 
1261 #define ADC_SQR1_SQ25_Pos                    (0U)
1262 #define ADC_SQR1_SQ25_Msk                    (0x1FU << ADC_SQR1_SQ25_Pos)      /*!< 0x0000001F */
1263 #define ADC_SQR1_SQ25                        ADC_SQR1_SQ25_Msk                 /*!< ADC group regular sequencer rank 25 */
1264 #define ADC_SQR1_SQ25_0                      (0x01U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000001 */
1265 #define ADC_SQR1_SQ25_1                      (0x02U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000002 */
1266 #define ADC_SQR1_SQ25_2                      (0x04U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000004 */
1267 #define ADC_SQR1_SQ25_3                      (0x08U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000008 */
1268 #define ADC_SQR1_SQ25_4                      (0x10U << ADC_SQR1_SQ25_Pos)      /*!< 0x00000010 */
1269 
1270 /*******************  Bit definition for ADC_SQR2 register  *******************/
1271 #define ADC_SQR2_SQ19_Pos                    (0U)
1272 #define ADC_SQR2_SQ19_Msk                    (0x1FU << ADC_SQR2_SQ19_Pos)      /*!< 0x0000001F */
1273 #define ADC_SQR2_SQ19                        ADC_SQR2_SQ19_Msk                 /*!< ADC group regular sequencer rank 19 */
1274 #define ADC_SQR2_SQ19_0                      (0x01U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000001 */
1275 #define ADC_SQR2_SQ19_1                      (0x02U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000002 */
1276 #define ADC_SQR2_SQ19_2                      (0x04U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000004 */
1277 #define ADC_SQR2_SQ19_3                      (0x08U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000008 */
1278 #define ADC_SQR2_SQ19_4                      (0x10U << ADC_SQR2_SQ19_Pos)      /*!< 0x00000010 */
1279 
1280 #define ADC_SQR2_SQ20_Pos                    (5U)
1281 #define ADC_SQR2_SQ20_Msk                    (0x1FU << ADC_SQR2_SQ20_Pos)      /*!< 0x000003E0 */
1282 #define ADC_SQR2_SQ20                        ADC_SQR2_SQ20_Msk                 /*!< ADC group regular sequencer rank 20 */
1283 #define ADC_SQR2_SQ20_0                      (0x01U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000020 */
1284 #define ADC_SQR2_SQ20_1                      (0x02U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000040 */
1285 #define ADC_SQR2_SQ20_2                      (0x04U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000080 */
1286 #define ADC_SQR2_SQ20_3                      (0x08U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000100 */
1287 #define ADC_SQR2_SQ20_4                      (0x10U << ADC_SQR2_SQ20_Pos)      /*!< 0x00000200 */
1288 
1289 #define ADC_SQR2_SQ21_Pos                    (10U)
1290 #define ADC_SQR2_SQ21_Msk                    (0x1FU << ADC_SQR2_SQ21_Pos)      /*!< 0x00007C00 */
1291 #define ADC_SQR2_SQ21                        ADC_SQR2_SQ21_Msk                 /*!< ADC group regular sequencer rank 21 */
1292 #define ADC_SQR2_SQ21_0                      (0x01U << ADC_SQR2_SQ21_Pos)      /*!< 0x00000400 */
1293 #define ADC_SQR2_SQ21_1                      (0x02U << ADC_SQR2_SQ21_Pos)      /*!< 0x00000800 */
1294 #define ADC_SQR2_SQ21_2                      (0x04U << ADC_SQR2_SQ21_Pos)      /*!< 0x00001000 */
1295 #define ADC_SQR2_SQ21_3                      (0x08U << ADC_SQR2_SQ21_Pos)      /*!< 0x00002000 */
1296 #define ADC_SQR2_SQ21_4                      (0x10U << ADC_SQR2_SQ21_Pos)      /*!< 0x00004000 */
1297 
1298 #define ADC_SQR2_SQ22_Pos                    (15U)
1299 #define ADC_SQR2_SQ22_Msk                    (0x1FU << ADC_SQR2_SQ22_Pos)      /*!< 0x000F8000 */
1300 #define ADC_SQR2_SQ22                        ADC_SQR2_SQ22_Msk                 /*!< ADC group regular sequencer rank 22 */
1301 #define ADC_SQR2_SQ22_0                      (0x01U << ADC_SQR2_SQ22_Pos)      /*!< 0x00008000 */
1302 #define ADC_SQR2_SQ22_1                      (0x02U << ADC_SQR2_SQ22_Pos)      /*!< 0x00010000 */
1303 #define ADC_SQR2_SQ22_2                      (0x04U << ADC_SQR2_SQ22_Pos)      /*!< 0x00020000 */
1304 #define ADC_SQR2_SQ22_3                      (0x08U << ADC_SQR2_SQ22_Pos)      /*!< 0x00040000 */
1305 #define ADC_SQR2_SQ22_4                      (0x10U << ADC_SQR2_SQ22_Pos)      /*!< 0x00080000 */
1306 
1307 #define ADC_SQR2_SQ23_Pos                    (20U)
1308 #define ADC_SQR2_SQ23_Msk                    (0x1FU << ADC_SQR2_SQ23_Pos)      /*!< 0x01F00000 */
1309 #define ADC_SQR2_SQ23                        ADC_SQR2_SQ23_Msk                 /*!< ADC group regular sequencer rank 23 */
1310 #define ADC_SQR2_SQ23_0                      (0x01U << ADC_SQR2_SQ23_Pos)      /*!< 0x00100000 */
1311 #define ADC_SQR2_SQ23_1                      (0x02U << ADC_SQR2_SQ23_Pos)      /*!< 0x00200000 */
1312 #define ADC_SQR2_SQ23_2                      (0x04U << ADC_SQR2_SQ23_Pos)      /*!< 0x00400000 */
1313 #define ADC_SQR2_SQ23_3                      (0x08U << ADC_SQR2_SQ23_Pos)      /*!< 0x00800000 */
1314 #define ADC_SQR2_SQ23_4                      (0x10U << ADC_SQR2_SQ23_Pos)      /*!< 0x01000000 */
1315 
1316 #define ADC_SQR2_SQ24_Pos                    (25U)
1317 #define ADC_SQR2_SQ24_Msk                    (0x1FU << ADC_SQR2_SQ24_Pos)      /*!< 0x3E000000 */
1318 #define ADC_SQR2_SQ24                        ADC_SQR2_SQ24_Msk                 /*!< ADC group regular sequencer rank 24 */
1319 #define ADC_SQR2_SQ24_0                      (0x01U << ADC_SQR2_SQ24_Pos)      /*!< 0x02000000 */
1320 #define ADC_SQR2_SQ24_1                      (0x02U << ADC_SQR2_SQ24_Pos)      /*!< 0x04000000 */
1321 #define ADC_SQR2_SQ24_2                      (0x04U << ADC_SQR2_SQ24_Pos)      /*!< 0x08000000 */
1322 #define ADC_SQR2_SQ24_3                      (0x08U << ADC_SQR2_SQ24_Pos)      /*!< 0x10000000 */
1323 #define ADC_SQR2_SQ24_4                      (0x10U << ADC_SQR2_SQ24_Pos)      /*!< 0x20000000 */
1324 
1325 /*******************  Bit definition for ADC_SQR3 register  *******************/
1326 #define ADC_SQR3_SQ13_Pos                    (0U)
1327 #define ADC_SQR3_SQ13_Msk                    (0x1FU << ADC_SQR3_SQ13_Pos)      /*!< 0x0000001F */
1328 #define ADC_SQR3_SQ13                        ADC_SQR3_SQ13_Msk                 /*!< ADC group regular sequencer rank 13 */
1329 #define ADC_SQR3_SQ13_0                      (0x01U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000001 */
1330 #define ADC_SQR3_SQ13_1                      (0x02U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000002 */
1331 #define ADC_SQR3_SQ13_2                      (0x04U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000004 */
1332 #define ADC_SQR3_SQ13_3                      (0x08U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000008 */
1333 #define ADC_SQR3_SQ13_4                      (0x10U << ADC_SQR3_SQ13_Pos)      /*!< 0x00000010 */
1334 
1335 #define ADC_SQR3_SQ14_Pos                    (5U)
1336 #define ADC_SQR3_SQ14_Msk                    (0x1FU << ADC_SQR3_SQ14_Pos)      /*!< 0x000003E0 */
1337 #define ADC_SQR3_SQ14                        ADC_SQR3_SQ14_Msk                 /*!< ADC group regular sequencer rank 14 */
1338 #define ADC_SQR3_SQ14_0                      (0x01U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000020 */
1339 #define ADC_SQR3_SQ14_1                      (0x02U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000040 */
1340 #define ADC_SQR3_SQ14_2                      (0x04U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000080 */
1341 #define ADC_SQR3_SQ14_3                      (0x08U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000100 */
1342 #define ADC_SQR3_SQ14_4                      (0x10U << ADC_SQR3_SQ14_Pos)      /*!< 0x00000200 */
1343 
1344 #define ADC_SQR3_SQ15_Pos                    (10U)
1345 #define ADC_SQR3_SQ15_Msk                    (0x1FU << ADC_SQR3_SQ15_Pos)      /*!< 0x00007C00 */
1346 #define ADC_SQR3_SQ15                        ADC_SQR3_SQ15_Msk                 /*!< ADC group regular sequencer rank 15 */
1347 #define ADC_SQR3_SQ15_0                      (0x01U << ADC_SQR3_SQ15_Pos)      /*!< 0x00000400 */
1348 #define ADC_SQR3_SQ15_1                      (0x02U << ADC_SQR3_SQ15_Pos)      /*!< 0x00000800 */
1349 #define ADC_SQR3_SQ15_2                      (0x04U << ADC_SQR3_SQ15_Pos)      /*!< 0x00001000 */
1350 #define ADC_SQR3_SQ15_3                      (0x08U << ADC_SQR3_SQ15_Pos)      /*!< 0x00002000 */
1351 #define ADC_SQR3_SQ15_4                      (0x10U << ADC_SQR3_SQ15_Pos)      /*!< 0x00004000 */
1352 
1353 #define ADC_SQR3_SQ16_Pos                    (15U)
1354 #define ADC_SQR3_SQ16_Msk                    (0x1FU << ADC_SQR3_SQ16_Pos)      /*!< 0x000F8000 */
1355 #define ADC_SQR3_SQ16                        ADC_SQR3_SQ16_Msk                 /*!< ADC group regular sequencer rank 16 */
1356 #define ADC_SQR3_SQ16_0                      (0x01U << ADC_SQR3_SQ16_Pos)      /*!< 0x00008000 */
1357 #define ADC_SQR3_SQ16_1                      (0x02U << ADC_SQR3_SQ16_Pos)      /*!< 0x00010000 */
1358 #define ADC_SQR3_SQ16_2                      (0x04U << ADC_SQR3_SQ16_Pos)      /*!< 0x00020000 */
1359 #define ADC_SQR3_SQ16_3                      (0x08U << ADC_SQR3_SQ16_Pos)      /*!< 0x00040000 */
1360 #define ADC_SQR3_SQ16_4                      (0x10U << ADC_SQR3_SQ16_Pos)      /*!< 0x00080000 */
1361 
1362 #define ADC_SQR3_SQ17_Pos                    (20U)
1363 #define ADC_SQR3_SQ17_Msk                    (0x1FU << ADC_SQR3_SQ17_Pos)      /*!< 0x01F00000 */
1364 #define ADC_SQR3_SQ17                        ADC_SQR3_SQ17_Msk                 /*!< ADC group regular sequencer rank 17 */
1365 #define ADC_SQR3_SQ17_0                      (0x01U << ADC_SQR3_SQ17_Pos)      /*!< 0x00100000 */
1366 #define ADC_SQR3_SQ17_1                      (0x02U << ADC_SQR3_SQ17_Pos)      /*!< 0x00200000 */
1367 #define ADC_SQR3_SQ17_2                      (0x04U << ADC_SQR3_SQ17_Pos)      /*!< 0x00400000 */
1368 #define ADC_SQR3_SQ17_3                      (0x08U << ADC_SQR3_SQ17_Pos)      /*!< 0x00800000 */
1369 #define ADC_SQR3_SQ17_4                      (0x10U << ADC_SQR3_SQ17_Pos)      /*!< 0x01000000 */
1370 
1371 #define ADC_SQR3_SQ18_Pos                    (25U)
1372 #define ADC_SQR3_SQ18_Msk                    (0x1FU << ADC_SQR3_SQ18_Pos)      /*!< 0x3E000000 */
1373 #define ADC_SQR3_SQ18                        ADC_SQR3_SQ18_Msk                 /*!< ADC group regular sequencer rank 18 */
1374 #define ADC_SQR3_SQ18_0                      (0x01U << ADC_SQR3_SQ18_Pos)      /*!< 0x02000000 */
1375 #define ADC_SQR3_SQ18_1                      (0x02U << ADC_SQR3_SQ18_Pos)      /*!< 0x04000000 */
1376 #define ADC_SQR3_SQ18_2                      (0x04U << ADC_SQR3_SQ18_Pos)      /*!< 0x08000000 */
1377 #define ADC_SQR3_SQ18_3                      (0x08U << ADC_SQR3_SQ18_Pos)      /*!< 0x10000000 */
1378 #define ADC_SQR3_SQ18_4                      (0x10U << ADC_SQR3_SQ18_Pos)      /*!< 0x20000000 */
1379 
1380 /*******************  Bit definition for ADC_SQR4 register  *******************/
1381 #define ADC_SQR4_SQ7_Pos                     (0U)
1382 #define ADC_SQR4_SQ7_Msk                     (0x1FU << ADC_SQR4_SQ7_Pos)       /*!< 0x0000001F */
1383 #define ADC_SQR4_SQ7                         ADC_SQR4_SQ7_Msk                  /*!< ADC group regular sequencer rank 7 */
1384 #define ADC_SQR4_SQ7_0                       (0x01U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000001 */
1385 #define ADC_SQR4_SQ7_1                       (0x02U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000002 */
1386 #define ADC_SQR4_SQ7_2                       (0x04U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000004 */
1387 #define ADC_SQR4_SQ7_3                       (0x08U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000008 */
1388 #define ADC_SQR4_SQ7_4                       (0x10U << ADC_SQR4_SQ7_Pos)       /*!< 0x00000010 */
1389 
1390 #define ADC_SQR4_SQ8_Pos                     (5U)
1391 #define ADC_SQR4_SQ8_Msk                     (0x1FU << ADC_SQR4_SQ8_Pos)       /*!< 0x000003E0 */
1392 #define ADC_SQR4_SQ8                         ADC_SQR4_SQ8_Msk                  /*!< ADC group regular sequencer rank 8 */
1393 #define ADC_SQR4_SQ8_0                       (0x01U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000020 */
1394 #define ADC_SQR4_SQ8_1                       (0x02U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000040 */
1395 #define ADC_SQR4_SQ8_2                       (0x04U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000080 */
1396 #define ADC_SQR4_SQ8_3                       (0x08U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000100 */
1397 #define ADC_SQR4_SQ8_4                       (0x10U << ADC_SQR4_SQ8_Pos)       /*!< 0x00000200 */
1398 
1399 #define ADC_SQR4_SQ9_Pos                     (10U)
1400 #define ADC_SQR4_SQ9_Msk                     (0x1FU << ADC_SQR4_SQ9_Pos)       /*!< 0x00007C00 */
1401 #define ADC_SQR4_SQ9                         ADC_SQR4_SQ9_Msk                  /*!< ADC group regular sequencer rank 9 */
1402 #define ADC_SQR4_SQ9_0                       (0x01U << ADC_SQR4_SQ9_Pos)       /*!< 0x00000400 */
1403 #define ADC_SQR4_SQ9_1                       (0x02U << ADC_SQR4_SQ9_Pos)       /*!< 0x00000800 */
1404 #define ADC_SQR4_SQ9_2                       (0x04U << ADC_SQR4_SQ9_Pos)       /*!< 0x00001000 */
1405 #define ADC_SQR4_SQ9_3                       (0x08U << ADC_SQR4_SQ9_Pos)       /*!< 0x00002000 */
1406 #define ADC_SQR4_SQ9_4                       (0x10U << ADC_SQR4_SQ9_Pos)       /*!< 0x00004000 */
1407 
1408 #define ADC_SQR4_SQ10_Pos                    (15U)
1409 #define ADC_SQR4_SQ10_Msk                    (0x1FU << ADC_SQR4_SQ10_Pos)      /*!< 0x000F8000 */
1410 #define ADC_SQR4_SQ10                        ADC_SQR4_SQ10_Msk                 /*!< ADC group regular sequencer rank 10 */
1411 #define ADC_SQR4_SQ10_0                      (0x01U << ADC_SQR4_SQ10_Pos)      /*!< 0x00008000 */
1412 #define ADC_SQR4_SQ10_1                      (0x02U << ADC_SQR4_SQ10_Pos)      /*!< 0x00010000 */
1413 #define ADC_SQR4_SQ10_2                      (0x04U << ADC_SQR4_SQ10_Pos)      /*!< 0x00020000 */
1414 #define ADC_SQR4_SQ10_3                      (0x08U << ADC_SQR4_SQ10_Pos)      /*!< 0x00040000 */
1415 #define ADC_SQR4_SQ10_4                      (0x10U << ADC_SQR4_SQ10_Pos)      /*!< 0x00080000 */
1416 
1417 #define ADC_SQR4_SQ11_Pos                    (20U)
1418 #define ADC_SQR4_SQ11_Msk                    (0x1FU << ADC_SQR4_SQ11_Pos)      /*!< 0x01F00000 */
1419 #define ADC_SQR4_SQ11                        ADC_SQR4_SQ11_Msk                 /*!< ADC group regular sequencer rank 11 */
1420 #define ADC_SQR4_SQ11_0                      (0x01U << ADC_SQR4_SQ11_Pos)      /*!< 0x00100000 */
1421 #define ADC_SQR4_SQ11_1                      (0x02U << ADC_SQR4_SQ11_Pos)      /*!< 0x00200000 */
1422 #define ADC_SQR4_SQ11_2                      (0x04U << ADC_SQR4_SQ11_Pos)      /*!< 0x00400000 */
1423 #define ADC_SQR4_SQ11_3                      (0x08U << ADC_SQR4_SQ11_Pos)      /*!< 0x00800000 */
1424 #define ADC_SQR4_SQ11_4                      (0x10U << ADC_SQR4_SQ11_Pos)      /*!< 0x01000000 */
1425 
1426 #define ADC_SQR4_SQ12_Pos                    (25U)
1427 #define ADC_SQR4_SQ12_Msk                    (0x1FU << ADC_SQR4_SQ12_Pos)      /*!< 0x3E000000 */
1428 #define ADC_SQR4_SQ12                        ADC_SQR4_SQ12_Msk                 /*!< ADC group regular sequencer rank 12 */
1429 #define ADC_SQR4_SQ12_0                      (0x01U << ADC_SQR4_SQ12_Pos)      /*!< 0x02000000 */
1430 #define ADC_SQR4_SQ12_1                      (0x02U << ADC_SQR4_SQ12_Pos)      /*!< 0x04000000 */
1431 #define ADC_SQR4_SQ12_2                      (0x04U << ADC_SQR4_SQ12_Pos)      /*!< 0x08000000 */
1432 #define ADC_SQR4_SQ12_3                      (0x08U << ADC_SQR4_SQ12_Pos)      /*!< 0x10000000 */
1433 #define ADC_SQR4_SQ12_4                      (0x10U << ADC_SQR4_SQ12_Pos)      /*!< 0x20000000 */
1434 
1435 /*******************  Bit definition for ADC_SQR5 register  *******************/
1436 #define ADC_SQR5_SQ1_Pos                     (0U)
1437 #define ADC_SQR5_SQ1_Msk                     (0x1FU << ADC_SQR5_SQ1_Pos)       /*!< 0x0000001F */
1438 #define ADC_SQR5_SQ1                         ADC_SQR5_SQ1_Msk                  /*!< ADC group regular sequencer rank 1 */
1439 #define ADC_SQR5_SQ1_0                       (0x01U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000001 */
1440 #define ADC_SQR5_SQ1_1                       (0x02U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000002 */
1441 #define ADC_SQR5_SQ1_2                       (0x04U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000004 */
1442 #define ADC_SQR5_SQ1_3                       (0x08U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000008 */
1443 #define ADC_SQR5_SQ1_4                       (0x10U << ADC_SQR5_SQ1_Pos)       /*!< 0x00000010 */
1444 
1445 #define ADC_SQR5_SQ2_Pos                     (5U)
1446 #define ADC_SQR5_SQ2_Msk                     (0x1FU << ADC_SQR5_SQ2_Pos)       /*!< 0x000003E0 */
1447 #define ADC_SQR5_SQ2                         ADC_SQR5_SQ2_Msk                  /*!< ADC group regular sequencer rank 2 */
1448 #define ADC_SQR5_SQ2_0                       (0x01U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000020 */
1449 #define ADC_SQR5_SQ2_1                       (0x02U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000040 */
1450 #define ADC_SQR5_SQ2_2                       (0x04U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000080 */
1451 #define ADC_SQR5_SQ2_3                       (0x08U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000100 */
1452 #define ADC_SQR5_SQ2_4                       (0x10U << ADC_SQR5_SQ2_Pos)       /*!< 0x00000200 */
1453 
1454 #define ADC_SQR5_SQ3_Pos                     (10U)
1455 #define ADC_SQR5_SQ3_Msk                     (0x1FU << ADC_SQR5_SQ3_Pos)       /*!< 0x00007C00 */
1456 #define ADC_SQR5_SQ3                         ADC_SQR5_SQ3_Msk                  /*!< ADC group regular sequencer rank 3 */
1457 #define ADC_SQR5_SQ3_0                       (0x01U << ADC_SQR5_SQ3_Pos)       /*!< 0x00000400 */
1458 #define ADC_SQR5_SQ3_1                       (0x02U << ADC_SQR5_SQ3_Pos)       /*!< 0x00000800 */
1459 #define ADC_SQR5_SQ3_2                       (0x04U << ADC_SQR5_SQ3_Pos)       /*!< 0x00001000 */
1460 #define ADC_SQR5_SQ3_3                       (0x08U << ADC_SQR5_SQ3_Pos)       /*!< 0x00002000 */
1461 #define ADC_SQR5_SQ3_4                       (0x10U << ADC_SQR5_SQ3_Pos)       /*!< 0x00004000 */
1462 
1463 #define ADC_SQR5_SQ4_Pos                     (15U)
1464 #define ADC_SQR5_SQ4_Msk                     (0x1FU << ADC_SQR5_SQ4_Pos)       /*!< 0x000F8000 */
1465 #define ADC_SQR5_SQ4                         ADC_SQR5_SQ4_Msk                  /*!< ADC group regular sequencer rank 4 */
1466 #define ADC_SQR5_SQ4_0                       (0x01U << ADC_SQR5_SQ4_Pos)       /*!< 0x00008000 */
1467 #define ADC_SQR5_SQ4_1                       (0x02U << ADC_SQR5_SQ4_Pos)       /*!< 0x00010000 */
1468 #define ADC_SQR5_SQ4_2                       (0x04U << ADC_SQR5_SQ4_Pos)       /*!< 0x00020000 */
1469 #define ADC_SQR5_SQ4_3                       (0x08U << ADC_SQR5_SQ4_Pos)       /*!< 0x00040000 */
1470 #define ADC_SQR5_SQ4_4                       (0x10U << ADC_SQR5_SQ4_Pos)       /*!< 0x00080000 */
1471 
1472 #define ADC_SQR5_SQ5_Pos                     (20U)
1473 #define ADC_SQR5_SQ5_Msk                     (0x1FU << ADC_SQR5_SQ5_Pos)       /*!< 0x01F00000 */
1474 #define ADC_SQR5_SQ5                         ADC_SQR5_SQ5_Msk                  /*!< ADC group regular sequencer rank 5 */
1475 #define ADC_SQR5_SQ5_0                       (0x01U << ADC_SQR5_SQ5_Pos)       /*!< 0x00100000 */
1476 #define ADC_SQR5_SQ5_1                       (0x02U << ADC_SQR5_SQ5_Pos)       /*!< 0x00200000 */
1477 #define ADC_SQR5_SQ5_2                       (0x04U << ADC_SQR5_SQ5_Pos)       /*!< 0x00400000 */
1478 #define ADC_SQR5_SQ5_3                       (0x08U << ADC_SQR5_SQ5_Pos)       /*!< 0x00800000 */
1479 #define ADC_SQR5_SQ5_4                       (0x10U << ADC_SQR5_SQ5_Pos)       /*!< 0x01000000 */
1480 
1481 #define ADC_SQR5_SQ6_Pos                     (25U)
1482 #define ADC_SQR5_SQ6_Msk                     (0x1FU << ADC_SQR5_SQ6_Pos)       /*!< 0x3E000000 */
1483 #define ADC_SQR5_SQ6                         ADC_SQR5_SQ6_Msk                  /*!< ADC group regular sequencer rank 6 */
1484 #define ADC_SQR5_SQ6_0                       (0x01U << ADC_SQR5_SQ6_Pos)       /*!< 0x02000000 */
1485 #define ADC_SQR5_SQ6_1                       (0x02U << ADC_SQR5_SQ6_Pos)       /*!< 0x04000000 */
1486 #define ADC_SQR5_SQ6_2                       (0x04U << ADC_SQR5_SQ6_Pos)       /*!< 0x08000000 */
1487 #define ADC_SQR5_SQ6_3                       (0x08U << ADC_SQR5_SQ6_Pos)       /*!< 0x10000000 */
1488 #define ADC_SQR5_SQ6_4                       (0x10U << ADC_SQR5_SQ6_Pos)       /*!< 0x20000000 */
1489 
1490 
1491 /*******************  Bit definition for ADC_JSQR register  *******************/
1492 #define ADC_JSQR_JSQ1_Pos                    (0U)
1493 #define ADC_JSQR_JSQ1_Msk                    (0x1FU << ADC_JSQR_JSQ1_Pos)      /*!< 0x0000001F */
1494 #define ADC_JSQR_JSQ1                        ADC_JSQR_JSQ1_Msk                 /*!< ADC group injected sequencer rank 1 */
1495 #define ADC_JSQR_JSQ1_0                      (0x01U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000001 */
1496 #define ADC_JSQR_JSQ1_1                      (0x02U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000002 */
1497 #define ADC_JSQR_JSQ1_2                      (0x04U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000004 */
1498 #define ADC_JSQR_JSQ1_3                      (0x08U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000008 */
1499 #define ADC_JSQR_JSQ1_4                      (0x10U << ADC_JSQR_JSQ1_Pos)      /*!< 0x00000010 */
1500 
1501 #define ADC_JSQR_JSQ2_Pos                    (5U)
1502 #define ADC_JSQR_JSQ2_Msk                    (0x1FU << ADC_JSQR_JSQ2_Pos)      /*!< 0x000003E0 */
1503 #define ADC_JSQR_JSQ2                        ADC_JSQR_JSQ2_Msk                 /*!< ADC group injected sequencer rank 2 */
1504 #define ADC_JSQR_JSQ2_0                      (0x01U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000020 */
1505 #define ADC_JSQR_JSQ2_1                      (0x02U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000040 */
1506 #define ADC_JSQR_JSQ2_2                      (0x04U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000080 */
1507 #define ADC_JSQR_JSQ2_3                      (0x08U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000100 */
1508 #define ADC_JSQR_JSQ2_4                      (0x10U << ADC_JSQR_JSQ2_Pos)      /*!< 0x00000200 */
1509 
1510 #define ADC_JSQR_JSQ3_Pos                    (10U)
1511 #define ADC_JSQR_JSQ3_Msk                    (0x1FU << ADC_JSQR_JSQ3_Pos)      /*!< 0x00007C00 */
1512 #define ADC_JSQR_JSQ3                        ADC_JSQR_JSQ3_Msk                 /*!< ADC group injected sequencer rank 3 */
1513 #define ADC_JSQR_JSQ3_0                      (0x01U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000400 */
1514 #define ADC_JSQR_JSQ3_1                      (0x02U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00000800 */
1515 #define ADC_JSQR_JSQ3_2                      (0x04U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00001000 */
1516 #define ADC_JSQR_JSQ3_3                      (0x08U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00002000 */
1517 #define ADC_JSQR_JSQ3_4                      (0x10U << ADC_JSQR_JSQ3_Pos)      /*!< 0x00004000 */
1518 
1519 #define ADC_JSQR_JSQ4_Pos                    (15U)
1520 #define ADC_JSQR_JSQ4_Msk                    (0x1FU << ADC_JSQR_JSQ4_Pos)      /*!< 0x000F8000 */
1521 #define ADC_JSQR_JSQ4                        ADC_JSQR_JSQ4_Msk                 /*!< ADC group injected sequencer rank 4 */
1522 #define ADC_JSQR_JSQ4_0                      (0x01U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00008000 */
1523 #define ADC_JSQR_JSQ4_1                      (0x02U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00010000 */
1524 #define ADC_JSQR_JSQ4_2                      (0x04U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00020000 */
1525 #define ADC_JSQR_JSQ4_3                      (0x08U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00040000 */
1526 #define ADC_JSQR_JSQ4_4                      (0x10U << ADC_JSQR_JSQ4_Pos)      /*!< 0x00080000 */
1527 
1528 #define ADC_JSQR_JL_Pos                      (20U)
1529 #define ADC_JSQR_JL_Msk                      (0x3U << ADC_JSQR_JL_Pos)         /*!< 0x00300000 */
1530 #define ADC_JSQR_JL                          ADC_JSQR_JL_Msk                   /*!< ADC group injected sequencer scan length */
1531 #define ADC_JSQR_JL_0                        (0x1U << ADC_JSQR_JL_Pos)         /*!< 0x00100000 */
1532 #define ADC_JSQR_JL_1                        (0x2U << ADC_JSQR_JL_Pos)         /*!< 0x00200000 */
1533 
1534 /*******************  Bit definition for ADC_JDR1 register  *******************/
1535 #define ADC_JDR1_JDATA_Pos                   (0U)
1536 #define ADC_JDR1_JDATA_Msk                   (0xFFFFU << ADC_JDR1_JDATA_Pos)   /*!< 0x0000FFFF */
1537 #define ADC_JDR1_JDATA                       ADC_JDR1_JDATA_Msk                /*!< ADC group injected sequencer rank 1 conversion data */
1538 
1539 /*******************  Bit definition for ADC_JDR2 register  *******************/
1540 #define ADC_JDR2_JDATA_Pos                   (0U)
1541 #define ADC_JDR2_JDATA_Msk                   (0xFFFFU << ADC_JDR2_JDATA_Pos)   /*!< 0x0000FFFF */
1542 #define ADC_JDR2_JDATA                       ADC_JDR2_JDATA_Msk                /*!< ADC group injected sequencer rank 2 conversion data */
1543 
1544 /*******************  Bit definition for ADC_JDR3 register  *******************/
1545 #define ADC_JDR3_JDATA_Pos                   (0U)
1546 #define ADC_JDR3_JDATA_Msk                   (0xFFFFU << ADC_JDR3_JDATA_Pos)   /*!< 0x0000FFFF */
1547 #define ADC_JDR3_JDATA                       ADC_JDR3_JDATA_Msk                /*!< ADC group injected sequencer rank 3 conversion data */
1548 
1549 /*******************  Bit definition for ADC_JDR4 register  *******************/
1550 #define ADC_JDR4_JDATA_Pos                   (0U)
1551 #define ADC_JDR4_JDATA_Msk                   (0xFFFFU << ADC_JDR4_JDATA_Pos)   /*!< 0x0000FFFF */
1552 #define ADC_JDR4_JDATA                       ADC_JDR4_JDATA_Msk                /*!< ADC group injected sequencer rank 4 conversion data */
1553 
1554 /********************  Bit definition for ADC_DR register  ********************/
1555 #define ADC_DR_DATA_Pos                      (0U)
1556 #define ADC_DR_DATA_Msk                      (0xFFFFU << ADC_DR_DATA_Pos)      /*!< 0x0000FFFF */
1557 #define ADC_DR_DATA                          ADC_DR_DATA_Msk                   /*!< ADC group regular conversion data */
1558 
1559 /*******************  Bit definition for ADC_CSR register  ********************/
1560 #define ADC_CSR_AWD1_Pos                     (0U)
1561 #define ADC_CSR_AWD1_Msk                     (0x1U << ADC_CSR_AWD1_Pos)        /*!< 0x00000001 */
1562 #define ADC_CSR_AWD1                         ADC_CSR_AWD1_Msk                  /*!< ADC multimode master analog watchdog 1 flag */
1563 #define ADC_CSR_EOCS1_Pos                    (1U)
1564 #define ADC_CSR_EOCS1_Msk                    (0x1U << ADC_CSR_EOCS1_Pos)       /*!< 0x00000002 */
1565 #define ADC_CSR_EOCS1                        ADC_CSR_EOCS1_Msk                 /*!< ADC multimode master group regular end of unitary conversion or end of sequence conversions flag */
1566 #define ADC_CSR_JEOS1_Pos                    (2U)
1567 #define ADC_CSR_JEOS1_Msk                    (0x1U << ADC_CSR_JEOS1_Pos)       /*!< 0x00000004 */
1568 #define ADC_CSR_JEOS1                        ADC_CSR_JEOS1_Msk                 /*!< ADC multimode master group injected end of sequence conversions flag */
1569 #define ADC_CSR_JSTRT1_Pos                   (3U)
1570 #define ADC_CSR_JSTRT1_Msk                   (0x1U << ADC_CSR_JSTRT1_Pos)      /*!< 0x00000008 */
1571 #define ADC_CSR_JSTRT1                       ADC_CSR_JSTRT1_Msk                /*!< ADC multimode master group injected conversion start flag */
1572 #define ADC_CSR_STRT1_Pos                    (4U)
1573 #define ADC_CSR_STRT1_Msk                    (0x1U << ADC_CSR_STRT1_Pos)       /*!< 0x00000010 */
1574 #define ADC_CSR_STRT1                        ADC_CSR_STRT1_Msk                 /*!< ADC multimode master group regular conversion start flag */
1575 #define ADC_CSR_OVR1_Pos                     (5U)
1576 #define ADC_CSR_OVR1_Msk                     (0x1U << ADC_CSR_OVR1_Pos)        /*!< 0x00000020 */
1577 #define ADC_CSR_OVR1                         ADC_CSR_OVR1_Msk                  /*!< ADC multimode master group regular overrun flag */
1578 #define ADC_CSR_ADONS1_Pos                   (6U)
1579 #define ADC_CSR_ADONS1_Msk                   (0x1U << ADC_CSR_ADONS1_Pos)      /*!< 0x00000040 */
1580 #define ADC_CSR_ADONS1                       ADC_CSR_ADONS1_Msk                /*!< ADC multimode master ready flag */
1581 
1582 /* Legacy defines */
1583 #define  ADC_CSR_EOC1                        (ADC_CSR_EOCS1)
1584 #define  ADC_CSR_JEOC1                       (ADC_CSR_JEOS1)
1585 
1586 /*******************  Bit definition for ADC_CCR register  ********************/
1587 #define ADC_CCR_ADCPRE_Pos                   (16U)
1588 #define ADC_CCR_ADCPRE_Msk                   (0x3U << ADC_CCR_ADCPRE_Pos)      /*!< 0x00030000 */
1589 #define ADC_CCR_ADCPRE                       ADC_CCR_ADCPRE_Msk                /*!< ADC clock source asynchronous prescaler */
1590 #define ADC_CCR_ADCPRE_0                     (0x1U << ADC_CCR_ADCPRE_Pos)      /*!< 0x00010000 */
1591 #define ADC_CCR_ADCPRE_1                     (0x2U << ADC_CCR_ADCPRE_Pos)      /*!< 0x00020000 */
1592 #define ADC_CCR_TSVREFE_Pos                  (23U)
1593 #define ADC_CCR_TSVREFE_Msk                  (0x1U << ADC_CCR_TSVREFE_Pos)     /*!< 0x00800000 */
1594 #define ADC_CCR_TSVREFE                      ADC_CCR_TSVREFE_Msk               /*!< ADC internal path to VrefInt and temperature sensor enable */
1595 
1596 /******************************************************************************/
1597 /*                                                                            */
1598 /*                      Analog Comparators (COMP)                             */
1599 /*                                                                            */
1600 /******************************************************************************/
1601 
1602 /******************  Bit definition for COMP_CSR register  ********************/
1603 #define COMP_CSR_10KPU                      (0x00000001U)                      /*!< Comparator 1 input plus 10K pull-up resistor */
1604 #define COMP_CSR_400KPU                     (0x00000002U)                      /*!< Comparator 1 input plus 400K pull-up resistor */
1605 #define COMP_CSR_10KPD                      (0x00000004U)                      /*!< Comparator 1 input plus 10K pull-down resistor */
1606 #define COMP_CSR_400KPD                     (0x00000008U)                      /*!< Comparator 1 input plus 400K pull-down resistor */
1607 #define COMP_CSR_CMP1EN_Pos                 (4U)
1608 #define COMP_CSR_CMP1EN_Msk                 (0x1U << COMP_CSR_CMP1EN_Pos)      /*!< 0x00000010 */
1609 #define COMP_CSR_CMP1EN                     COMP_CSR_CMP1EN_Msk                /*!< Comparator 1 enable */
1610 #define COMP_CSR_CMP1OUT_Pos                (7U)
1611 #define COMP_CSR_CMP1OUT_Msk                (0x1U << COMP_CSR_CMP1OUT_Pos)     /*!< 0x00000080 */
1612 #define COMP_CSR_CMP1OUT                    COMP_CSR_CMP1OUT_Msk               /*!< Comparator 1 output level */
1613 #define COMP_CSR_SPEED_Pos                  (12U)
1614 #define COMP_CSR_SPEED_Msk                  (0x1U << COMP_CSR_SPEED_Pos)       /*!< 0x00001000 */
1615 #define COMP_CSR_SPEED                      COMP_CSR_SPEED_Msk                 /*!< Comparator 2 power mode */
1616 #define COMP_CSR_CMP2OUT_Pos                (13U)
1617 #define COMP_CSR_CMP2OUT_Msk                (0x1U << COMP_CSR_CMP2OUT_Pos)     /*!< 0x00002000 */
1618 #define COMP_CSR_CMP2OUT                    COMP_CSR_CMP2OUT_Msk               /*!< Comparator 2 output level */
1619 
1620 #define COMP_CSR_WNDWE_Pos                  (17U)
1621 #define COMP_CSR_WNDWE_Msk                  (0x1U << COMP_CSR_WNDWE_Pos)       /*!< 0x00020000 */
1622 #define COMP_CSR_WNDWE                      COMP_CSR_WNDWE_Msk                 /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)  */
1623 
1624 #define COMP_CSR_INSEL_Pos                  (18U)
1625 #define COMP_CSR_INSEL_Msk                  (0x7U << COMP_CSR_INSEL_Pos)       /*!< 0x001C0000 */
1626 #define COMP_CSR_INSEL                      COMP_CSR_INSEL_Msk                 /*!< Comparator 2 input minus selection */
1627 #define COMP_CSR_INSEL_0                    (0x1U << COMP_CSR_INSEL_Pos)       /*!< 0x00040000 */
1628 #define COMP_CSR_INSEL_1                    (0x2U << COMP_CSR_INSEL_Pos)       /*!< 0x00080000 */
1629 #define COMP_CSR_INSEL_2                    (0x4U << COMP_CSR_INSEL_Pos)       /*!< 0x00100000 */
1630 #define COMP_CSR_OUTSEL_Pos                 (21U)
1631 #define COMP_CSR_OUTSEL_Msk                 (0x7U << COMP_CSR_OUTSEL_Pos)      /*!< 0x00E00000 */
1632 #define COMP_CSR_OUTSEL                     COMP_CSR_OUTSEL_Msk                /*!< Comparator 2 output redirection */
1633 #define COMP_CSR_OUTSEL_0                   (0x1U << COMP_CSR_OUTSEL_Pos)      /*!< 0x00200000 */
1634 #define COMP_CSR_OUTSEL_1                   (0x2U << COMP_CSR_OUTSEL_Pos)      /*!< 0x00400000 */
1635 #define COMP_CSR_OUTSEL_2                   (0x4U << COMP_CSR_OUTSEL_Pos)      /*!< 0x00800000 */
1636 
1637 /* Bits present in COMP register but not related to comparator */
1638 /* (or partially related to comparator, in addition to other peripherals) */
1639 #define COMP_CSR_VREFOUTEN_Pos              (16U)
1640 #define COMP_CSR_VREFOUTEN_Msk              (0x1U << COMP_CSR_VREFOUTEN_Pos)   /*!< 0x00010000 */
1641 #define COMP_CSR_VREFOUTEN                  COMP_CSR_VREFOUTEN_Msk             /*!< VrefInt output enable on GPIO group 3 */
1642 
1643 #define COMP_CSR_FCH3_Pos                   (26U)
1644 #define COMP_CSR_FCH3_Msk                   (0x1U << COMP_CSR_FCH3_Pos)        /*!< 0x04000000 */
1645 #define COMP_CSR_FCH3                       COMP_CSR_FCH3_Msk                  /*!< Bit 26 */
1646 #define COMP_CSR_FCH8_Pos                   (27U)
1647 #define COMP_CSR_FCH8_Msk                   (0x1U << COMP_CSR_FCH8_Pos)        /*!< 0x08000000 */
1648 #define COMP_CSR_FCH8                       COMP_CSR_FCH8_Msk                  /*!< Bit 27 */
1649 #define COMP_CSR_RCH13_Pos                  (28U)
1650 #define COMP_CSR_RCH13_Msk                  (0x1U << COMP_CSR_RCH13_Pos)       /*!< 0x10000000 */
1651 #define COMP_CSR_RCH13                      COMP_CSR_RCH13_Msk                 /*!< Bit 28 */
1652 
1653 #define COMP_CSR_CAIE_Pos                   (29U)
1654 #define COMP_CSR_CAIE_Msk                   (0x1U << COMP_CSR_CAIE_Pos)        /*!< 0x20000000 */
1655 #define COMP_CSR_CAIE                       COMP_CSR_CAIE_Msk                  /*!< Bit 29 */
1656 #define COMP_CSR_CAIF_Pos                   (30U)
1657 #define COMP_CSR_CAIF_Msk                   (0x1U << COMP_CSR_CAIF_Pos)        /*!< 0x40000000 */
1658 #define COMP_CSR_CAIF                       COMP_CSR_CAIF_Msk                  /*!< Bit 30 */
1659 #define COMP_CSR_TSUSP_Pos                  (31U)
1660 #define COMP_CSR_TSUSP_Msk                  (0x1U << COMP_CSR_TSUSP_Pos)       /*!< 0x80000000 */
1661 #define COMP_CSR_TSUSP                      COMP_CSR_TSUSP_Msk                 /*!< Bit 31 */
1662 
1663 /******************************************************************************/
1664 /*                                                                            */
1665 /*                         Operational Amplifier (OPAMP)                      */
1666 /*                                                                            */
1667 /******************************************************************************/
1668 /*******************  Bit definition for OPAMP_CSR register  ******************/
1669 #define OPAMP_CSR_OPA1PD_Pos                  (0U)
1670 #define OPAMP_CSR_OPA1PD_Msk                  (0x1U << OPAMP_CSR_OPA1PD_Pos)   /*!< 0x00000001 */
1671 #define OPAMP_CSR_OPA1PD                      OPAMP_CSR_OPA1PD_Msk             /*!< OPAMP1 disable */
1672 #define OPAMP_CSR_S3SEL1_Pos                  (1U)
1673 #define OPAMP_CSR_S3SEL1_Msk                  (0x1U << OPAMP_CSR_S3SEL1_Pos)   /*!< 0x00000002 */
1674 #define OPAMP_CSR_S3SEL1                      OPAMP_CSR_S3SEL1_Msk             /*!< Switch 3 for OPAMP1 Enable */
1675 #define OPAMP_CSR_S4SEL1_Pos                  (2U)
1676 #define OPAMP_CSR_S4SEL1_Msk                  (0x1U << OPAMP_CSR_S4SEL1_Pos)   /*!< 0x00000004 */
1677 #define OPAMP_CSR_S4SEL1                      OPAMP_CSR_S4SEL1_Msk             /*!< Switch 4 for OPAMP1 Enable */
1678 #define OPAMP_CSR_S5SEL1_Pos                  (3U)
1679 #define OPAMP_CSR_S5SEL1_Msk                  (0x1U << OPAMP_CSR_S5SEL1_Pos)   /*!< 0x00000008 */
1680 #define OPAMP_CSR_S5SEL1                      OPAMP_CSR_S5SEL1_Msk             /*!< Switch 5 for OPAMP1 Enable */
1681 #define OPAMP_CSR_S6SEL1_Pos                  (4U)
1682 #define OPAMP_CSR_S6SEL1_Msk                  (0x1U << OPAMP_CSR_S6SEL1_Pos)   /*!< 0x00000010 */
1683 #define OPAMP_CSR_S6SEL1                      OPAMP_CSR_S6SEL1_Msk             /*!< Switch 6 for OPAMP1 Enable */
1684 #define OPAMP_CSR_OPA1CAL_L_Pos               (5U)
1685 #define OPAMP_CSR_OPA1CAL_L_Msk               (0x1U << OPAMP_CSR_OPA1CAL_L_Pos) /*!< 0x00000020 */
1686 #define OPAMP_CSR_OPA1CAL_L                   OPAMP_CSR_OPA1CAL_L_Msk          /*!< OPAMP1 Offset calibration for P differential pair */
1687 #define OPAMP_CSR_OPA1CAL_H_Pos               (6U)
1688 #define OPAMP_CSR_OPA1CAL_H_Msk               (0x1U << OPAMP_CSR_OPA1CAL_H_Pos) /*!< 0x00000040 */
1689 #define OPAMP_CSR_OPA1CAL_H                   OPAMP_CSR_OPA1CAL_H_Msk          /*!< OPAMP1 Offset calibration for N differential pair */
1690 #define OPAMP_CSR_OPA1LPM_Pos                 (7U)
1691 #define OPAMP_CSR_OPA1LPM_Msk                 (0x1U << OPAMP_CSR_OPA1LPM_Pos)  /*!< 0x00000080 */
1692 #define OPAMP_CSR_OPA1LPM                     OPAMP_CSR_OPA1LPM_Msk            /*!< OPAMP1 Low power enable */
1693 #define OPAMP_CSR_OPA2PD_Pos                  (8U)
1694 #define OPAMP_CSR_OPA2PD_Msk                  (0x1U << OPAMP_CSR_OPA2PD_Pos)   /*!< 0x00000100 */
1695 #define OPAMP_CSR_OPA2PD                      OPAMP_CSR_OPA2PD_Msk             /*!< OPAMP2 disable */
1696 #define OPAMP_CSR_S3SEL2_Pos                  (9U)
1697 #define OPAMP_CSR_S3SEL2_Msk                  (0x1U << OPAMP_CSR_S3SEL2_Pos)   /*!< 0x00000200 */
1698 #define OPAMP_CSR_S3SEL2                      OPAMP_CSR_S3SEL2_Msk             /*!< Switch 3 for OPAMP2 Enable */
1699 #define OPAMP_CSR_S4SEL2_Pos                  (10U)
1700 #define OPAMP_CSR_S4SEL2_Msk                  (0x1U << OPAMP_CSR_S4SEL2_Pos)   /*!< 0x00000400 */
1701 #define OPAMP_CSR_S4SEL2                      OPAMP_CSR_S4SEL2_Msk             /*!< Switch 4 for OPAMP2 Enable */
1702 #define OPAMP_CSR_S5SEL2_Pos                  (11U)
1703 #define OPAMP_CSR_S5SEL2_Msk                  (0x1U << OPAMP_CSR_S5SEL2_Pos)   /*!< 0x00000800 */
1704 #define OPAMP_CSR_S5SEL2                      OPAMP_CSR_S5SEL2_Msk             /*!< Switch 5 for OPAMP2 Enable */
1705 #define OPAMP_CSR_S6SEL2_Pos                  (12U)
1706 #define OPAMP_CSR_S6SEL2_Msk                  (0x1U << OPAMP_CSR_S6SEL2_Pos)   /*!< 0x00001000 */
1707 #define OPAMP_CSR_S6SEL2                      OPAMP_CSR_S6SEL2_Msk             /*!< Switch 6 for OPAMP2 Enable */
1708 #define OPAMP_CSR_OPA2CAL_L_Pos               (13U)
1709 #define OPAMP_CSR_OPA2CAL_L_Msk               (0x1U << OPAMP_CSR_OPA2CAL_L_Pos) /*!< 0x00002000 */
1710 #define OPAMP_CSR_OPA2CAL_L                   OPAMP_CSR_OPA2CAL_L_Msk          /*!< OPAMP2 Offset calibration for P differential pair */
1711 #define OPAMP_CSR_OPA2CAL_H_Pos               (14U)
1712 #define OPAMP_CSR_OPA2CAL_H_Msk               (0x1U << OPAMP_CSR_OPA2CAL_H_Pos) /*!< 0x00004000 */
1713 #define OPAMP_CSR_OPA2CAL_H                   OPAMP_CSR_OPA2CAL_H_Msk          /*!< OPAMP2 Offset calibration for N differential pair */
1714 #define OPAMP_CSR_OPA2LPM_Pos                 (15U)
1715 #define OPAMP_CSR_OPA2LPM_Msk                 (0x1U << OPAMP_CSR_OPA2LPM_Pos)  /*!< 0x00008000 */
1716 #define OPAMP_CSR_OPA2LPM                     OPAMP_CSR_OPA2LPM_Msk            /*!< OPAMP2 Low power enable */
1717 #define OPAMP_CSR_ANAWSEL1_Pos                (24U)
1718 #define OPAMP_CSR_ANAWSEL1_Msk                (0x1U << OPAMP_CSR_ANAWSEL1_Pos) /*!< 0x01000000 */
1719 #define OPAMP_CSR_ANAWSEL1                    OPAMP_CSR_ANAWSEL1_Msk           /*!< Switch ANA Enable for OPAMP1 */
1720 #define OPAMP_CSR_ANAWSEL2_Pos                (25U)
1721 #define OPAMP_CSR_ANAWSEL2_Msk                (0x1U << OPAMP_CSR_ANAWSEL2_Pos) /*!< 0x02000000 */
1722 #define OPAMP_CSR_ANAWSEL2                    OPAMP_CSR_ANAWSEL2_Msk           /*!< Switch ANA Enable for OPAMP2 */
1723 #define OPAMP_CSR_S7SEL2_Pos                  (27U)
1724 #define OPAMP_CSR_S7SEL2_Msk                  (0x1U << OPAMP_CSR_S7SEL2_Pos)   /*!< 0x08000000 */
1725 #define OPAMP_CSR_S7SEL2                      OPAMP_CSR_S7SEL2_Msk             /*!< Switch 7 for OPAMP2 Enable */
1726 #define OPAMP_CSR_AOP_RANGE_Pos               (28U)
1727 #define OPAMP_CSR_AOP_RANGE_Msk               (0x1U << OPAMP_CSR_AOP_RANGE_Pos) /*!< 0x10000000 */
1728 #define OPAMP_CSR_AOP_RANGE                   OPAMP_CSR_AOP_RANGE_Msk          /*!< Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef) */
1729 #define OPAMP_CSR_OPA1CALOUT_Pos              (29U)
1730 #define OPAMP_CSR_OPA1CALOUT_Msk              (0x1U << OPAMP_CSR_OPA1CALOUT_Pos) /*!< 0x20000000 */
1731 #define OPAMP_CSR_OPA1CALOUT                  OPAMP_CSR_OPA1CALOUT_Msk         /*!< OPAMP1 calibration output */
1732 #define OPAMP_CSR_OPA2CALOUT_Pos              (30U)
1733 #define OPAMP_CSR_OPA2CALOUT_Msk              (0x1U << OPAMP_CSR_OPA2CALOUT_Pos) /*!< 0x40000000 */
1734 #define OPAMP_CSR_OPA2CALOUT                  OPAMP_CSR_OPA2CALOUT_Msk         /*!< OPAMP2 calibration output */
1735 
1736 /*******************  Bit definition for OPAMP_OTR register  ******************/
1737 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos (0U)
1738 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x0000001F */
1739 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
1740 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos (5U)
1741 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000003E0 */
1742 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
1743 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos (10U)
1744 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos) /*!< 0x00007C00 */
1745 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW     OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
1746 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos (15U)
1747 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos) /*!< 0x000F8000 */
1748 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH    OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
1749 #define OPAMP_OTR_OT_USER_Pos                 (31U)
1750 #define OPAMP_OTR_OT_USER_Msk                 (0x1U << OPAMP_OTR_OT_USER_Pos)  /*!< 0x80000000 */
1751 #define OPAMP_OTR_OT_USER                     OPAMP_OTR_OT_USER_Msk            /*!< Switch to OPAMP offset user trimmed values */
1752 
1753 /*******************  Bit definition for OPAMP_LPOTR register  ****************/
1754 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos (0U)
1755 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x0000001F */
1756 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
1757 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos (5U)
1758 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000003E0 */
1759 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
1760 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos (10U)
1761 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos) /*!< 0x00007C00 */
1762 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
1763 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos (15U)
1764 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos) /*!< 0x000F8000 */
1765 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
1766 
1767 /******************************************************************************/
1768 /*                                                                            */
1769 /*                       CRC calculation unit (CRC)                           */
1770 /*                                                                            */
1771 /******************************************************************************/
1772 
1773 /*******************  Bit definition for CRC_DR register  *********************/
1774 #define CRC_DR_DR_Pos                       (0U)
1775 #define CRC_DR_DR_Msk                       (0xFFFFFFFFU << CRC_DR_DR_Pos)     /*!< 0xFFFFFFFF */
1776 #define CRC_DR_DR                           CRC_DR_DR_Msk                      /*!< Data register bits */
1777 
1778 /*******************  Bit definition for CRC_IDR register  ********************/
1779 #define CRC_IDR_IDR_Pos                     (0U)
1780 #define CRC_IDR_IDR_Msk                     (0xFFU << CRC_IDR_IDR_Pos)         /*!< 0x000000FF */
1781 #define CRC_IDR_IDR                         CRC_IDR_IDR_Msk                    /*!< General-purpose 8-bit data register bits */
1782 
1783 /********************  Bit definition for CRC_CR register  ********************/
1784 #define CRC_CR_RESET_Pos                    (0U)
1785 #define CRC_CR_RESET_Msk                    (0x1U << CRC_CR_RESET_Pos)         /*!< 0x00000001 */
1786 #define CRC_CR_RESET                        CRC_CR_RESET_Msk                   /*!< RESET bit */
1787 
1788 /******************************************************************************/
1789 /*                                                                            */
1790 /*                    Digital to Analog Converter (DAC)                       */
1791 /*                                                                            */
1792 /******************************************************************************/
1793 
1794 /********************  Bit definition for DAC_CR register  ********************/
1795 #define DAC_CR_EN1_Pos                      (0U)
1796 #define DAC_CR_EN1_Msk                      (0x1U << DAC_CR_EN1_Pos)           /*!< 0x00000001 */
1797 #define DAC_CR_EN1                          DAC_CR_EN1_Msk                     /*!<DAC channel1 enable */
1798 #define DAC_CR_BOFF1_Pos                    (1U)
1799 #define DAC_CR_BOFF1_Msk                    (0x1U << DAC_CR_BOFF1_Pos)         /*!< 0x00000002 */
1800 #define DAC_CR_BOFF1                        DAC_CR_BOFF1_Msk                   /*!<DAC channel1 output buffer disable */
1801 #define DAC_CR_TEN1_Pos                     (2U)
1802 #define DAC_CR_TEN1_Msk                     (0x1U << DAC_CR_TEN1_Pos)          /*!< 0x00000004 */
1803 #define DAC_CR_TEN1                         DAC_CR_TEN1_Msk                    /*!<DAC channel1 Trigger enable */
1804 
1805 #define DAC_CR_TSEL1_Pos                    (3U)
1806 #define DAC_CR_TSEL1_Msk                    (0x7U << DAC_CR_TSEL1_Pos)         /*!< 0x00000038 */
1807 #define DAC_CR_TSEL1                        DAC_CR_TSEL1_Msk                   /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
1808 #define DAC_CR_TSEL1_0                      (0x1U << DAC_CR_TSEL1_Pos)         /*!< 0x00000008 */
1809 #define DAC_CR_TSEL1_1                      (0x2U << DAC_CR_TSEL1_Pos)         /*!< 0x00000010 */
1810 #define DAC_CR_TSEL1_2                      (0x4U << DAC_CR_TSEL1_Pos)         /*!< 0x00000020 */
1811 
1812 #define DAC_CR_WAVE1_Pos                    (6U)
1813 #define DAC_CR_WAVE1_Msk                    (0x3U << DAC_CR_WAVE1_Pos)         /*!< 0x000000C0 */
1814 #define DAC_CR_WAVE1                        DAC_CR_WAVE1_Msk                   /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
1815 #define DAC_CR_WAVE1_0                      (0x1U << DAC_CR_WAVE1_Pos)         /*!< 0x00000040 */
1816 #define DAC_CR_WAVE1_1                      (0x2U << DAC_CR_WAVE1_Pos)         /*!< 0x00000080 */
1817 
1818 #define DAC_CR_MAMP1_Pos                    (8U)
1819 #define DAC_CR_MAMP1_Msk                    (0xFU << DAC_CR_MAMP1_Pos)         /*!< 0x00000F00 */
1820 #define DAC_CR_MAMP1                        DAC_CR_MAMP1_Msk                   /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
1821 #define DAC_CR_MAMP1_0                      (0x1U << DAC_CR_MAMP1_Pos)         /*!< 0x00000100 */
1822 #define DAC_CR_MAMP1_1                      (0x2U << DAC_CR_MAMP1_Pos)         /*!< 0x00000200 */
1823 #define DAC_CR_MAMP1_2                      (0x4U << DAC_CR_MAMP1_Pos)         /*!< 0x00000400 */
1824 #define DAC_CR_MAMP1_3                      (0x8U << DAC_CR_MAMP1_Pos)         /*!< 0x00000800 */
1825 
1826 #define DAC_CR_DMAEN1_Pos                   (12U)
1827 #define DAC_CR_DMAEN1_Msk                   (0x1U << DAC_CR_DMAEN1_Pos)        /*!< 0x00001000 */
1828 #define DAC_CR_DMAEN1                       DAC_CR_DMAEN1_Msk                  /*!<DAC channel1 DMA enable */
1829 #define DAC_CR_DMAUDRIE1_Pos                (13U)
1830 #define DAC_CR_DMAUDRIE1_Msk                (0x1U << DAC_CR_DMAUDRIE1_Pos)     /*!< 0x00002000 */
1831 #define DAC_CR_DMAUDRIE1                    DAC_CR_DMAUDRIE1_Msk               /*!<DAC channel1 DMA Interrupt enable */
1832 #define DAC_CR_EN2_Pos                      (16U)
1833 #define DAC_CR_EN2_Msk                      (0x1U << DAC_CR_EN2_Pos)           /*!< 0x00010000 */
1834 #define DAC_CR_EN2                          DAC_CR_EN2_Msk                     /*!<DAC channel2 enable */
1835 #define DAC_CR_BOFF2_Pos                    (17U)
1836 #define DAC_CR_BOFF2_Msk                    (0x1U << DAC_CR_BOFF2_Pos)         /*!< 0x00020000 */
1837 #define DAC_CR_BOFF2                        DAC_CR_BOFF2_Msk                   /*!<DAC channel2 output buffer disable */
1838 #define DAC_CR_TEN2_Pos                     (18U)
1839 #define DAC_CR_TEN2_Msk                     (0x1U << DAC_CR_TEN2_Pos)          /*!< 0x00040000 */
1840 #define DAC_CR_TEN2                         DAC_CR_TEN2_Msk                    /*!<DAC channel2 Trigger enable */
1841 
1842 #define DAC_CR_TSEL2_Pos                    (19U)
1843 #define DAC_CR_TSEL2_Msk                    (0x7U << DAC_CR_TSEL2_Pos)         /*!< 0x00380000 */
1844 #define DAC_CR_TSEL2                        DAC_CR_TSEL2_Msk                   /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
1845 #define DAC_CR_TSEL2_0                      (0x1U << DAC_CR_TSEL2_Pos)         /*!< 0x00080000 */
1846 #define DAC_CR_TSEL2_1                      (0x2U << DAC_CR_TSEL2_Pos)         /*!< 0x00100000 */
1847 #define DAC_CR_TSEL2_2                      (0x4U << DAC_CR_TSEL2_Pos)         /*!< 0x00200000 */
1848 
1849 #define DAC_CR_WAVE2_Pos                    (22U)
1850 #define DAC_CR_WAVE2_Msk                    (0x3U << DAC_CR_WAVE2_Pos)         /*!< 0x00C00000 */
1851 #define DAC_CR_WAVE2                        DAC_CR_WAVE2_Msk                   /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
1852 #define DAC_CR_WAVE2_0                      (0x1U << DAC_CR_WAVE2_Pos)         /*!< 0x00400000 */
1853 #define DAC_CR_WAVE2_1                      (0x2U << DAC_CR_WAVE2_Pos)         /*!< 0x00800000 */
1854 
1855 #define DAC_CR_MAMP2_Pos                    (24U)
1856 #define DAC_CR_MAMP2_Msk                    (0xFU << DAC_CR_MAMP2_Pos)         /*!< 0x0F000000 */
1857 #define DAC_CR_MAMP2                        DAC_CR_MAMP2_Msk                   /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
1858 #define DAC_CR_MAMP2_0                      (0x1U << DAC_CR_MAMP2_Pos)         /*!< 0x01000000 */
1859 #define DAC_CR_MAMP2_1                      (0x2U << DAC_CR_MAMP2_Pos)         /*!< 0x02000000 */
1860 #define DAC_CR_MAMP2_2                      (0x4U << DAC_CR_MAMP2_Pos)         /*!< 0x04000000 */
1861 #define DAC_CR_MAMP2_3                      (0x8U << DAC_CR_MAMP2_Pos)         /*!< 0x08000000 */
1862 
1863 #define DAC_CR_DMAEN2_Pos                   (28U)
1864 #define DAC_CR_DMAEN2_Msk                   (0x1U << DAC_CR_DMAEN2_Pos)        /*!< 0x10000000 */
1865 #define DAC_CR_DMAEN2                       DAC_CR_DMAEN2_Msk                  /*!<DAC channel2 DMA enabled */
1866 #define DAC_CR_DMAUDRIE2_Pos                (29U)
1867 #define DAC_CR_DMAUDRIE2_Msk                (0x1U << DAC_CR_DMAUDRIE2_Pos)     /*!< 0x20000000 */
1868 #define DAC_CR_DMAUDRIE2                    DAC_CR_DMAUDRIE2_Msk               /*!<DAC channel2 DMA underrun interrupt enable */
1869 /*****************  Bit definition for DAC_SWTRIGR register  ******************/
1870 #define DAC_SWTRIGR_SWTRIG1_Pos             (0U)
1871 #define DAC_SWTRIGR_SWTRIG1_Msk             (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)  /*!< 0x00000001 */
1872 #define DAC_SWTRIGR_SWTRIG1                 DAC_SWTRIGR_SWTRIG1_Msk            /*!<DAC channel1 software trigger */
1873 #define DAC_SWTRIGR_SWTRIG2_Pos             (1U)
1874 #define DAC_SWTRIGR_SWTRIG2_Msk             (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)  /*!< 0x00000002 */
1875 #define DAC_SWTRIGR_SWTRIG2                 DAC_SWTRIGR_SWTRIG2_Msk            /*!<DAC channel2 software trigger */
1876 
1877 /*****************  Bit definition for DAC_DHR12R1 register  ******************/
1878 #define DAC_DHR12R1_DACC1DHR_Pos            (0U)
1879 #define DAC_DHR12R1_DACC1DHR_Msk            (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
1880 #define DAC_DHR12R1_DACC1DHR                DAC_DHR12R1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
1881 
1882 /*****************  Bit definition for DAC_DHR12L1 register  ******************/
1883 #define DAC_DHR12L1_DACC1DHR_Pos            (4U)
1884 #define DAC_DHR12L1_DACC1DHR_Msk            (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1885 #define DAC_DHR12L1_DACC1DHR                DAC_DHR12L1_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
1886 
1887 /******************  Bit definition for DAC_DHR8R1 register  ******************/
1888 #define DAC_DHR8R1_DACC1DHR_Pos             (0U)
1889 #define DAC_DHR8R1_DACC1DHR_Msk             (0xFFU << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
1890 #define DAC_DHR8R1_DACC1DHR                 DAC_DHR8R1_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
1891 
1892 /*****************  Bit definition for DAC_DHR12R2 register  ******************/
1893 #define DAC_DHR12R2_DACC2DHR_Pos            (0U)
1894 #define DAC_DHR12R2_DACC2DHR_Msk            (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
1895 #define DAC_DHR12R2_DACC2DHR                DAC_DHR12R2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
1896 
1897 /*****************  Bit definition for DAC_DHR12L2 register  ******************/
1898 #define DAC_DHR12L2_DACC2DHR_Pos            (4U)
1899 #define DAC_DHR12L2_DACC2DHR_Msk            (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
1900 #define DAC_DHR12L2_DACC2DHR                DAC_DHR12L2_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
1901 
1902 /******************  Bit definition for DAC_DHR8R2 register  ******************/
1903 #define DAC_DHR8R2_DACC2DHR_Pos             (0U)
1904 #define DAC_DHR8R2_DACC2DHR_Msk             (0xFFU << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
1905 #define DAC_DHR8R2_DACC2DHR                 DAC_DHR8R2_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
1906 
1907 /*****************  Bit definition for DAC_DHR12RD register  ******************/
1908 #define DAC_DHR12RD_DACC1DHR_Pos            (0U)
1909 #define DAC_DHR12RD_DACC1DHR_Msk            (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
1910 #define DAC_DHR12RD_DACC1DHR                DAC_DHR12RD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Right aligned data */
1911 #define DAC_DHR12RD_DACC2DHR_Pos            (16U)
1912 #define DAC_DHR12RD_DACC2DHR_Msk            (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
1913 #define DAC_DHR12RD_DACC2DHR                DAC_DHR12RD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Right aligned data */
1914 
1915 /*****************  Bit definition for DAC_DHR12LD register  ******************/
1916 #define DAC_DHR12LD_DACC1DHR_Pos            (4U)
1917 #define DAC_DHR12LD_DACC1DHR_Msk            (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
1918 #define DAC_DHR12LD_DACC1DHR                DAC_DHR12LD_DACC1DHR_Msk           /*!<DAC channel1 12-bit Left aligned data */
1919 #define DAC_DHR12LD_DACC2DHR_Pos            (20U)
1920 #define DAC_DHR12LD_DACC2DHR_Msk            (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
1921 #define DAC_DHR12LD_DACC2DHR                DAC_DHR12LD_DACC2DHR_Msk           /*!<DAC channel2 12-bit Left aligned data */
1922 
1923 /******************  Bit definition for DAC_DHR8RD register  ******************/
1924 #define DAC_DHR8RD_DACC1DHR_Pos             (0U)
1925 #define DAC_DHR8RD_DACC1DHR_Msk             (0xFFU << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
1926 #define DAC_DHR8RD_DACC1DHR                 DAC_DHR8RD_DACC1DHR_Msk            /*!<DAC channel1 8-bit Right aligned data */
1927 #define DAC_DHR8RD_DACC2DHR_Pos             (8U)
1928 #define DAC_DHR8RD_DACC2DHR_Msk             (0xFFU << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
1929 #define DAC_DHR8RD_DACC2DHR                 DAC_DHR8RD_DACC2DHR_Msk            /*!<DAC channel2 8-bit Right aligned data */
1930 
1931 /*******************  Bit definition for DAC_DOR1 register  *******************/
1932 #define DAC_DOR1_DACC1DOR_Pos               (0U)
1933 #define DAC_DOR1_DACC1DOR_Msk               (0xFFFU << DAC_DOR1_DACC1DOR_Pos)  /*!< 0x00000FFF */
1934 #define DAC_DOR1_DACC1DOR                   DAC_DOR1_DACC1DOR_Msk              /*!<DAC channel1 data output */
1935 
1936 /*******************  Bit definition for DAC_DOR2 register  *******************/
1937 #define DAC_DOR2_DACC2DOR_Pos               (0U)
1938 #define DAC_DOR2_DACC2DOR_Msk               (0xFFFU << DAC_DOR2_DACC2DOR_Pos)  /*!< 0x00000FFF */
1939 #define DAC_DOR2_DACC2DOR                   DAC_DOR2_DACC2DOR_Msk              /*!<DAC channel2 data output */
1940 
1941 /********************  Bit definition for DAC_SR register  ********************/
1942 #define DAC_SR_DMAUDR1_Pos                  (13U)
1943 #define DAC_SR_DMAUDR1_Msk                  (0x1U << DAC_SR_DMAUDR1_Pos)       /*!< 0x00002000 */
1944 #define DAC_SR_DMAUDR1                      DAC_SR_DMAUDR1_Msk                 /*!<DAC channel1 DMA underrun flag */
1945 #define DAC_SR_DMAUDR2_Pos                  (29U)
1946 #define DAC_SR_DMAUDR2_Msk                  (0x1U << DAC_SR_DMAUDR2_Pos)       /*!< 0x20000000 */
1947 #define DAC_SR_DMAUDR2                      DAC_SR_DMAUDR2_Msk                 /*!<DAC channel2 DMA underrun flag */
1948 
1949 /******************************************************************************/
1950 /*                                                                            */
1951 /*                           Debug MCU (DBGMCU)                               */
1952 /*                                                                            */
1953 /******************************************************************************/
1954 
1955 /****************  Bit definition for DBGMCU_IDCODE register  *****************/
1956 #define DBGMCU_IDCODE_DEV_ID_Pos                 (0U)
1957 #define DBGMCU_IDCODE_DEV_ID_Msk                 (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
1958 #define DBGMCU_IDCODE_DEV_ID                     DBGMCU_IDCODE_DEV_ID_Msk      /*!< Device Identifier */
1959 
1960 #define DBGMCU_IDCODE_REV_ID_Pos                 (16U)
1961 #define DBGMCU_IDCODE_REV_ID_Msk                 (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
1962 #define DBGMCU_IDCODE_REV_ID                     DBGMCU_IDCODE_REV_ID_Msk      /*!< REV_ID[15:0] bits (Revision Identifier) */
1963 #define DBGMCU_IDCODE_REV_ID_0                   (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
1964 #define DBGMCU_IDCODE_REV_ID_1                   (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
1965 #define DBGMCU_IDCODE_REV_ID_2                   (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
1966 #define DBGMCU_IDCODE_REV_ID_3                   (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
1967 #define DBGMCU_IDCODE_REV_ID_4                   (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
1968 #define DBGMCU_IDCODE_REV_ID_5                   (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
1969 #define DBGMCU_IDCODE_REV_ID_6                   (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
1970 #define DBGMCU_IDCODE_REV_ID_7                   (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
1971 #define DBGMCU_IDCODE_REV_ID_8                   (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
1972 #define DBGMCU_IDCODE_REV_ID_9                   (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
1973 #define DBGMCU_IDCODE_REV_ID_10                  (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
1974 #define DBGMCU_IDCODE_REV_ID_11                  (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
1975 #define DBGMCU_IDCODE_REV_ID_12                  (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
1976 #define DBGMCU_IDCODE_REV_ID_13                  (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
1977 #define DBGMCU_IDCODE_REV_ID_14                  (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
1978 #define DBGMCU_IDCODE_REV_ID_15                  (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
1979 
1980 /******************  Bit definition for DBGMCU_CR register  *******************/
1981 #define DBGMCU_CR_DBG_SLEEP_Pos                  (0U)
1982 #define DBGMCU_CR_DBG_SLEEP_Msk                  (0x1U << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */
1983 #define DBGMCU_CR_DBG_SLEEP                      DBGMCU_CR_DBG_SLEEP_Msk       /*!< Debug Sleep Mode */
1984 #define DBGMCU_CR_DBG_STOP_Pos                   (1U)
1985 #define DBGMCU_CR_DBG_STOP_Msk                   (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
1986 #define DBGMCU_CR_DBG_STOP                       DBGMCU_CR_DBG_STOP_Msk        /*!< Debug Stop Mode */
1987 #define DBGMCU_CR_DBG_STANDBY_Pos                (2U)
1988 #define DBGMCU_CR_DBG_STANDBY_Msk                (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
1989 #define DBGMCU_CR_DBG_STANDBY                    DBGMCU_CR_DBG_STANDBY_Msk     /*!< Debug Standby mode */
1990 #define DBGMCU_CR_TRACE_IOEN_Pos                 (5U)
1991 #define DBGMCU_CR_TRACE_IOEN_Msk                 (0x1U << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */
1992 #define DBGMCU_CR_TRACE_IOEN                     DBGMCU_CR_TRACE_IOEN_Msk      /*!< Trace Pin Assignment Control */
1993 
1994 #define DBGMCU_CR_TRACE_MODE_Pos                 (6U)
1995 #define DBGMCU_CR_TRACE_MODE_Msk                 (0x3U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */
1996 #define DBGMCU_CR_TRACE_MODE                     DBGMCU_CR_TRACE_MODE_Msk      /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
1997 #define DBGMCU_CR_TRACE_MODE_0                   (0x1U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */
1998 #define DBGMCU_CR_TRACE_MODE_1                   (0x2U << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */
1999 
2000 /******************  Bit definition for DBGMCU_APB1_FZ register  **************/
2001 
2002 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos         (0U)
2003 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
2004 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP             DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
2005 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos         (1U)
2006 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
2007 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP             DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
2008 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos         (2U)
2009 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */
2010 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP             DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */
2011 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos         (3U)
2012 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */
2013 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP             DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */
2014 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos         (4U)
2015 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */
2016 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP             DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */
2017 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos         (5U)
2018 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */
2019 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP             DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */
2020 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos          (10U)
2021 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk          (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
2022 #define DBGMCU_APB1_FZ_DBG_RTC_STOP              DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Counter stopped when Core is halted */
2023 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos         (11U)
2024 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
2025 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP             DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
2026 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos         (12U)
2027 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk         (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
2028 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP             DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
2029 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
2030 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
2031 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
2032 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)
2033 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */
2034 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */
2035 
2036 /******************  Bit definition for DBGMCU_APB2_FZ register  **************/
2037 
2038 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos         (2U)
2039 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk         (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00000004 */
2040 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP             DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk /*!< TIM9 counter stopped when core is halted */
2041 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos        (3U)
2042 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk        (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00000008 */
2043 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP            DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk /*!< TIM10 counter stopped when core is halted */
2044 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos        (4U)
2045 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk        (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00000010 */
2046 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP            DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk /*!< TIM11 counter stopped when core is halted */
2047 
2048 /******************************************************************************/
2049 /*                                                                            */
2050 /*                           DMA Controller (DMA)                             */
2051 /*                                                                            */
2052 /******************************************************************************/
2053 
2054 /*******************  Bit definition for DMA_ISR register  ********************/
2055 #define DMA_ISR_GIF1_Pos                    (0U)
2056 #define DMA_ISR_GIF1_Msk                    (0x1U << DMA_ISR_GIF1_Pos)         /*!< 0x00000001 */
2057 #define DMA_ISR_GIF1                        DMA_ISR_GIF1_Msk                   /*!< Channel 1 Global interrupt flag */
2058 #define DMA_ISR_TCIF1_Pos                   (1U)
2059 #define DMA_ISR_TCIF1_Msk                   (0x1U << DMA_ISR_TCIF1_Pos)        /*!< 0x00000002 */
2060 #define DMA_ISR_TCIF1                       DMA_ISR_TCIF1_Msk                  /*!< Channel 1 Transfer Complete flag */
2061 #define DMA_ISR_HTIF1_Pos                   (2U)
2062 #define DMA_ISR_HTIF1_Msk                   (0x1U << DMA_ISR_HTIF1_Pos)        /*!< 0x00000004 */
2063 #define DMA_ISR_HTIF1                       DMA_ISR_HTIF1_Msk                  /*!< Channel 1 Half Transfer flag */
2064 #define DMA_ISR_TEIF1_Pos                   (3U)
2065 #define DMA_ISR_TEIF1_Msk                   (0x1U << DMA_ISR_TEIF1_Pos)        /*!< 0x00000008 */
2066 #define DMA_ISR_TEIF1                       DMA_ISR_TEIF1_Msk                  /*!< Channel 1 Transfer Error flag */
2067 #define DMA_ISR_GIF2_Pos                    (4U)
2068 #define DMA_ISR_GIF2_Msk                    (0x1U << DMA_ISR_GIF2_Pos)         /*!< 0x00000010 */
2069 #define DMA_ISR_GIF2                        DMA_ISR_GIF2_Msk                   /*!< Channel 2 Global interrupt flag */
2070 #define DMA_ISR_TCIF2_Pos                   (5U)
2071 #define DMA_ISR_TCIF2_Msk                   (0x1U << DMA_ISR_TCIF2_Pos)        /*!< 0x00000020 */
2072 #define DMA_ISR_TCIF2                       DMA_ISR_TCIF2_Msk                  /*!< Channel 2 Transfer Complete flag */
2073 #define DMA_ISR_HTIF2_Pos                   (6U)
2074 #define DMA_ISR_HTIF2_Msk                   (0x1U << DMA_ISR_HTIF2_Pos)        /*!< 0x00000040 */
2075 #define DMA_ISR_HTIF2                       DMA_ISR_HTIF2_Msk                  /*!< Channel 2 Half Transfer flag */
2076 #define DMA_ISR_TEIF2_Pos                   (7U)
2077 #define DMA_ISR_TEIF2_Msk                   (0x1U << DMA_ISR_TEIF2_Pos)        /*!< 0x00000080 */
2078 #define DMA_ISR_TEIF2                       DMA_ISR_TEIF2_Msk                  /*!< Channel 2 Transfer Error flag */
2079 #define DMA_ISR_GIF3_Pos                    (8U)
2080 #define DMA_ISR_GIF3_Msk                    (0x1U << DMA_ISR_GIF3_Pos)         /*!< 0x00000100 */
2081 #define DMA_ISR_GIF3                        DMA_ISR_GIF3_Msk                   /*!< Channel 3 Global interrupt flag */
2082 #define DMA_ISR_TCIF3_Pos                   (9U)
2083 #define DMA_ISR_TCIF3_Msk                   (0x1U << DMA_ISR_TCIF3_Pos)        /*!< 0x00000200 */
2084 #define DMA_ISR_TCIF3                       DMA_ISR_TCIF3_Msk                  /*!< Channel 3 Transfer Complete flag */
2085 #define DMA_ISR_HTIF3_Pos                   (10U)
2086 #define DMA_ISR_HTIF3_Msk                   (0x1U << DMA_ISR_HTIF3_Pos)        /*!< 0x00000400 */
2087 #define DMA_ISR_HTIF3                       DMA_ISR_HTIF3_Msk                  /*!< Channel 3 Half Transfer flag */
2088 #define DMA_ISR_TEIF3_Pos                   (11U)
2089 #define DMA_ISR_TEIF3_Msk                   (0x1U << DMA_ISR_TEIF3_Pos)        /*!< 0x00000800 */
2090 #define DMA_ISR_TEIF3                       DMA_ISR_TEIF3_Msk                  /*!< Channel 3 Transfer Error flag */
2091 #define DMA_ISR_GIF4_Pos                    (12U)
2092 #define DMA_ISR_GIF4_Msk                    (0x1U << DMA_ISR_GIF4_Pos)         /*!< 0x00001000 */
2093 #define DMA_ISR_GIF4                        DMA_ISR_GIF4_Msk                   /*!< Channel 4 Global interrupt flag */
2094 #define DMA_ISR_TCIF4_Pos                   (13U)
2095 #define DMA_ISR_TCIF4_Msk                   (0x1U << DMA_ISR_TCIF4_Pos)        /*!< 0x00002000 */
2096 #define DMA_ISR_TCIF4                       DMA_ISR_TCIF4_Msk                  /*!< Channel 4 Transfer Complete flag */
2097 #define DMA_ISR_HTIF4_Pos                   (14U)
2098 #define DMA_ISR_HTIF4_Msk                   (0x1U << DMA_ISR_HTIF4_Pos)        /*!< 0x00004000 */
2099 #define DMA_ISR_HTIF4                       DMA_ISR_HTIF4_Msk                  /*!< Channel 4 Half Transfer flag */
2100 #define DMA_ISR_TEIF4_Pos                   (15U)
2101 #define DMA_ISR_TEIF4_Msk                   (0x1U << DMA_ISR_TEIF4_Pos)        /*!< 0x00008000 */
2102 #define DMA_ISR_TEIF4                       DMA_ISR_TEIF4_Msk                  /*!< Channel 4 Transfer Error flag */
2103 #define DMA_ISR_GIF5_Pos                    (16U)
2104 #define DMA_ISR_GIF5_Msk                    (0x1U << DMA_ISR_GIF5_Pos)         /*!< 0x00010000 */
2105 #define DMA_ISR_GIF5                        DMA_ISR_GIF5_Msk                   /*!< Channel 5 Global interrupt flag */
2106 #define DMA_ISR_TCIF5_Pos                   (17U)
2107 #define DMA_ISR_TCIF5_Msk                   (0x1U << DMA_ISR_TCIF5_Pos)        /*!< 0x00020000 */
2108 #define DMA_ISR_TCIF5                       DMA_ISR_TCIF5_Msk                  /*!< Channel 5 Transfer Complete flag */
2109 #define DMA_ISR_HTIF5_Pos                   (18U)
2110 #define DMA_ISR_HTIF5_Msk                   (0x1U << DMA_ISR_HTIF5_Pos)        /*!< 0x00040000 */
2111 #define DMA_ISR_HTIF5                       DMA_ISR_HTIF5_Msk                  /*!< Channel 5 Half Transfer flag */
2112 #define DMA_ISR_TEIF5_Pos                   (19U)
2113 #define DMA_ISR_TEIF5_Msk                   (0x1U << DMA_ISR_TEIF5_Pos)        /*!< 0x00080000 */
2114 #define DMA_ISR_TEIF5                       DMA_ISR_TEIF5_Msk                  /*!< Channel 5 Transfer Error flag */
2115 #define DMA_ISR_GIF6_Pos                    (20U)
2116 #define DMA_ISR_GIF6_Msk                    (0x1U << DMA_ISR_GIF6_Pos)         /*!< 0x00100000 */
2117 #define DMA_ISR_GIF6                        DMA_ISR_GIF6_Msk                   /*!< Channel 6 Global interrupt flag */
2118 #define DMA_ISR_TCIF6_Pos                   (21U)
2119 #define DMA_ISR_TCIF6_Msk                   (0x1U << DMA_ISR_TCIF6_Pos)        /*!< 0x00200000 */
2120 #define DMA_ISR_TCIF6                       DMA_ISR_TCIF6_Msk                  /*!< Channel 6 Transfer Complete flag */
2121 #define DMA_ISR_HTIF6_Pos                   (22U)
2122 #define DMA_ISR_HTIF6_Msk                   (0x1U << DMA_ISR_HTIF6_Pos)        /*!< 0x00400000 */
2123 #define DMA_ISR_HTIF6                       DMA_ISR_HTIF6_Msk                  /*!< Channel 6 Half Transfer flag */
2124 #define DMA_ISR_TEIF6_Pos                   (23U)
2125 #define DMA_ISR_TEIF6_Msk                   (0x1U << DMA_ISR_TEIF6_Pos)        /*!< 0x00800000 */
2126 #define DMA_ISR_TEIF6                       DMA_ISR_TEIF6_Msk                  /*!< Channel 6 Transfer Error flag */
2127 #define DMA_ISR_GIF7_Pos                    (24U)
2128 #define DMA_ISR_GIF7_Msk                    (0x1U << DMA_ISR_GIF7_Pos)         /*!< 0x01000000 */
2129 #define DMA_ISR_GIF7                        DMA_ISR_GIF7_Msk                   /*!< Channel 7 Global interrupt flag */
2130 #define DMA_ISR_TCIF7_Pos                   (25U)
2131 #define DMA_ISR_TCIF7_Msk                   (0x1U << DMA_ISR_TCIF7_Pos)        /*!< 0x02000000 */
2132 #define DMA_ISR_TCIF7                       DMA_ISR_TCIF7_Msk                  /*!< Channel 7 Transfer Complete flag */
2133 #define DMA_ISR_HTIF7_Pos                   (26U)
2134 #define DMA_ISR_HTIF7_Msk                   (0x1U << DMA_ISR_HTIF7_Pos)        /*!< 0x04000000 */
2135 #define DMA_ISR_HTIF7                       DMA_ISR_HTIF7_Msk                  /*!< Channel 7 Half Transfer flag */
2136 #define DMA_ISR_TEIF7_Pos                   (27U)
2137 #define DMA_ISR_TEIF7_Msk                   (0x1U << DMA_ISR_TEIF7_Pos)        /*!< 0x08000000 */
2138 #define DMA_ISR_TEIF7                       DMA_ISR_TEIF7_Msk                  /*!< Channel 7 Transfer Error flag */
2139 
2140 /*******************  Bit definition for DMA_IFCR register  *******************/
2141 #define DMA_IFCR_CGIF1_Pos                  (0U)
2142 #define DMA_IFCR_CGIF1_Msk                  (0x1U << DMA_IFCR_CGIF1_Pos)       /*!< 0x00000001 */
2143 #define DMA_IFCR_CGIF1                      DMA_IFCR_CGIF1_Msk                 /*!< Channel 1 Global interrupt clear */
2144 #define DMA_IFCR_CTCIF1_Pos                 (1U)
2145 #define DMA_IFCR_CTCIF1_Msk                 (0x1U << DMA_IFCR_CTCIF1_Pos)      /*!< 0x00000002 */
2146 #define DMA_IFCR_CTCIF1                     DMA_IFCR_CTCIF1_Msk                /*!< Channel 1 Transfer Complete clear */
2147 #define DMA_IFCR_CHTIF1_Pos                 (2U)
2148 #define DMA_IFCR_CHTIF1_Msk                 (0x1U << DMA_IFCR_CHTIF1_Pos)      /*!< 0x00000004 */
2149 #define DMA_IFCR_CHTIF1                     DMA_IFCR_CHTIF1_Msk                /*!< Channel 1 Half Transfer clear */
2150 #define DMA_IFCR_CTEIF1_Pos                 (3U)
2151 #define DMA_IFCR_CTEIF1_Msk                 (0x1U << DMA_IFCR_CTEIF1_Pos)      /*!< 0x00000008 */
2152 #define DMA_IFCR_CTEIF1                     DMA_IFCR_CTEIF1_Msk                /*!< Channel 1 Transfer Error clear */
2153 #define DMA_IFCR_CGIF2_Pos                  (4U)
2154 #define DMA_IFCR_CGIF2_Msk                  (0x1U << DMA_IFCR_CGIF2_Pos)       /*!< 0x00000010 */
2155 #define DMA_IFCR_CGIF2                      DMA_IFCR_CGIF2_Msk                 /*!< Channel 2 Global interrupt clear */
2156 #define DMA_IFCR_CTCIF2_Pos                 (5U)
2157 #define DMA_IFCR_CTCIF2_Msk                 (0x1U << DMA_IFCR_CTCIF2_Pos)      /*!< 0x00000020 */
2158 #define DMA_IFCR_CTCIF2                     DMA_IFCR_CTCIF2_Msk                /*!< Channel 2 Transfer Complete clear */
2159 #define DMA_IFCR_CHTIF2_Pos                 (6U)
2160 #define DMA_IFCR_CHTIF2_Msk                 (0x1U << DMA_IFCR_CHTIF2_Pos)      /*!< 0x00000040 */
2161 #define DMA_IFCR_CHTIF2                     DMA_IFCR_CHTIF2_Msk                /*!< Channel 2 Half Transfer clear */
2162 #define DMA_IFCR_CTEIF2_Pos                 (7U)
2163 #define DMA_IFCR_CTEIF2_Msk                 (0x1U << DMA_IFCR_CTEIF2_Pos)      /*!< 0x00000080 */
2164 #define DMA_IFCR_CTEIF2                     DMA_IFCR_CTEIF2_Msk                /*!< Channel 2 Transfer Error clear */
2165 #define DMA_IFCR_CGIF3_Pos                  (8U)
2166 #define DMA_IFCR_CGIF3_Msk                  (0x1U << DMA_IFCR_CGIF3_Pos)       /*!< 0x00000100 */
2167 #define DMA_IFCR_CGIF3                      DMA_IFCR_CGIF3_Msk                 /*!< Channel 3 Global interrupt clear */
2168 #define DMA_IFCR_CTCIF3_Pos                 (9U)
2169 #define DMA_IFCR_CTCIF3_Msk                 (0x1U << DMA_IFCR_CTCIF3_Pos)      /*!< 0x00000200 */
2170 #define DMA_IFCR_CTCIF3                     DMA_IFCR_CTCIF3_Msk                /*!< Channel 3 Transfer Complete clear */
2171 #define DMA_IFCR_CHTIF3_Pos                 (10U)
2172 #define DMA_IFCR_CHTIF3_Msk                 (0x1U << DMA_IFCR_CHTIF3_Pos)      /*!< 0x00000400 */
2173 #define DMA_IFCR_CHTIF3                     DMA_IFCR_CHTIF3_Msk                /*!< Channel 3 Half Transfer clear */
2174 #define DMA_IFCR_CTEIF3_Pos                 (11U)
2175 #define DMA_IFCR_CTEIF3_Msk                 (0x1U << DMA_IFCR_CTEIF3_Pos)      /*!< 0x00000800 */
2176 #define DMA_IFCR_CTEIF3                     DMA_IFCR_CTEIF3_Msk                /*!< Channel 3 Transfer Error clear */
2177 #define DMA_IFCR_CGIF4_Pos                  (12U)
2178 #define DMA_IFCR_CGIF4_Msk                  (0x1U << DMA_IFCR_CGIF4_Pos)       /*!< 0x00001000 */
2179 #define DMA_IFCR_CGIF4                      DMA_IFCR_CGIF4_Msk                 /*!< Channel 4 Global interrupt clear */
2180 #define DMA_IFCR_CTCIF4_Pos                 (13U)
2181 #define DMA_IFCR_CTCIF4_Msk                 (0x1U << DMA_IFCR_CTCIF4_Pos)      /*!< 0x00002000 */
2182 #define DMA_IFCR_CTCIF4                     DMA_IFCR_CTCIF4_Msk                /*!< Channel 4 Transfer Complete clear */
2183 #define DMA_IFCR_CHTIF4_Pos                 (14U)
2184 #define DMA_IFCR_CHTIF4_Msk                 (0x1U << DMA_IFCR_CHTIF4_Pos)      /*!< 0x00004000 */
2185 #define DMA_IFCR_CHTIF4                     DMA_IFCR_CHTIF4_Msk                /*!< Channel 4 Half Transfer clear */
2186 #define DMA_IFCR_CTEIF4_Pos                 (15U)
2187 #define DMA_IFCR_CTEIF4_Msk                 (0x1U << DMA_IFCR_CTEIF4_Pos)      /*!< 0x00008000 */
2188 #define DMA_IFCR_CTEIF4                     DMA_IFCR_CTEIF4_Msk                /*!< Channel 4 Transfer Error clear */
2189 #define DMA_IFCR_CGIF5_Pos                  (16U)
2190 #define DMA_IFCR_CGIF5_Msk                  (0x1U << DMA_IFCR_CGIF5_Pos)       /*!< 0x00010000 */
2191 #define DMA_IFCR_CGIF5                      DMA_IFCR_CGIF5_Msk                 /*!< Channel 5 Global interrupt clear */
2192 #define DMA_IFCR_CTCIF5_Pos                 (17U)
2193 #define DMA_IFCR_CTCIF5_Msk                 (0x1U << DMA_IFCR_CTCIF5_Pos)      /*!< 0x00020000 */
2194 #define DMA_IFCR_CTCIF5                     DMA_IFCR_CTCIF5_Msk                /*!< Channel 5 Transfer Complete clear */
2195 #define DMA_IFCR_CHTIF5_Pos                 (18U)
2196 #define DMA_IFCR_CHTIF5_Msk                 (0x1U << DMA_IFCR_CHTIF5_Pos)      /*!< 0x00040000 */
2197 #define DMA_IFCR_CHTIF5                     DMA_IFCR_CHTIF5_Msk                /*!< Channel 5 Half Transfer clear */
2198 #define DMA_IFCR_CTEIF5_Pos                 (19U)
2199 #define DMA_IFCR_CTEIF5_Msk                 (0x1U << DMA_IFCR_CTEIF5_Pos)      /*!< 0x00080000 */
2200 #define DMA_IFCR_CTEIF5                     DMA_IFCR_CTEIF5_Msk                /*!< Channel 5 Transfer Error clear */
2201 #define DMA_IFCR_CGIF6_Pos                  (20U)
2202 #define DMA_IFCR_CGIF6_Msk                  (0x1U << DMA_IFCR_CGIF6_Pos)       /*!< 0x00100000 */
2203 #define DMA_IFCR_CGIF6                      DMA_IFCR_CGIF6_Msk                 /*!< Channel 6 Global interrupt clear */
2204 #define DMA_IFCR_CTCIF6_Pos                 (21U)
2205 #define DMA_IFCR_CTCIF6_Msk                 (0x1U << DMA_IFCR_CTCIF6_Pos)      /*!< 0x00200000 */
2206 #define DMA_IFCR_CTCIF6                     DMA_IFCR_CTCIF6_Msk                /*!< Channel 6 Transfer Complete clear */
2207 #define DMA_IFCR_CHTIF6_Pos                 (22U)
2208 #define DMA_IFCR_CHTIF6_Msk                 (0x1U << DMA_IFCR_CHTIF6_Pos)      /*!< 0x00400000 */
2209 #define DMA_IFCR_CHTIF6                     DMA_IFCR_CHTIF6_Msk                /*!< Channel 6 Half Transfer clear */
2210 #define DMA_IFCR_CTEIF6_Pos                 (23U)
2211 #define DMA_IFCR_CTEIF6_Msk                 (0x1U << DMA_IFCR_CTEIF6_Pos)      /*!< 0x00800000 */
2212 #define DMA_IFCR_CTEIF6                     DMA_IFCR_CTEIF6_Msk                /*!< Channel 6 Transfer Error clear */
2213 #define DMA_IFCR_CGIF7_Pos                  (24U)
2214 #define DMA_IFCR_CGIF7_Msk                  (0x1U << DMA_IFCR_CGIF7_Pos)       /*!< 0x01000000 */
2215 #define DMA_IFCR_CGIF7                      DMA_IFCR_CGIF7_Msk                 /*!< Channel 7 Global interrupt clear */
2216 #define DMA_IFCR_CTCIF7_Pos                 (25U)
2217 #define DMA_IFCR_CTCIF7_Msk                 (0x1U << DMA_IFCR_CTCIF7_Pos)      /*!< 0x02000000 */
2218 #define DMA_IFCR_CTCIF7                     DMA_IFCR_CTCIF7_Msk                /*!< Channel 7 Transfer Complete clear */
2219 #define DMA_IFCR_CHTIF7_Pos                 (26U)
2220 #define DMA_IFCR_CHTIF7_Msk                 (0x1U << DMA_IFCR_CHTIF7_Pos)      /*!< 0x04000000 */
2221 #define DMA_IFCR_CHTIF7                     DMA_IFCR_CHTIF7_Msk                /*!< Channel 7 Half Transfer clear */
2222 #define DMA_IFCR_CTEIF7_Pos                 (27U)
2223 #define DMA_IFCR_CTEIF7_Msk                 (0x1U << DMA_IFCR_CTEIF7_Pos)      /*!< 0x08000000 */
2224 #define DMA_IFCR_CTEIF7                     DMA_IFCR_CTEIF7_Msk                /*!< Channel 7 Transfer Error clear */
2225 
2226 /*******************  Bit definition for DMA_CCR register  *******************/
2227 #define DMA_CCR_EN_Pos                      (0U)
2228 #define DMA_CCR_EN_Msk                      (0x1U << DMA_CCR_EN_Pos)           /*!< 0x00000001 */
2229 #define DMA_CCR_EN                          DMA_CCR_EN_Msk                     /*!< Channel enable*/
2230 #define DMA_CCR_TCIE_Pos                    (1U)
2231 #define DMA_CCR_TCIE_Msk                    (0x1U << DMA_CCR_TCIE_Pos)         /*!< 0x00000002 */
2232 #define DMA_CCR_TCIE                        DMA_CCR_TCIE_Msk                   /*!< Transfer complete interrupt enable */
2233 #define DMA_CCR_HTIE_Pos                    (2U)
2234 #define DMA_CCR_HTIE_Msk                    (0x1U << DMA_CCR_HTIE_Pos)         /*!< 0x00000004 */
2235 #define DMA_CCR_HTIE                        DMA_CCR_HTIE_Msk                   /*!< Half Transfer interrupt enable */
2236 #define DMA_CCR_TEIE_Pos                    (3U)
2237 #define DMA_CCR_TEIE_Msk                    (0x1U << DMA_CCR_TEIE_Pos)         /*!< 0x00000008 */
2238 #define DMA_CCR_TEIE                        DMA_CCR_TEIE_Msk                   /*!< Transfer error interrupt enable */
2239 #define DMA_CCR_DIR_Pos                     (4U)
2240 #define DMA_CCR_DIR_Msk                     (0x1U << DMA_CCR_DIR_Pos)          /*!< 0x00000010 */
2241 #define DMA_CCR_DIR                         DMA_CCR_DIR_Msk                    /*!< Data transfer direction */
2242 #define DMA_CCR_CIRC_Pos                    (5U)
2243 #define DMA_CCR_CIRC_Msk                    (0x1U << DMA_CCR_CIRC_Pos)         /*!< 0x00000020 */
2244 #define DMA_CCR_CIRC                        DMA_CCR_CIRC_Msk                   /*!< Circular mode */
2245 #define DMA_CCR_PINC_Pos                    (6U)
2246 #define DMA_CCR_PINC_Msk                    (0x1U << DMA_CCR_PINC_Pos)         /*!< 0x00000040 */
2247 #define DMA_CCR_PINC                        DMA_CCR_PINC_Msk                   /*!< Peripheral increment mode */
2248 #define DMA_CCR_MINC_Pos                    (7U)
2249 #define DMA_CCR_MINC_Msk                    (0x1U << DMA_CCR_MINC_Pos)         /*!< 0x00000080 */
2250 #define DMA_CCR_MINC                        DMA_CCR_MINC_Msk                   /*!< Memory increment mode */
2251 
2252 #define DMA_CCR_PSIZE_Pos                   (8U)
2253 #define DMA_CCR_PSIZE_Msk                   (0x3U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000300 */
2254 #define DMA_CCR_PSIZE                       DMA_CCR_PSIZE_Msk                  /*!< PSIZE[1:0] bits (Peripheral size) */
2255 #define DMA_CCR_PSIZE_0                     (0x1U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000100 */
2256 #define DMA_CCR_PSIZE_1                     (0x2U << DMA_CCR_PSIZE_Pos)        /*!< 0x00000200 */
2257 
2258 #define DMA_CCR_MSIZE_Pos                   (10U)
2259 #define DMA_CCR_MSIZE_Msk                   (0x3U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000C00 */
2260 #define DMA_CCR_MSIZE                       DMA_CCR_MSIZE_Msk                  /*!< MSIZE[1:0] bits (Memory size) */
2261 #define DMA_CCR_MSIZE_0                     (0x1U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000400 */
2262 #define DMA_CCR_MSIZE_1                     (0x2U << DMA_CCR_MSIZE_Pos)        /*!< 0x00000800 */
2263 
2264 #define DMA_CCR_PL_Pos                      (12U)
2265 #define DMA_CCR_PL_Msk                      (0x3U << DMA_CCR_PL_Pos)           /*!< 0x00003000 */
2266 #define DMA_CCR_PL                          DMA_CCR_PL_Msk                     /*!< PL[1:0] bits(Channel Priority level) */
2267 #define DMA_CCR_PL_0                        (0x1U << DMA_CCR_PL_Pos)           /*!< 0x00001000 */
2268 #define DMA_CCR_PL_1                        (0x2U << DMA_CCR_PL_Pos)           /*!< 0x00002000 */
2269 
2270 #define DMA_CCR_MEM2MEM_Pos                 (14U)
2271 #define DMA_CCR_MEM2MEM_Msk                 (0x1U << DMA_CCR_MEM2MEM_Pos)      /*!< 0x00004000 */
2272 #define DMA_CCR_MEM2MEM                     DMA_CCR_MEM2MEM_Msk                /*!< Memory to memory mode */
2273 
2274 /******************  Bit definition generic for DMA_CNDTR register  *******************/
2275 #define DMA_CNDTR_NDT_Pos                   (0U)
2276 #define DMA_CNDTR_NDT_Msk                   (0xFFFFU << DMA_CNDTR_NDT_Pos)     /*!< 0x0000FFFF */
2277 #define DMA_CNDTR_NDT                       DMA_CNDTR_NDT_Msk                  /*!< Number of data to Transfer */
2278 
2279 /******************  Bit definition for DMA_CNDTR1 register  ******************/
2280 #define DMA_CNDTR1_NDT_Pos                  (0U)
2281 #define DMA_CNDTR1_NDT_Msk                  (0xFFFFU << DMA_CNDTR1_NDT_Pos)    /*!< 0x0000FFFF */
2282 #define DMA_CNDTR1_NDT                      DMA_CNDTR1_NDT_Msk                 /*!< Number of data to Transfer */
2283 
2284 /******************  Bit definition for DMA_CNDTR2 register  ******************/
2285 #define DMA_CNDTR2_NDT_Pos                  (0U)
2286 #define DMA_CNDTR2_NDT_Msk                  (0xFFFFU << DMA_CNDTR2_NDT_Pos)    /*!< 0x0000FFFF */
2287 #define DMA_CNDTR2_NDT                      DMA_CNDTR2_NDT_Msk                 /*!< Number of data to Transfer */
2288 
2289 /******************  Bit definition for DMA_CNDTR3 register  ******************/
2290 #define DMA_CNDTR3_NDT_Pos                  (0U)
2291 #define DMA_CNDTR3_NDT_Msk                  (0xFFFFU << DMA_CNDTR3_NDT_Pos)    /*!< 0x0000FFFF */
2292 #define DMA_CNDTR3_NDT                      DMA_CNDTR3_NDT_Msk                 /*!< Number of data to Transfer */
2293 
2294 /******************  Bit definition for DMA_CNDTR4 register  ******************/
2295 #define DMA_CNDTR4_NDT_Pos                  (0U)
2296 #define DMA_CNDTR4_NDT_Msk                  (0xFFFFU << DMA_CNDTR4_NDT_Pos)    /*!< 0x0000FFFF */
2297 #define DMA_CNDTR4_NDT                      DMA_CNDTR4_NDT_Msk                 /*!< Number of data to Transfer */
2298 
2299 /******************  Bit definition for DMA_CNDTR5 register  ******************/
2300 #define DMA_CNDTR5_NDT_Pos                  (0U)
2301 #define DMA_CNDTR5_NDT_Msk                  (0xFFFFU << DMA_CNDTR5_NDT_Pos)    /*!< 0x0000FFFF */
2302 #define DMA_CNDTR5_NDT                      DMA_CNDTR5_NDT_Msk                 /*!< Number of data to Transfer */
2303 
2304 /******************  Bit definition for DMA_CNDTR6 register  ******************/
2305 #define DMA_CNDTR6_NDT_Pos                  (0U)
2306 #define DMA_CNDTR6_NDT_Msk                  (0xFFFFU << DMA_CNDTR6_NDT_Pos)    /*!< 0x0000FFFF */
2307 #define DMA_CNDTR6_NDT                      DMA_CNDTR6_NDT_Msk                 /*!< Number of data to Transfer */
2308 
2309 /******************  Bit definition for DMA_CNDTR7 register  ******************/
2310 #define DMA_CNDTR7_NDT_Pos                  (0U)
2311 #define DMA_CNDTR7_NDT_Msk                  (0xFFFFU << DMA_CNDTR7_NDT_Pos)    /*!< 0x0000FFFF */
2312 #define DMA_CNDTR7_NDT                      DMA_CNDTR7_NDT_Msk                 /*!< Number of data to Transfer */
2313 
2314 /******************  Bit definition generic for DMA_CPAR register  ********************/
2315 #define DMA_CPAR_PA_Pos                     (0U)
2316 #define DMA_CPAR_PA_Msk                     (0xFFFFFFFFU << DMA_CPAR_PA_Pos)   /*!< 0xFFFFFFFF */
2317 #define DMA_CPAR_PA                         DMA_CPAR_PA_Msk                    /*!< Peripheral Address */
2318 
2319 /******************  Bit definition for DMA_CPAR1 register  *******************/
2320 #define DMA_CPAR1_PA_Pos                    (0U)
2321 #define DMA_CPAR1_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR1_PA_Pos)  /*!< 0xFFFFFFFF */
2322 #define DMA_CPAR1_PA                        DMA_CPAR1_PA_Msk                   /*!< Peripheral Address */
2323 
2324 /******************  Bit definition for DMA_CPAR2 register  *******************/
2325 #define DMA_CPAR2_PA_Pos                    (0U)
2326 #define DMA_CPAR2_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR2_PA_Pos)  /*!< 0xFFFFFFFF */
2327 #define DMA_CPAR2_PA                        DMA_CPAR2_PA_Msk                   /*!< Peripheral Address */
2328 
2329 /******************  Bit definition for DMA_CPAR3 register  *******************/
2330 #define DMA_CPAR3_PA_Pos                    (0U)
2331 #define DMA_CPAR3_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR3_PA_Pos)  /*!< 0xFFFFFFFF */
2332 #define DMA_CPAR3_PA                        DMA_CPAR3_PA_Msk                   /*!< Peripheral Address */
2333 
2334 
2335 /******************  Bit definition for DMA_CPAR4 register  *******************/
2336 #define DMA_CPAR4_PA_Pos                    (0U)
2337 #define DMA_CPAR4_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR4_PA_Pos)  /*!< 0xFFFFFFFF */
2338 #define DMA_CPAR4_PA                        DMA_CPAR4_PA_Msk                   /*!< Peripheral Address */
2339 
2340 /******************  Bit definition for DMA_CPAR5 register  *******************/
2341 #define DMA_CPAR5_PA_Pos                    (0U)
2342 #define DMA_CPAR5_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR5_PA_Pos)  /*!< 0xFFFFFFFF */
2343 #define DMA_CPAR5_PA                        DMA_CPAR5_PA_Msk                   /*!< Peripheral Address */
2344 
2345 /******************  Bit definition for DMA_CPAR6 register  *******************/
2346 #define DMA_CPAR6_PA_Pos                    (0U)
2347 #define DMA_CPAR6_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR6_PA_Pos)  /*!< 0xFFFFFFFF */
2348 #define DMA_CPAR6_PA                        DMA_CPAR6_PA_Msk                   /*!< Peripheral Address */
2349 
2350 
2351 /******************  Bit definition for DMA_CPAR7 register  *******************/
2352 #define DMA_CPAR7_PA_Pos                    (0U)
2353 #define DMA_CPAR7_PA_Msk                    (0xFFFFFFFFU << DMA_CPAR7_PA_Pos)  /*!< 0xFFFFFFFF */
2354 #define DMA_CPAR7_PA                        DMA_CPAR7_PA_Msk                   /*!< Peripheral Address */
2355 
2356 /******************  Bit definition generic for DMA_CMAR register  ********************/
2357 #define DMA_CMAR_MA_Pos                     (0U)
2358 #define DMA_CMAR_MA_Msk                     (0xFFFFFFFFU << DMA_CMAR_MA_Pos)   /*!< 0xFFFFFFFF */
2359 #define DMA_CMAR_MA                         DMA_CMAR_MA_Msk                    /*!< Memory Address */
2360 
2361 /******************  Bit definition for DMA_CMAR1 register  *******************/
2362 #define DMA_CMAR1_MA_Pos                    (0U)
2363 #define DMA_CMAR1_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR1_MA_Pos)  /*!< 0xFFFFFFFF */
2364 #define DMA_CMAR1_MA                        DMA_CMAR1_MA_Msk                   /*!< Memory Address */
2365 
2366 /******************  Bit definition for DMA_CMAR2 register  *******************/
2367 #define DMA_CMAR2_MA_Pos                    (0U)
2368 #define DMA_CMAR2_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR2_MA_Pos)  /*!< 0xFFFFFFFF */
2369 #define DMA_CMAR2_MA                        DMA_CMAR2_MA_Msk                   /*!< Memory Address */
2370 
2371 /******************  Bit definition for DMA_CMAR3 register  *******************/
2372 #define DMA_CMAR3_MA_Pos                    (0U)
2373 #define DMA_CMAR3_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR3_MA_Pos)  /*!< 0xFFFFFFFF */
2374 #define DMA_CMAR3_MA                        DMA_CMAR3_MA_Msk                   /*!< Memory Address */
2375 
2376 
2377 /******************  Bit definition for DMA_CMAR4 register  *******************/
2378 #define DMA_CMAR4_MA_Pos                    (0U)
2379 #define DMA_CMAR4_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR4_MA_Pos)  /*!< 0xFFFFFFFF */
2380 #define DMA_CMAR4_MA                        DMA_CMAR4_MA_Msk                   /*!< Memory Address */
2381 
2382 /******************  Bit definition for DMA_CMAR5 register  *******************/
2383 #define DMA_CMAR5_MA_Pos                    (0U)
2384 #define DMA_CMAR5_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR5_MA_Pos)  /*!< 0xFFFFFFFF */
2385 #define DMA_CMAR5_MA                        DMA_CMAR5_MA_Msk                   /*!< Memory Address */
2386 
2387 /******************  Bit definition for DMA_CMAR6 register  *******************/
2388 #define DMA_CMAR6_MA_Pos                    (0U)
2389 #define DMA_CMAR6_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR6_MA_Pos)  /*!< 0xFFFFFFFF */
2390 #define DMA_CMAR6_MA                        DMA_CMAR6_MA_Msk                   /*!< Memory Address */
2391 
2392 /******************  Bit definition for DMA_CMAR7 register  *******************/
2393 #define DMA_CMAR7_MA_Pos                    (0U)
2394 #define DMA_CMAR7_MA_Msk                    (0xFFFFFFFFU << DMA_CMAR7_MA_Pos)  /*!< 0xFFFFFFFF */
2395 #define DMA_CMAR7_MA                        DMA_CMAR7_MA_Msk                   /*!< Memory Address */
2396 
2397 /******************************************************************************/
2398 /*                                                                            */
2399 /*                  External Interrupt/Event Controller (EXTI)                */
2400 /*                                                                            */
2401 /******************************************************************************/
2402 
2403 /*******************  Bit definition for EXTI_IMR register  *******************/
2404 #define EXTI_IMR_MR0_Pos                    (0U)
2405 #define EXTI_IMR_MR0_Msk                    (0x1U << EXTI_IMR_MR0_Pos)         /*!< 0x00000001 */
2406 #define EXTI_IMR_MR0                        EXTI_IMR_MR0_Msk                   /*!< Interrupt Mask on line 0 */
2407 #define EXTI_IMR_MR1_Pos                    (1U)
2408 #define EXTI_IMR_MR1_Msk                    (0x1U << EXTI_IMR_MR1_Pos)         /*!< 0x00000002 */
2409 #define EXTI_IMR_MR1                        EXTI_IMR_MR1_Msk                   /*!< Interrupt Mask on line 1 */
2410 #define EXTI_IMR_MR2_Pos                    (2U)
2411 #define EXTI_IMR_MR2_Msk                    (0x1U << EXTI_IMR_MR2_Pos)         /*!< 0x00000004 */
2412 #define EXTI_IMR_MR2                        EXTI_IMR_MR2_Msk                   /*!< Interrupt Mask on line 2 */
2413 #define EXTI_IMR_MR3_Pos                    (3U)
2414 #define EXTI_IMR_MR3_Msk                    (0x1U << EXTI_IMR_MR3_Pos)         /*!< 0x00000008 */
2415 #define EXTI_IMR_MR3                        EXTI_IMR_MR3_Msk                   /*!< Interrupt Mask on line 3 */
2416 #define EXTI_IMR_MR4_Pos                    (4U)
2417 #define EXTI_IMR_MR4_Msk                    (0x1U << EXTI_IMR_MR4_Pos)         /*!< 0x00000010 */
2418 #define EXTI_IMR_MR4                        EXTI_IMR_MR4_Msk                   /*!< Interrupt Mask on line 4 */
2419 #define EXTI_IMR_MR5_Pos                    (5U)
2420 #define EXTI_IMR_MR5_Msk                    (0x1U << EXTI_IMR_MR5_Pos)         /*!< 0x00000020 */
2421 #define EXTI_IMR_MR5                        EXTI_IMR_MR5_Msk                   /*!< Interrupt Mask on line 5 */
2422 #define EXTI_IMR_MR6_Pos                    (6U)
2423 #define EXTI_IMR_MR6_Msk                    (0x1U << EXTI_IMR_MR6_Pos)         /*!< 0x00000040 */
2424 #define EXTI_IMR_MR6                        EXTI_IMR_MR6_Msk                   /*!< Interrupt Mask on line 6 */
2425 #define EXTI_IMR_MR7_Pos                    (7U)
2426 #define EXTI_IMR_MR7_Msk                    (0x1U << EXTI_IMR_MR7_Pos)         /*!< 0x00000080 */
2427 #define EXTI_IMR_MR7                        EXTI_IMR_MR7_Msk                   /*!< Interrupt Mask on line 7 */
2428 #define EXTI_IMR_MR8_Pos                    (8U)
2429 #define EXTI_IMR_MR8_Msk                    (0x1U << EXTI_IMR_MR8_Pos)         /*!< 0x00000100 */
2430 #define EXTI_IMR_MR8                        EXTI_IMR_MR8_Msk                   /*!< Interrupt Mask on line 8 */
2431 #define EXTI_IMR_MR9_Pos                    (9U)
2432 #define EXTI_IMR_MR9_Msk                    (0x1U << EXTI_IMR_MR9_Pos)         /*!< 0x00000200 */
2433 #define EXTI_IMR_MR9                        EXTI_IMR_MR9_Msk                   /*!< Interrupt Mask on line 9 */
2434 #define EXTI_IMR_MR10_Pos                   (10U)
2435 #define EXTI_IMR_MR10_Msk                   (0x1U << EXTI_IMR_MR10_Pos)        /*!< 0x00000400 */
2436 #define EXTI_IMR_MR10                       EXTI_IMR_MR10_Msk                  /*!< Interrupt Mask on line 10 */
2437 #define EXTI_IMR_MR11_Pos                   (11U)
2438 #define EXTI_IMR_MR11_Msk                   (0x1U << EXTI_IMR_MR11_Pos)        /*!< 0x00000800 */
2439 #define EXTI_IMR_MR11                       EXTI_IMR_MR11_Msk                  /*!< Interrupt Mask on line 11 */
2440 #define EXTI_IMR_MR12_Pos                   (12U)
2441 #define EXTI_IMR_MR12_Msk                   (0x1U << EXTI_IMR_MR12_Pos)        /*!< 0x00001000 */
2442 #define EXTI_IMR_MR12                       EXTI_IMR_MR12_Msk                  /*!< Interrupt Mask on line 12 */
2443 #define EXTI_IMR_MR13_Pos                   (13U)
2444 #define EXTI_IMR_MR13_Msk                   (0x1U << EXTI_IMR_MR13_Pos)        /*!< 0x00002000 */
2445 #define EXTI_IMR_MR13                       EXTI_IMR_MR13_Msk                  /*!< Interrupt Mask on line 13 */
2446 #define EXTI_IMR_MR14_Pos                   (14U)
2447 #define EXTI_IMR_MR14_Msk                   (0x1U << EXTI_IMR_MR14_Pos)        /*!< 0x00004000 */
2448 #define EXTI_IMR_MR14                       EXTI_IMR_MR14_Msk                  /*!< Interrupt Mask on line 14 */
2449 #define EXTI_IMR_MR15_Pos                   (15U)
2450 #define EXTI_IMR_MR15_Msk                   (0x1U << EXTI_IMR_MR15_Pos)        /*!< 0x00008000 */
2451 #define EXTI_IMR_MR15                       EXTI_IMR_MR15_Msk                  /*!< Interrupt Mask on line 15 */
2452 #define EXTI_IMR_MR16_Pos                   (16U)
2453 #define EXTI_IMR_MR16_Msk                   (0x1U << EXTI_IMR_MR16_Pos)        /*!< 0x00010000 */
2454 #define EXTI_IMR_MR16                       EXTI_IMR_MR16_Msk                  /*!< Interrupt Mask on line 16 */
2455 #define EXTI_IMR_MR17_Pos                   (17U)
2456 #define EXTI_IMR_MR17_Msk                   (0x1U << EXTI_IMR_MR17_Pos)        /*!< 0x00020000 */
2457 #define EXTI_IMR_MR17                       EXTI_IMR_MR17_Msk                  /*!< Interrupt Mask on line 17 */
2458 #define EXTI_IMR_MR18_Pos                   (18U)
2459 #define EXTI_IMR_MR18_Msk                   (0x1U << EXTI_IMR_MR18_Pos)        /*!< 0x00040000 */
2460 #define EXTI_IMR_MR18                       EXTI_IMR_MR18_Msk                  /*!< Interrupt Mask on line 18 */
2461 #define EXTI_IMR_MR19_Pos                   (19U)
2462 #define EXTI_IMR_MR19_Msk                   (0x1U << EXTI_IMR_MR19_Pos)        /*!< 0x00080000 */
2463 #define EXTI_IMR_MR19                       EXTI_IMR_MR19_Msk                  /*!< Interrupt Mask on line 19 */
2464 #define EXTI_IMR_MR20_Pos                   (20U)
2465 #define EXTI_IMR_MR20_Msk                   (0x1U << EXTI_IMR_MR20_Pos)        /*!< 0x00100000 */
2466 #define EXTI_IMR_MR20                       EXTI_IMR_MR20_Msk                  /*!< Interrupt Mask on line 20 */
2467 #define EXTI_IMR_MR21_Pos                   (21U)
2468 #define EXTI_IMR_MR21_Msk                   (0x1U << EXTI_IMR_MR21_Pos)        /*!< 0x00200000 */
2469 #define EXTI_IMR_MR21                       EXTI_IMR_MR21_Msk                  /*!< Interrupt Mask on line 21 */
2470 #define EXTI_IMR_MR22_Pos                   (22U)
2471 #define EXTI_IMR_MR22_Msk                   (0x1U << EXTI_IMR_MR22_Pos)        /*!< 0x00400000 */
2472 #define EXTI_IMR_MR22                       EXTI_IMR_MR22_Msk                  /*!< Interrupt Mask on line 22 */
2473 #define EXTI_IMR_MR23_Pos                   (23U)
2474 #define EXTI_IMR_MR23_Msk                   (0x1U << EXTI_IMR_MR23_Pos)        /*!< 0x00800000 */
2475 #define EXTI_IMR_MR23                       EXTI_IMR_MR23_Msk                  /*!< Interrupt Mask on line 23 */
2476 
2477 /* References Defines */
2478 #define  EXTI_IMR_IM0 EXTI_IMR_MR0
2479 #define  EXTI_IMR_IM1 EXTI_IMR_MR1
2480 #define  EXTI_IMR_IM2 EXTI_IMR_MR2
2481 #define  EXTI_IMR_IM3 EXTI_IMR_MR3
2482 #define  EXTI_IMR_IM4 EXTI_IMR_MR4
2483 #define  EXTI_IMR_IM5 EXTI_IMR_MR5
2484 #define  EXTI_IMR_IM6 EXTI_IMR_MR6
2485 #define  EXTI_IMR_IM7 EXTI_IMR_MR7
2486 #define  EXTI_IMR_IM8 EXTI_IMR_MR8
2487 #define  EXTI_IMR_IM9 EXTI_IMR_MR9
2488 #define  EXTI_IMR_IM10 EXTI_IMR_MR10
2489 #define  EXTI_IMR_IM11 EXTI_IMR_MR11
2490 #define  EXTI_IMR_IM12 EXTI_IMR_MR12
2491 #define  EXTI_IMR_IM13 EXTI_IMR_MR13
2492 #define  EXTI_IMR_IM14 EXTI_IMR_MR14
2493 #define  EXTI_IMR_IM15 EXTI_IMR_MR15
2494 #define  EXTI_IMR_IM16 EXTI_IMR_MR16
2495 #define  EXTI_IMR_IM17 EXTI_IMR_MR17
2496 #define  EXTI_IMR_IM18 EXTI_IMR_MR18
2497 #define  EXTI_IMR_IM19 EXTI_IMR_MR19
2498 #define  EXTI_IMR_IM20 EXTI_IMR_MR20
2499 #define  EXTI_IMR_IM21 EXTI_IMR_MR21
2500 #define  EXTI_IMR_IM22 EXTI_IMR_MR22
2501 /* Category 3, 4 & 5 */
2502 #define  EXTI_IMR_IM23 EXTI_IMR_MR23
2503 #define EXTI_IMR_IM_Pos                     (0U)
2504 #define EXTI_IMR_IM_Msk                     (0xFFFFFFU << EXTI_IMR_IM_Pos)     /*!< 0x00FFFFFF */
2505 #define EXTI_IMR_IM                         EXTI_IMR_IM_Msk                    /*!< Interrupt Mask All */
2506 
2507 /*******************  Bit definition for EXTI_EMR register  *******************/
2508 #define EXTI_EMR_MR0_Pos                    (0U)
2509 #define EXTI_EMR_MR0_Msk                    (0x1U << EXTI_EMR_MR0_Pos)         /*!< 0x00000001 */
2510 #define EXTI_EMR_MR0                        EXTI_EMR_MR0_Msk                   /*!< Event Mask on line 0 */
2511 #define EXTI_EMR_MR1_Pos                    (1U)
2512 #define EXTI_EMR_MR1_Msk                    (0x1U << EXTI_EMR_MR1_Pos)         /*!< 0x00000002 */
2513 #define EXTI_EMR_MR1                        EXTI_EMR_MR1_Msk                   /*!< Event Mask on line 1 */
2514 #define EXTI_EMR_MR2_Pos                    (2U)
2515 #define EXTI_EMR_MR2_Msk                    (0x1U << EXTI_EMR_MR2_Pos)         /*!< 0x00000004 */
2516 #define EXTI_EMR_MR2                        EXTI_EMR_MR2_Msk                   /*!< Event Mask on line 2 */
2517 #define EXTI_EMR_MR3_Pos                    (3U)
2518 #define EXTI_EMR_MR3_Msk                    (0x1U << EXTI_EMR_MR3_Pos)         /*!< 0x00000008 */
2519 #define EXTI_EMR_MR3                        EXTI_EMR_MR3_Msk                   /*!< Event Mask on line 3 */
2520 #define EXTI_EMR_MR4_Pos                    (4U)
2521 #define EXTI_EMR_MR4_Msk                    (0x1U << EXTI_EMR_MR4_Pos)         /*!< 0x00000010 */
2522 #define EXTI_EMR_MR4                        EXTI_EMR_MR4_Msk                   /*!< Event Mask on line 4 */
2523 #define EXTI_EMR_MR5_Pos                    (5U)
2524 #define EXTI_EMR_MR5_Msk                    (0x1U << EXTI_EMR_MR5_Pos)         /*!< 0x00000020 */
2525 #define EXTI_EMR_MR5                        EXTI_EMR_MR5_Msk                   /*!< Event Mask on line 5 */
2526 #define EXTI_EMR_MR6_Pos                    (6U)
2527 #define EXTI_EMR_MR6_Msk                    (0x1U << EXTI_EMR_MR6_Pos)         /*!< 0x00000040 */
2528 #define EXTI_EMR_MR6                        EXTI_EMR_MR6_Msk                   /*!< Event Mask on line 6 */
2529 #define EXTI_EMR_MR7_Pos                    (7U)
2530 #define EXTI_EMR_MR7_Msk                    (0x1U << EXTI_EMR_MR7_Pos)         /*!< 0x00000080 */
2531 #define EXTI_EMR_MR7                        EXTI_EMR_MR7_Msk                   /*!< Event Mask on line 7 */
2532 #define EXTI_EMR_MR8_Pos                    (8U)
2533 #define EXTI_EMR_MR8_Msk                    (0x1U << EXTI_EMR_MR8_Pos)         /*!< 0x00000100 */
2534 #define EXTI_EMR_MR8                        EXTI_EMR_MR8_Msk                   /*!< Event Mask on line 8 */
2535 #define EXTI_EMR_MR9_Pos                    (9U)
2536 #define EXTI_EMR_MR9_Msk                    (0x1U << EXTI_EMR_MR9_Pos)         /*!< 0x00000200 */
2537 #define EXTI_EMR_MR9                        EXTI_EMR_MR9_Msk                   /*!< Event Mask on line 9 */
2538 #define EXTI_EMR_MR10_Pos                   (10U)
2539 #define EXTI_EMR_MR10_Msk                   (0x1U << EXTI_EMR_MR10_Pos)        /*!< 0x00000400 */
2540 #define EXTI_EMR_MR10                       EXTI_EMR_MR10_Msk                  /*!< Event Mask on line 10 */
2541 #define EXTI_EMR_MR11_Pos                   (11U)
2542 #define EXTI_EMR_MR11_Msk                   (0x1U << EXTI_EMR_MR11_Pos)        /*!< 0x00000800 */
2543 #define EXTI_EMR_MR11                       EXTI_EMR_MR11_Msk                  /*!< Event Mask on line 11 */
2544 #define EXTI_EMR_MR12_Pos                   (12U)
2545 #define EXTI_EMR_MR12_Msk                   (0x1U << EXTI_EMR_MR12_Pos)        /*!< 0x00001000 */
2546 #define EXTI_EMR_MR12                       EXTI_EMR_MR12_Msk                  /*!< Event Mask on line 12 */
2547 #define EXTI_EMR_MR13_Pos                   (13U)
2548 #define EXTI_EMR_MR13_Msk                   (0x1U << EXTI_EMR_MR13_Pos)        /*!< 0x00002000 */
2549 #define EXTI_EMR_MR13                       EXTI_EMR_MR13_Msk                  /*!< Event Mask on line 13 */
2550 #define EXTI_EMR_MR14_Pos                   (14U)
2551 #define EXTI_EMR_MR14_Msk                   (0x1U << EXTI_EMR_MR14_Pos)        /*!< 0x00004000 */
2552 #define EXTI_EMR_MR14                       EXTI_EMR_MR14_Msk                  /*!< Event Mask on line 14 */
2553 #define EXTI_EMR_MR15_Pos                   (15U)
2554 #define EXTI_EMR_MR15_Msk                   (0x1U << EXTI_EMR_MR15_Pos)        /*!< 0x00008000 */
2555 #define EXTI_EMR_MR15                       EXTI_EMR_MR15_Msk                  /*!< Event Mask on line 15 */
2556 #define EXTI_EMR_MR16_Pos                   (16U)
2557 #define EXTI_EMR_MR16_Msk                   (0x1U << EXTI_EMR_MR16_Pos)        /*!< 0x00010000 */
2558 #define EXTI_EMR_MR16                       EXTI_EMR_MR16_Msk                  /*!< Event Mask on line 16 */
2559 #define EXTI_EMR_MR17_Pos                   (17U)
2560 #define EXTI_EMR_MR17_Msk                   (0x1U << EXTI_EMR_MR17_Pos)        /*!< 0x00020000 */
2561 #define EXTI_EMR_MR17                       EXTI_EMR_MR17_Msk                  /*!< Event Mask on line 17 */
2562 #define EXTI_EMR_MR18_Pos                   (18U)
2563 #define EXTI_EMR_MR18_Msk                   (0x1U << EXTI_EMR_MR18_Pos)        /*!< 0x00040000 */
2564 #define EXTI_EMR_MR18                       EXTI_EMR_MR18_Msk                  /*!< Event Mask on line 18 */
2565 #define EXTI_EMR_MR19_Pos                   (19U)
2566 #define EXTI_EMR_MR19_Msk                   (0x1U << EXTI_EMR_MR19_Pos)        /*!< 0x00080000 */
2567 #define EXTI_EMR_MR19                       EXTI_EMR_MR19_Msk                  /*!< Event Mask on line 19 */
2568 #define EXTI_EMR_MR20_Pos                   (20U)
2569 #define EXTI_EMR_MR20_Msk                   (0x1U << EXTI_EMR_MR20_Pos)        /*!< 0x00100000 */
2570 #define EXTI_EMR_MR20                       EXTI_EMR_MR20_Msk                  /*!< Event Mask on line 20 */
2571 #define EXTI_EMR_MR21_Pos                   (21U)
2572 #define EXTI_EMR_MR21_Msk                   (0x1U << EXTI_EMR_MR21_Pos)        /*!< 0x00200000 */
2573 #define EXTI_EMR_MR21                       EXTI_EMR_MR21_Msk                  /*!< Event Mask on line 21 */
2574 #define EXTI_EMR_MR22_Pos                   (22U)
2575 #define EXTI_EMR_MR22_Msk                   (0x1U << EXTI_EMR_MR22_Pos)        /*!< 0x00400000 */
2576 #define EXTI_EMR_MR22                       EXTI_EMR_MR22_Msk                  /*!< Event Mask on line 22 */
2577 #define EXTI_EMR_MR23_Pos                   (23U)
2578 #define EXTI_EMR_MR23_Msk                   (0x1U << EXTI_EMR_MR23_Pos)        /*!< 0x00800000 */
2579 #define EXTI_EMR_MR23                       EXTI_EMR_MR23_Msk                  /*!< Event Mask on line 23 */
2580 
2581 /* References Defines */
2582 #define  EXTI_EMR_EM0 EXTI_EMR_MR0
2583 #define  EXTI_EMR_EM1 EXTI_EMR_MR1
2584 #define  EXTI_EMR_EM2 EXTI_EMR_MR2
2585 #define  EXTI_EMR_EM3 EXTI_EMR_MR3
2586 #define  EXTI_EMR_EM4 EXTI_EMR_MR4
2587 #define  EXTI_EMR_EM5 EXTI_EMR_MR5
2588 #define  EXTI_EMR_EM6 EXTI_EMR_MR6
2589 #define  EXTI_EMR_EM7 EXTI_EMR_MR7
2590 #define  EXTI_EMR_EM8 EXTI_EMR_MR8
2591 #define  EXTI_EMR_EM9 EXTI_EMR_MR9
2592 #define  EXTI_EMR_EM10 EXTI_EMR_MR10
2593 #define  EXTI_EMR_EM11 EXTI_EMR_MR11
2594 #define  EXTI_EMR_EM12 EXTI_EMR_MR12
2595 #define  EXTI_EMR_EM13 EXTI_EMR_MR13
2596 #define  EXTI_EMR_EM14 EXTI_EMR_MR14
2597 #define  EXTI_EMR_EM15 EXTI_EMR_MR15
2598 #define  EXTI_EMR_EM16 EXTI_EMR_MR16
2599 #define  EXTI_EMR_EM17 EXTI_EMR_MR17
2600 #define  EXTI_EMR_EM18 EXTI_EMR_MR18
2601 #define  EXTI_EMR_EM19 EXTI_EMR_MR19
2602 #define  EXTI_EMR_EM20 EXTI_EMR_MR20
2603 #define  EXTI_EMR_EM21 EXTI_EMR_MR21
2604 #define  EXTI_EMR_EM22 EXTI_EMR_MR22
2605 #define  EXTI_EMR_EM23 EXTI_EMR_MR23
2606 
2607 /******************  Bit definition for EXTI_RTSR register  *******************/
2608 #define EXTI_RTSR_TR0_Pos                   (0U)
2609 #define EXTI_RTSR_TR0_Msk                   (0x1U << EXTI_RTSR_TR0_Pos)        /*!< 0x00000001 */
2610 #define EXTI_RTSR_TR0                       EXTI_RTSR_TR0_Msk                  /*!< Rising trigger event configuration bit of line 0 */
2611 #define EXTI_RTSR_TR1_Pos                   (1U)
2612 #define EXTI_RTSR_TR1_Msk                   (0x1U << EXTI_RTSR_TR1_Pos)        /*!< 0x00000002 */
2613 #define EXTI_RTSR_TR1                       EXTI_RTSR_TR1_Msk                  /*!< Rising trigger event configuration bit of line 1 */
2614 #define EXTI_RTSR_TR2_Pos                   (2U)
2615 #define EXTI_RTSR_TR2_Msk                   (0x1U << EXTI_RTSR_TR2_Pos)        /*!< 0x00000004 */
2616 #define EXTI_RTSR_TR2                       EXTI_RTSR_TR2_Msk                  /*!< Rising trigger event configuration bit of line 2 */
2617 #define EXTI_RTSR_TR3_Pos                   (3U)
2618 #define EXTI_RTSR_TR3_Msk                   (0x1U << EXTI_RTSR_TR3_Pos)        /*!< 0x00000008 */
2619 #define EXTI_RTSR_TR3                       EXTI_RTSR_TR3_Msk                  /*!< Rising trigger event configuration bit of line 3 */
2620 #define EXTI_RTSR_TR4_Pos                   (4U)
2621 #define EXTI_RTSR_TR4_Msk                   (0x1U << EXTI_RTSR_TR4_Pos)        /*!< 0x00000010 */
2622 #define EXTI_RTSR_TR4                       EXTI_RTSR_TR4_Msk                  /*!< Rising trigger event configuration bit of line 4 */
2623 #define EXTI_RTSR_TR5_Pos                   (5U)
2624 #define EXTI_RTSR_TR5_Msk                   (0x1U << EXTI_RTSR_TR5_Pos)        /*!< 0x00000020 */
2625 #define EXTI_RTSR_TR5                       EXTI_RTSR_TR5_Msk                  /*!< Rising trigger event configuration bit of line 5 */
2626 #define EXTI_RTSR_TR6_Pos                   (6U)
2627 #define EXTI_RTSR_TR6_Msk                   (0x1U << EXTI_RTSR_TR6_Pos)        /*!< 0x00000040 */
2628 #define EXTI_RTSR_TR6                       EXTI_RTSR_TR6_Msk                  /*!< Rising trigger event configuration bit of line 6 */
2629 #define EXTI_RTSR_TR7_Pos                   (7U)
2630 #define EXTI_RTSR_TR7_Msk                   (0x1U << EXTI_RTSR_TR7_Pos)        /*!< 0x00000080 */
2631 #define EXTI_RTSR_TR7                       EXTI_RTSR_TR7_Msk                  /*!< Rising trigger event configuration bit of line 7 */
2632 #define EXTI_RTSR_TR8_Pos                   (8U)
2633 #define EXTI_RTSR_TR8_Msk                   (0x1U << EXTI_RTSR_TR8_Pos)        /*!< 0x00000100 */
2634 #define EXTI_RTSR_TR8                       EXTI_RTSR_TR8_Msk                  /*!< Rising trigger event configuration bit of line 8 */
2635 #define EXTI_RTSR_TR9_Pos                   (9U)
2636 #define EXTI_RTSR_TR9_Msk                   (0x1U << EXTI_RTSR_TR9_Pos)        /*!< 0x00000200 */
2637 #define EXTI_RTSR_TR9                       EXTI_RTSR_TR9_Msk                  /*!< Rising trigger event configuration bit of line 9 */
2638 #define EXTI_RTSR_TR10_Pos                  (10U)
2639 #define EXTI_RTSR_TR10_Msk                  (0x1U << EXTI_RTSR_TR10_Pos)       /*!< 0x00000400 */
2640 #define EXTI_RTSR_TR10                      EXTI_RTSR_TR10_Msk                 /*!< Rising trigger event configuration bit of line 10 */
2641 #define EXTI_RTSR_TR11_Pos                  (11U)
2642 #define EXTI_RTSR_TR11_Msk                  (0x1U << EXTI_RTSR_TR11_Pos)       /*!< 0x00000800 */
2643 #define EXTI_RTSR_TR11                      EXTI_RTSR_TR11_Msk                 /*!< Rising trigger event configuration bit of line 11 */
2644 #define EXTI_RTSR_TR12_Pos                  (12U)
2645 #define EXTI_RTSR_TR12_Msk                  (0x1U << EXTI_RTSR_TR12_Pos)       /*!< 0x00001000 */
2646 #define EXTI_RTSR_TR12                      EXTI_RTSR_TR12_Msk                 /*!< Rising trigger event configuration bit of line 12 */
2647 #define EXTI_RTSR_TR13_Pos                  (13U)
2648 #define EXTI_RTSR_TR13_Msk                  (0x1U << EXTI_RTSR_TR13_Pos)       /*!< 0x00002000 */
2649 #define EXTI_RTSR_TR13                      EXTI_RTSR_TR13_Msk                 /*!< Rising trigger event configuration bit of line 13 */
2650 #define EXTI_RTSR_TR14_Pos                  (14U)
2651 #define EXTI_RTSR_TR14_Msk                  (0x1U << EXTI_RTSR_TR14_Pos)       /*!< 0x00004000 */
2652 #define EXTI_RTSR_TR14                      EXTI_RTSR_TR14_Msk                 /*!< Rising trigger event configuration bit of line 14 */
2653 #define EXTI_RTSR_TR15_Pos                  (15U)
2654 #define EXTI_RTSR_TR15_Msk                  (0x1U << EXTI_RTSR_TR15_Pos)       /*!< 0x00008000 */
2655 #define EXTI_RTSR_TR15                      EXTI_RTSR_TR15_Msk                 /*!< Rising trigger event configuration bit of line 15 */
2656 #define EXTI_RTSR_TR16_Pos                  (16U)
2657 #define EXTI_RTSR_TR16_Msk                  (0x1U << EXTI_RTSR_TR16_Pos)       /*!< 0x00010000 */
2658 #define EXTI_RTSR_TR16                      EXTI_RTSR_TR16_Msk                 /*!< Rising trigger event configuration bit of line 16 */
2659 #define EXTI_RTSR_TR17_Pos                  (17U)
2660 #define EXTI_RTSR_TR17_Msk                  (0x1U << EXTI_RTSR_TR17_Pos)       /*!< 0x00020000 */
2661 #define EXTI_RTSR_TR17                      EXTI_RTSR_TR17_Msk                 /*!< Rising trigger event configuration bit of line 17 */
2662 #define EXTI_RTSR_TR18_Pos                  (18U)
2663 #define EXTI_RTSR_TR18_Msk                  (0x1U << EXTI_RTSR_TR18_Pos)       /*!< 0x00040000 */
2664 #define EXTI_RTSR_TR18                      EXTI_RTSR_TR18_Msk                 /*!< Rising trigger event configuration bit of line 18 */
2665 #define EXTI_RTSR_TR19_Pos                  (19U)
2666 #define EXTI_RTSR_TR19_Msk                  (0x1U << EXTI_RTSR_TR19_Pos)       /*!< 0x00080000 */
2667 #define EXTI_RTSR_TR19                      EXTI_RTSR_TR19_Msk                 /*!< Rising trigger event configuration bit of line 19 */
2668 #define EXTI_RTSR_TR20_Pos                  (20U)
2669 #define EXTI_RTSR_TR20_Msk                  (0x1U << EXTI_RTSR_TR20_Pos)       /*!< 0x00100000 */
2670 #define EXTI_RTSR_TR20                      EXTI_RTSR_TR20_Msk                 /*!< Rising trigger event configuration bit of line 20 */
2671 #define EXTI_RTSR_TR21_Pos                  (21U)
2672 #define EXTI_RTSR_TR21_Msk                  (0x1U << EXTI_RTSR_TR21_Pos)       /*!< 0x00200000 */
2673 #define EXTI_RTSR_TR21                      EXTI_RTSR_TR21_Msk                 /*!< Rising trigger event configuration bit of line 21 */
2674 #define EXTI_RTSR_TR22_Pos                  (22U)
2675 #define EXTI_RTSR_TR22_Msk                  (0x1U << EXTI_RTSR_TR22_Pos)       /*!< 0x00400000 */
2676 #define EXTI_RTSR_TR22                      EXTI_RTSR_TR22_Msk                 /*!< Rising trigger event configuration bit of line 22 */
2677 #define EXTI_RTSR_TR23_Pos                  (23U)
2678 #define EXTI_RTSR_TR23_Msk                  (0x1U << EXTI_RTSR_TR23_Pos)       /*!< 0x00800000 */
2679 #define EXTI_RTSR_TR23                      EXTI_RTSR_TR23_Msk                 /*!< Rising trigger event configuration bit of line 23 */
2680 
2681 /* References Defines */
2682 #define  EXTI_RTSR_RT0 EXTI_RTSR_TR0
2683 #define  EXTI_RTSR_RT1 EXTI_RTSR_TR1
2684 #define  EXTI_RTSR_RT2 EXTI_RTSR_TR2
2685 #define  EXTI_RTSR_RT3 EXTI_RTSR_TR3
2686 #define  EXTI_RTSR_RT4 EXTI_RTSR_TR4
2687 #define  EXTI_RTSR_RT5 EXTI_RTSR_TR5
2688 #define  EXTI_RTSR_RT6 EXTI_RTSR_TR6
2689 #define  EXTI_RTSR_RT7 EXTI_RTSR_TR7
2690 #define  EXTI_RTSR_RT8 EXTI_RTSR_TR8
2691 #define  EXTI_RTSR_RT9 EXTI_RTSR_TR9
2692 #define  EXTI_RTSR_RT10 EXTI_RTSR_TR10
2693 #define  EXTI_RTSR_RT11 EXTI_RTSR_TR11
2694 #define  EXTI_RTSR_RT12 EXTI_RTSR_TR12
2695 #define  EXTI_RTSR_RT13 EXTI_RTSR_TR13
2696 #define  EXTI_RTSR_RT14 EXTI_RTSR_TR14
2697 #define  EXTI_RTSR_RT15 EXTI_RTSR_TR15
2698 #define  EXTI_RTSR_RT16 EXTI_RTSR_TR16
2699 #define  EXTI_RTSR_RT17 EXTI_RTSR_TR17
2700 #define  EXTI_RTSR_RT18 EXTI_RTSR_TR18
2701 #define  EXTI_RTSR_RT19 EXTI_RTSR_TR19
2702 #define  EXTI_RTSR_RT20 EXTI_RTSR_TR20
2703 #define  EXTI_RTSR_RT21 EXTI_RTSR_TR21
2704 #define  EXTI_RTSR_RT22 EXTI_RTSR_TR22
2705 #define  EXTI_RTSR_RT23 EXTI_RTSR_TR23
2706 
2707 /******************  Bit definition for EXTI_FTSR register  *******************/
2708 #define EXTI_FTSR_TR0_Pos                   (0U)
2709 #define EXTI_FTSR_TR0_Msk                   (0x1U << EXTI_FTSR_TR0_Pos)        /*!< 0x00000001 */
2710 #define EXTI_FTSR_TR0                       EXTI_FTSR_TR0_Msk                  /*!< Falling trigger event configuration bit of line 0 */
2711 #define EXTI_FTSR_TR1_Pos                   (1U)
2712 #define EXTI_FTSR_TR1_Msk                   (0x1U << EXTI_FTSR_TR1_Pos)        /*!< 0x00000002 */
2713 #define EXTI_FTSR_TR1                       EXTI_FTSR_TR1_Msk                  /*!< Falling trigger event configuration bit of line 1 */
2714 #define EXTI_FTSR_TR2_Pos                   (2U)
2715 #define EXTI_FTSR_TR2_Msk                   (0x1U << EXTI_FTSR_TR2_Pos)        /*!< 0x00000004 */
2716 #define EXTI_FTSR_TR2                       EXTI_FTSR_TR2_Msk                  /*!< Falling trigger event configuration bit of line 2 */
2717 #define EXTI_FTSR_TR3_Pos                   (3U)
2718 #define EXTI_FTSR_TR3_Msk                   (0x1U << EXTI_FTSR_TR3_Pos)        /*!< 0x00000008 */
2719 #define EXTI_FTSR_TR3                       EXTI_FTSR_TR3_Msk                  /*!< Falling trigger event configuration bit of line 3 */
2720 #define EXTI_FTSR_TR4_Pos                   (4U)
2721 #define EXTI_FTSR_TR4_Msk                   (0x1U << EXTI_FTSR_TR4_Pos)        /*!< 0x00000010 */
2722 #define EXTI_FTSR_TR4                       EXTI_FTSR_TR4_Msk                  /*!< Falling trigger event configuration bit of line 4 */
2723 #define EXTI_FTSR_TR5_Pos                   (5U)
2724 #define EXTI_FTSR_TR5_Msk                   (0x1U << EXTI_FTSR_TR5_Pos)        /*!< 0x00000020 */
2725 #define EXTI_FTSR_TR5                       EXTI_FTSR_TR5_Msk                  /*!< Falling trigger event configuration bit of line 5 */
2726 #define EXTI_FTSR_TR6_Pos                   (6U)
2727 #define EXTI_FTSR_TR6_Msk                   (0x1U << EXTI_FTSR_TR6_Pos)        /*!< 0x00000040 */
2728 #define EXTI_FTSR_TR6                       EXTI_FTSR_TR6_Msk                  /*!< Falling trigger event configuration bit of line 6 */
2729 #define EXTI_FTSR_TR7_Pos                   (7U)
2730 #define EXTI_FTSR_TR7_Msk                   (0x1U << EXTI_FTSR_TR7_Pos)        /*!< 0x00000080 */
2731 #define EXTI_FTSR_TR7                       EXTI_FTSR_TR7_Msk                  /*!< Falling trigger event configuration bit of line 7 */
2732 #define EXTI_FTSR_TR8_Pos                   (8U)
2733 #define EXTI_FTSR_TR8_Msk                   (0x1U << EXTI_FTSR_TR8_Pos)        /*!< 0x00000100 */
2734 #define EXTI_FTSR_TR8                       EXTI_FTSR_TR8_Msk                  /*!< Falling trigger event configuration bit of line 8 */
2735 #define EXTI_FTSR_TR9_Pos                   (9U)
2736 #define EXTI_FTSR_TR9_Msk                   (0x1U << EXTI_FTSR_TR9_Pos)        /*!< 0x00000200 */
2737 #define EXTI_FTSR_TR9                       EXTI_FTSR_TR9_Msk                  /*!< Falling trigger event configuration bit of line 9 */
2738 #define EXTI_FTSR_TR10_Pos                  (10U)
2739 #define EXTI_FTSR_TR10_Msk                  (0x1U << EXTI_FTSR_TR10_Pos)       /*!< 0x00000400 */
2740 #define EXTI_FTSR_TR10                      EXTI_FTSR_TR10_Msk                 /*!< Falling trigger event configuration bit of line 10 */
2741 #define EXTI_FTSR_TR11_Pos                  (11U)
2742 #define EXTI_FTSR_TR11_Msk                  (0x1U << EXTI_FTSR_TR11_Pos)       /*!< 0x00000800 */
2743 #define EXTI_FTSR_TR11                      EXTI_FTSR_TR11_Msk                 /*!< Falling trigger event configuration bit of line 11 */
2744 #define EXTI_FTSR_TR12_Pos                  (12U)
2745 #define EXTI_FTSR_TR12_Msk                  (0x1U << EXTI_FTSR_TR12_Pos)       /*!< 0x00001000 */
2746 #define EXTI_FTSR_TR12                      EXTI_FTSR_TR12_Msk                 /*!< Falling trigger event configuration bit of line 12 */
2747 #define EXTI_FTSR_TR13_Pos                  (13U)
2748 #define EXTI_FTSR_TR13_Msk                  (0x1U << EXTI_FTSR_TR13_Pos)       /*!< 0x00002000 */
2749 #define EXTI_FTSR_TR13                      EXTI_FTSR_TR13_Msk                 /*!< Falling trigger event configuration bit of line 13 */
2750 #define EXTI_FTSR_TR14_Pos                  (14U)
2751 #define EXTI_FTSR_TR14_Msk                  (0x1U << EXTI_FTSR_TR14_Pos)       /*!< 0x00004000 */
2752 #define EXTI_FTSR_TR14                      EXTI_FTSR_TR14_Msk                 /*!< Falling trigger event configuration bit of line 14 */
2753 #define EXTI_FTSR_TR15_Pos                  (15U)
2754 #define EXTI_FTSR_TR15_Msk                  (0x1U << EXTI_FTSR_TR15_Pos)       /*!< 0x00008000 */
2755 #define EXTI_FTSR_TR15                      EXTI_FTSR_TR15_Msk                 /*!< Falling trigger event configuration bit of line 15 */
2756 #define EXTI_FTSR_TR16_Pos                  (16U)
2757 #define EXTI_FTSR_TR16_Msk                  (0x1U << EXTI_FTSR_TR16_Pos)       /*!< 0x00010000 */
2758 #define EXTI_FTSR_TR16                      EXTI_FTSR_TR16_Msk                 /*!< Falling trigger event configuration bit of line 16 */
2759 #define EXTI_FTSR_TR17_Pos                  (17U)
2760 #define EXTI_FTSR_TR17_Msk                  (0x1U << EXTI_FTSR_TR17_Pos)       /*!< 0x00020000 */
2761 #define EXTI_FTSR_TR17                      EXTI_FTSR_TR17_Msk                 /*!< Falling trigger event configuration bit of line 17 */
2762 #define EXTI_FTSR_TR18_Pos                  (18U)
2763 #define EXTI_FTSR_TR18_Msk                  (0x1U << EXTI_FTSR_TR18_Pos)       /*!< 0x00040000 */
2764 #define EXTI_FTSR_TR18                      EXTI_FTSR_TR18_Msk                 /*!< Falling trigger event configuration bit of line 18 */
2765 #define EXTI_FTSR_TR19_Pos                  (19U)
2766 #define EXTI_FTSR_TR19_Msk                  (0x1U << EXTI_FTSR_TR19_Pos)       /*!< 0x00080000 */
2767 #define EXTI_FTSR_TR19                      EXTI_FTSR_TR19_Msk                 /*!< Falling trigger event configuration bit of line 19 */
2768 #define EXTI_FTSR_TR20_Pos                  (20U)
2769 #define EXTI_FTSR_TR20_Msk                  (0x1U << EXTI_FTSR_TR20_Pos)       /*!< 0x00100000 */
2770 #define EXTI_FTSR_TR20                      EXTI_FTSR_TR20_Msk                 /*!< Falling trigger event configuration bit of line 20 */
2771 #define EXTI_FTSR_TR21_Pos                  (21U)
2772 #define EXTI_FTSR_TR21_Msk                  (0x1U << EXTI_FTSR_TR21_Pos)       /*!< 0x00200000 */
2773 #define EXTI_FTSR_TR21                      EXTI_FTSR_TR21_Msk                 /*!< Falling trigger event configuration bit of line 21 */
2774 #define EXTI_FTSR_TR22_Pos                  (22U)
2775 #define EXTI_FTSR_TR22_Msk                  (0x1U << EXTI_FTSR_TR22_Pos)       /*!< 0x00400000 */
2776 #define EXTI_FTSR_TR22                      EXTI_FTSR_TR22_Msk                 /*!< Falling trigger event configuration bit of line 22 */
2777 #define EXTI_FTSR_TR23_Pos                  (23U)
2778 #define EXTI_FTSR_TR23_Msk                  (0x1U << EXTI_FTSR_TR23_Pos)       /*!< 0x00800000 */
2779 #define EXTI_FTSR_TR23                      EXTI_FTSR_TR23_Msk                 /*!< Falling trigger event configuration bit of line 23 */
2780 
2781 /* References Defines */
2782 #define  EXTI_FTSR_FT0 EXTI_FTSR_TR0
2783 #define  EXTI_FTSR_FT1 EXTI_FTSR_TR1
2784 #define  EXTI_FTSR_FT2 EXTI_FTSR_TR2
2785 #define  EXTI_FTSR_FT3 EXTI_FTSR_TR3
2786 #define  EXTI_FTSR_FT4 EXTI_FTSR_TR4
2787 #define  EXTI_FTSR_FT5 EXTI_FTSR_TR5
2788 #define  EXTI_FTSR_FT6 EXTI_FTSR_TR6
2789 #define  EXTI_FTSR_FT7 EXTI_FTSR_TR7
2790 #define  EXTI_FTSR_FT8 EXTI_FTSR_TR8
2791 #define  EXTI_FTSR_FT9 EXTI_FTSR_TR9
2792 #define  EXTI_FTSR_FT10 EXTI_FTSR_TR10
2793 #define  EXTI_FTSR_FT11 EXTI_FTSR_TR11
2794 #define  EXTI_FTSR_FT12 EXTI_FTSR_TR12
2795 #define  EXTI_FTSR_FT13 EXTI_FTSR_TR13
2796 #define  EXTI_FTSR_FT14 EXTI_FTSR_TR14
2797 #define  EXTI_FTSR_FT15 EXTI_FTSR_TR15
2798 #define  EXTI_FTSR_FT16 EXTI_FTSR_TR16
2799 #define  EXTI_FTSR_FT17 EXTI_FTSR_TR17
2800 #define  EXTI_FTSR_FT18 EXTI_FTSR_TR18
2801 #define  EXTI_FTSR_FT19 EXTI_FTSR_TR19
2802 #define  EXTI_FTSR_FT20 EXTI_FTSR_TR20
2803 #define  EXTI_FTSR_FT21 EXTI_FTSR_TR21
2804 #define  EXTI_FTSR_FT22 EXTI_FTSR_TR22
2805 #define  EXTI_FTSR_FT23 EXTI_FTSR_TR23
2806 
2807 /******************  Bit definition for EXTI_SWIER register  ******************/
2808 #define EXTI_SWIER_SWIER0_Pos               (0U)
2809 #define EXTI_SWIER_SWIER0_Msk               (0x1U << EXTI_SWIER_SWIER0_Pos)    /*!< 0x00000001 */
2810 #define EXTI_SWIER_SWIER0                   EXTI_SWIER_SWIER0_Msk              /*!< Software Interrupt on line 0 */
2811 #define EXTI_SWIER_SWIER1_Pos               (1U)
2812 #define EXTI_SWIER_SWIER1_Msk               (0x1U << EXTI_SWIER_SWIER1_Pos)    /*!< 0x00000002 */
2813 #define EXTI_SWIER_SWIER1                   EXTI_SWIER_SWIER1_Msk              /*!< Software Interrupt on line 1 */
2814 #define EXTI_SWIER_SWIER2_Pos               (2U)
2815 #define EXTI_SWIER_SWIER2_Msk               (0x1U << EXTI_SWIER_SWIER2_Pos)    /*!< 0x00000004 */
2816 #define EXTI_SWIER_SWIER2                   EXTI_SWIER_SWIER2_Msk              /*!< Software Interrupt on line 2 */
2817 #define EXTI_SWIER_SWIER3_Pos               (3U)
2818 #define EXTI_SWIER_SWIER3_Msk               (0x1U << EXTI_SWIER_SWIER3_Pos)    /*!< 0x00000008 */
2819 #define EXTI_SWIER_SWIER3                   EXTI_SWIER_SWIER3_Msk              /*!< Software Interrupt on line 3 */
2820 #define EXTI_SWIER_SWIER4_Pos               (4U)
2821 #define EXTI_SWIER_SWIER4_Msk               (0x1U << EXTI_SWIER_SWIER4_Pos)    /*!< 0x00000010 */
2822 #define EXTI_SWIER_SWIER4                   EXTI_SWIER_SWIER4_Msk              /*!< Software Interrupt on line 4 */
2823 #define EXTI_SWIER_SWIER5_Pos               (5U)
2824 #define EXTI_SWIER_SWIER5_Msk               (0x1U << EXTI_SWIER_SWIER5_Pos)    /*!< 0x00000020 */
2825 #define EXTI_SWIER_SWIER5                   EXTI_SWIER_SWIER5_Msk              /*!< Software Interrupt on line 5 */
2826 #define EXTI_SWIER_SWIER6_Pos               (6U)
2827 #define EXTI_SWIER_SWIER6_Msk               (0x1U << EXTI_SWIER_SWIER6_Pos)    /*!< 0x00000040 */
2828 #define EXTI_SWIER_SWIER6                   EXTI_SWIER_SWIER6_Msk              /*!< Software Interrupt on line 6 */
2829 #define EXTI_SWIER_SWIER7_Pos               (7U)
2830 #define EXTI_SWIER_SWIER7_Msk               (0x1U << EXTI_SWIER_SWIER7_Pos)    /*!< 0x00000080 */
2831 #define EXTI_SWIER_SWIER7                   EXTI_SWIER_SWIER7_Msk              /*!< Software Interrupt on line 7 */
2832 #define EXTI_SWIER_SWIER8_Pos               (8U)
2833 #define EXTI_SWIER_SWIER8_Msk               (0x1U << EXTI_SWIER_SWIER8_Pos)    /*!< 0x00000100 */
2834 #define EXTI_SWIER_SWIER8                   EXTI_SWIER_SWIER8_Msk              /*!< Software Interrupt on line 8 */
2835 #define EXTI_SWIER_SWIER9_Pos               (9U)
2836 #define EXTI_SWIER_SWIER9_Msk               (0x1U << EXTI_SWIER_SWIER9_Pos)    /*!< 0x00000200 */
2837 #define EXTI_SWIER_SWIER9                   EXTI_SWIER_SWIER9_Msk              /*!< Software Interrupt on line 9 */
2838 #define EXTI_SWIER_SWIER10_Pos              (10U)
2839 #define EXTI_SWIER_SWIER10_Msk              (0x1U << EXTI_SWIER_SWIER10_Pos)   /*!< 0x00000400 */
2840 #define EXTI_SWIER_SWIER10                  EXTI_SWIER_SWIER10_Msk             /*!< Software Interrupt on line 10 */
2841 #define EXTI_SWIER_SWIER11_Pos              (11U)
2842 #define EXTI_SWIER_SWIER11_Msk              (0x1U << EXTI_SWIER_SWIER11_Pos)   /*!< 0x00000800 */
2843 #define EXTI_SWIER_SWIER11                  EXTI_SWIER_SWIER11_Msk             /*!< Software Interrupt on line 11 */
2844 #define EXTI_SWIER_SWIER12_Pos              (12U)
2845 #define EXTI_SWIER_SWIER12_Msk              (0x1U << EXTI_SWIER_SWIER12_Pos)   /*!< 0x00001000 */
2846 #define EXTI_SWIER_SWIER12                  EXTI_SWIER_SWIER12_Msk             /*!< Software Interrupt on line 12 */
2847 #define EXTI_SWIER_SWIER13_Pos              (13U)
2848 #define EXTI_SWIER_SWIER13_Msk              (0x1U << EXTI_SWIER_SWIER13_Pos)   /*!< 0x00002000 */
2849 #define EXTI_SWIER_SWIER13                  EXTI_SWIER_SWIER13_Msk             /*!< Software Interrupt on line 13 */
2850 #define EXTI_SWIER_SWIER14_Pos              (14U)
2851 #define EXTI_SWIER_SWIER14_Msk              (0x1U << EXTI_SWIER_SWIER14_Pos)   /*!< 0x00004000 */
2852 #define EXTI_SWIER_SWIER14                  EXTI_SWIER_SWIER14_Msk             /*!< Software Interrupt on line 14 */
2853 #define EXTI_SWIER_SWIER15_Pos              (15U)
2854 #define EXTI_SWIER_SWIER15_Msk              (0x1U << EXTI_SWIER_SWIER15_Pos)   /*!< 0x00008000 */
2855 #define EXTI_SWIER_SWIER15                  EXTI_SWIER_SWIER15_Msk             /*!< Software Interrupt on line 15 */
2856 #define EXTI_SWIER_SWIER16_Pos              (16U)
2857 #define EXTI_SWIER_SWIER16_Msk              (0x1U << EXTI_SWIER_SWIER16_Pos)   /*!< 0x00010000 */
2858 #define EXTI_SWIER_SWIER16                  EXTI_SWIER_SWIER16_Msk             /*!< Software Interrupt on line 16 */
2859 #define EXTI_SWIER_SWIER17_Pos              (17U)
2860 #define EXTI_SWIER_SWIER17_Msk              (0x1U << EXTI_SWIER_SWIER17_Pos)   /*!< 0x00020000 */
2861 #define EXTI_SWIER_SWIER17                  EXTI_SWIER_SWIER17_Msk             /*!< Software Interrupt on line 17 */
2862 #define EXTI_SWIER_SWIER18_Pos              (18U)
2863 #define EXTI_SWIER_SWIER18_Msk              (0x1U << EXTI_SWIER_SWIER18_Pos)   /*!< 0x00040000 */
2864 #define EXTI_SWIER_SWIER18                  EXTI_SWIER_SWIER18_Msk             /*!< Software Interrupt on line 18 */
2865 #define EXTI_SWIER_SWIER19_Pos              (19U)
2866 #define EXTI_SWIER_SWIER19_Msk              (0x1U << EXTI_SWIER_SWIER19_Pos)   /*!< 0x00080000 */
2867 #define EXTI_SWIER_SWIER19                  EXTI_SWIER_SWIER19_Msk             /*!< Software Interrupt on line 19 */
2868 #define EXTI_SWIER_SWIER20_Pos              (20U)
2869 #define EXTI_SWIER_SWIER20_Msk              (0x1U << EXTI_SWIER_SWIER20_Pos)   /*!< 0x00100000 */
2870 #define EXTI_SWIER_SWIER20                  EXTI_SWIER_SWIER20_Msk             /*!< Software Interrupt on line 20 */
2871 #define EXTI_SWIER_SWIER21_Pos              (21U)
2872 #define EXTI_SWIER_SWIER21_Msk              (0x1U << EXTI_SWIER_SWIER21_Pos)   /*!< 0x00200000 */
2873 #define EXTI_SWIER_SWIER21                  EXTI_SWIER_SWIER21_Msk             /*!< Software Interrupt on line 21 */
2874 #define EXTI_SWIER_SWIER22_Pos              (22U)
2875 #define EXTI_SWIER_SWIER22_Msk              (0x1U << EXTI_SWIER_SWIER22_Pos)   /*!< 0x00400000 */
2876 #define EXTI_SWIER_SWIER22                  EXTI_SWIER_SWIER22_Msk             /*!< Software Interrupt on line 22 */
2877 #define EXTI_SWIER_SWIER23_Pos              (23U)
2878 #define EXTI_SWIER_SWIER23_Msk              (0x1U << EXTI_SWIER_SWIER23_Pos)   /*!< 0x00800000 */
2879 #define EXTI_SWIER_SWIER23                  EXTI_SWIER_SWIER23_Msk             /*!< Software Interrupt on line 23 */
2880 
2881 /* References Defines */
2882 #define  EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
2883 #define  EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
2884 #define  EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
2885 #define  EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
2886 #define  EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
2887 #define  EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
2888 #define  EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
2889 #define  EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
2890 #define  EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
2891 #define  EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
2892 #define  EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
2893 #define  EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
2894 #define  EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
2895 #define  EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
2896 #define  EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
2897 #define  EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
2898 #define  EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
2899 #define  EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
2900 #define  EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18
2901 #define  EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
2902 #define  EXTI_SWIER_SWI20 EXTI_SWIER_SWIER20
2903 #define  EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
2904 #define  EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
2905 #define  EXTI_SWIER_SWI23 EXTI_SWIER_SWIER23
2906 
2907 /*******************  Bit definition for EXTI_PR register  ********************/
2908 #define EXTI_PR_PR0_Pos                     (0U)
2909 #define EXTI_PR_PR0_Msk                     (0x1U << EXTI_PR_PR0_Pos)          /*!< 0x00000001 */
2910 #define EXTI_PR_PR0                         EXTI_PR_PR0_Msk                    /*!< Pending bit for line 0 */
2911 #define EXTI_PR_PR1_Pos                     (1U)
2912 #define EXTI_PR_PR1_Msk                     (0x1U << EXTI_PR_PR1_Pos)          /*!< 0x00000002 */
2913 #define EXTI_PR_PR1                         EXTI_PR_PR1_Msk                    /*!< Pending bit for line 1 */
2914 #define EXTI_PR_PR2_Pos                     (2U)
2915 #define EXTI_PR_PR2_Msk                     (0x1U << EXTI_PR_PR2_Pos)          /*!< 0x00000004 */
2916 #define EXTI_PR_PR2                         EXTI_PR_PR2_Msk                    /*!< Pending bit for line 2 */
2917 #define EXTI_PR_PR3_Pos                     (3U)
2918 #define EXTI_PR_PR3_Msk                     (0x1U << EXTI_PR_PR3_Pos)          /*!< 0x00000008 */
2919 #define EXTI_PR_PR3                         EXTI_PR_PR3_Msk                    /*!< Pending bit for line 3 */
2920 #define EXTI_PR_PR4_Pos                     (4U)
2921 #define EXTI_PR_PR4_Msk                     (0x1U << EXTI_PR_PR4_Pos)          /*!< 0x00000010 */
2922 #define EXTI_PR_PR4                         EXTI_PR_PR4_Msk                    /*!< Pending bit for line 4 */
2923 #define EXTI_PR_PR5_Pos                     (5U)
2924 #define EXTI_PR_PR5_Msk                     (0x1U << EXTI_PR_PR5_Pos)          /*!< 0x00000020 */
2925 #define EXTI_PR_PR5                         EXTI_PR_PR5_Msk                    /*!< Pending bit for line 5 */
2926 #define EXTI_PR_PR6_Pos                     (6U)
2927 #define EXTI_PR_PR6_Msk                     (0x1U << EXTI_PR_PR6_Pos)          /*!< 0x00000040 */
2928 #define EXTI_PR_PR6                         EXTI_PR_PR6_Msk                    /*!< Pending bit for line 6 */
2929 #define EXTI_PR_PR7_Pos                     (7U)
2930 #define EXTI_PR_PR7_Msk                     (0x1U << EXTI_PR_PR7_Pos)          /*!< 0x00000080 */
2931 #define EXTI_PR_PR7                         EXTI_PR_PR7_Msk                    /*!< Pending bit for line 7 */
2932 #define EXTI_PR_PR8_Pos                     (8U)
2933 #define EXTI_PR_PR8_Msk                     (0x1U << EXTI_PR_PR8_Pos)          /*!< 0x00000100 */
2934 #define EXTI_PR_PR8                         EXTI_PR_PR8_Msk                    /*!< Pending bit for line 8 */
2935 #define EXTI_PR_PR9_Pos                     (9U)
2936 #define EXTI_PR_PR9_Msk                     (0x1U << EXTI_PR_PR9_Pos)          /*!< 0x00000200 */
2937 #define EXTI_PR_PR9                         EXTI_PR_PR9_Msk                    /*!< Pending bit for line 9 */
2938 #define EXTI_PR_PR10_Pos                    (10U)
2939 #define EXTI_PR_PR10_Msk                    (0x1U << EXTI_PR_PR10_Pos)         /*!< 0x00000400 */
2940 #define EXTI_PR_PR10                        EXTI_PR_PR10_Msk                   /*!< Pending bit for line 10 */
2941 #define EXTI_PR_PR11_Pos                    (11U)
2942 #define EXTI_PR_PR11_Msk                    (0x1U << EXTI_PR_PR11_Pos)         /*!< 0x00000800 */
2943 #define EXTI_PR_PR11                        EXTI_PR_PR11_Msk                   /*!< Pending bit for line 11 */
2944 #define EXTI_PR_PR12_Pos                    (12U)
2945 #define EXTI_PR_PR12_Msk                    (0x1U << EXTI_PR_PR12_Pos)         /*!< 0x00001000 */
2946 #define EXTI_PR_PR12                        EXTI_PR_PR12_Msk                   /*!< Pending bit for line 12 */
2947 #define EXTI_PR_PR13_Pos                    (13U)
2948 #define EXTI_PR_PR13_Msk                    (0x1U << EXTI_PR_PR13_Pos)         /*!< 0x00002000 */
2949 #define EXTI_PR_PR13                        EXTI_PR_PR13_Msk                   /*!< Pending bit for line 13 */
2950 #define EXTI_PR_PR14_Pos                    (14U)
2951 #define EXTI_PR_PR14_Msk                    (0x1U << EXTI_PR_PR14_Pos)         /*!< 0x00004000 */
2952 #define EXTI_PR_PR14                        EXTI_PR_PR14_Msk                   /*!< Pending bit for line 14 */
2953 #define EXTI_PR_PR15_Pos                    (15U)
2954 #define EXTI_PR_PR15_Msk                    (0x1U << EXTI_PR_PR15_Pos)         /*!< 0x00008000 */
2955 #define EXTI_PR_PR15                        EXTI_PR_PR15_Msk                   /*!< Pending bit for line 15 */
2956 #define EXTI_PR_PR16_Pos                    (16U)
2957 #define EXTI_PR_PR16_Msk                    (0x1U << EXTI_PR_PR16_Pos)         /*!< 0x00010000 */
2958 #define EXTI_PR_PR16                        EXTI_PR_PR16_Msk                   /*!< Pending bit for line 16 */
2959 #define EXTI_PR_PR17_Pos                    (17U)
2960 #define EXTI_PR_PR17_Msk                    (0x1U << EXTI_PR_PR17_Pos)         /*!< 0x00020000 */
2961 #define EXTI_PR_PR17                        EXTI_PR_PR17_Msk                   /*!< Pending bit for line 17 */
2962 #define EXTI_PR_PR18_Pos                    (18U)
2963 #define EXTI_PR_PR18_Msk                    (0x1U << EXTI_PR_PR18_Pos)         /*!< 0x00040000 */
2964 #define EXTI_PR_PR18                        EXTI_PR_PR18_Msk                   /*!< Pending bit for line 18 */
2965 #define EXTI_PR_PR19_Pos                    (19U)
2966 #define EXTI_PR_PR19_Msk                    (0x1U << EXTI_PR_PR19_Pos)         /*!< 0x00080000 */
2967 #define EXTI_PR_PR19                        EXTI_PR_PR19_Msk                   /*!< Pending bit for line 19 */
2968 #define EXTI_PR_PR20_Pos                    (20U)
2969 #define EXTI_PR_PR20_Msk                    (0x1U << EXTI_PR_PR20_Pos)         /*!< 0x00100000 */
2970 #define EXTI_PR_PR20                        EXTI_PR_PR20_Msk                   /*!< Pending bit for line 20 */
2971 #define EXTI_PR_PR21_Pos                    (21U)
2972 #define EXTI_PR_PR21_Msk                    (0x1U << EXTI_PR_PR21_Pos)         /*!< 0x00200000 */
2973 #define EXTI_PR_PR21                        EXTI_PR_PR21_Msk                   /*!< Pending bit for line 21 */
2974 #define EXTI_PR_PR22_Pos                    (22U)
2975 #define EXTI_PR_PR22_Msk                    (0x1U << EXTI_PR_PR22_Pos)         /*!< 0x00400000 */
2976 #define EXTI_PR_PR22                        EXTI_PR_PR22_Msk                   /*!< Pending bit for line 22 */
2977 #define EXTI_PR_PR23_Pos                    (23U)
2978 #define EXTI_PR_PR23_Msk                    (0x1U << EXTI_PR_PR23_Pos)         /*!< 0x00800000 */
2979 #define EXTI_PR_PR23                        EXTI_PR_PR23_Msk                   /*!< Pending bit for line 23 */
2980 
2981 /* References Defines */
2982 #define  EXTI_PR_PIF0 EXTI_PR_PR0
2983 #define  EXTI_PR_PIF1 EXTI_PR_PR1
2984 #define  EXTI_PR_PIF2 EXTI_PR_PR2
2985 #define  EXTI_PR_PIF3 EXTI_PR_PR3
2986 #define  EXTI_PR_PIF4 EXTI_PR_PR4
2987 #define  EXTI_PR_PIF5 EXTI_PR_PR5
2988 #define  EXTI_PR_PIF6 EXTI_PR_PR6
2989 #define  EXTI_PR_PIF7 EXTI_PR_PR7
2990 #define  EXTI_PR_PIF8 EXTI_PR_PR8
2991 #define  EXTI_PR_PIF9 EXTI_PR_PR9
2992 #define  EXTI_PR_PIF10 EXTI_PR_PR10
2993 #define  EXTI_PR_PIF11 EXTI_PR_PR11
2994 #define  EXTI_PR_PIF12 EXTI_PR_PR12
2995 #define  EXTI_PR_PIF13 EXTI_PR_PR13
2996 #define  EXTI_PR_PIF14 EXTI_PR_PR14
2997 #define  EXTI_PR_PIF15 EXTI_PR_PR15
2998 #define  EXTI_PR_PIF16 EXTI_PR_PR16
2999 #define  EXTI_PR_PIF17 EXTI_PR_PR17
3000 #define  EXTI_PR_PIF18 EXTI_PR_PR18
3001 #define  EXTI_PR_PIF19 EXTI_PR_PR19
3002 #define  EXTI_PR_PIF20 EXTI_PR_PR20
3003 #define  EXTI_PR_PIF21 EXTI_PR_PR21
3004 #define  EXTI_PR_PIF22 EXTI_PR_PR22
3005 #define  EXTI_PR_PIF23 EXTI_PR_PR23
3006 
3007 /******************************************************************************/
3008 /*                                                                            */
3009 /*                FLASH, DATA EEPROM and Option Bytes Registers               */
3010 /*                        (FLASH, DATA_EEPROM, OB)                            */
3011 /*                                                                            */
3012 /******************************************************************************/
3013 
3014 /*******************  Bit definition for FLASH_ACR register  ******************/
3015 #define FLASH_ACR_LATENCY_Pos                (0U)
3016 #define FLASH_ACR_LATENCY_Msk                (0x1U << FLASH_ACR_LATENCY_Pos)   /*!< 0x00000001 */
3017 #define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Latency */
3018 #define FLASH_ACR_PRFTEN_Pos                 (1U)
3019 #define FLASH_ACR_PRFTEN_Msk                 (0x1U << FLASH_ACR_PRFTEN_Pos)    /*!< 0x00000002 */
3020 #define FLASH_ACR_PRFTEN                     FLASH_ACR_PRFTEN_Msk              /*!< Prefetch Buffer Enable */
3021 #define FLASH_ACR_ACC64_Pos                  (2U)
3022 #define FLASH_ACR_ACC64_Msk                  (0x1U << FLASH_ACR_ACC64_Pos)     /*!< 0x00000004 */
3023 #define FLASH_ACR_ACC64                      FLASH_ACR_ACC64_Msk               /*!< Access 64 bits */
3024 #define FLASH_ACR_SLEEP_PD_Pos               (3U)
3025 #define FLASH_ACR_SLEEP_PD_Msk               (0x1U << FLASH_ACR_SLEEP_PD_Pos)  /*!< 0x00000008 */
3026 #define FLASH_ACR_SLEEP_PD                   FLASH_ACR_SLEEP_PD_Msk            /*!< Flash mode during sleep mode */
3027 #define FLASH_ACR_RUN_PD_Pos                 (4U)
3028 #define FLASH_ACR_RUN_PD_Msk                 (0x1U << FLASH_ACR_RUN_PD_Pos)    /*!< 0x00000010 */
3029 #define FLASH_ACR_RUN_PD                     FLASH_ACR_RUN_PD_Msk              /*!< Flash mode during RUN mode */
3030 
3031 /*******************  Bit definition for FLASH_PECR register  ******************/
3032 #define FLASH_PECR_PELOCK_Pos                (0U)
3033 #define FLASH_PECR_PELOCK_Msk                (0x1U << FLASH_PECR_PELOCK_Pos)   /*!< 0x00000001 */
3034 #define FLASH_PECR_PELOCK                    FLASH_PECR_PELOCK_Msk             /*!< FLASH_PECR and Flash data Lock */
3035 #define FLASH_PECR_PRGLOCK_Pos               (1U)
3036 #define FLASH_PECR_PRGLOCK_Msk               (0x1U << FLASH_PECR_PRGLOCK_Pos)  /*!< 0x00000002 */
3037 #define FLASH_PECR_PRGLOCK                   FLASH_PECR_PRGLOCK_Msk            /*!< Program matrix Lock */
3038 #define FLASH_PECR_OPTLOCK_Pos               (2U)
3039 #define FLASH_PECR_OPTLOCK_Msk               (0x1U << FLASH_PECR_OPTLOCK_Pos)  /*!< 0x00000004 */
3040 #define FLASH_PECR_OPTLOCK                   FLASH_PECR_OPTLOCK_Msk            /*!< Option byte matrix Lock */
3041 #define FLASH_PECR_PROG_Pos                  (3U)
3042 #define FLASH_PECR_PROG_Msk                  (0x1U << FLASH_PECR_PROG_Pos)     /*!< 0x00000008 */
3043 #define FLASH_PECR_PROG                      FLASH_PECR_PROG_Msk               /*!< Program matrix selection */
3044 #define FLASH_PECR_DATA_Pos                  (4U)
3045 #define FLASH_PECR_DATA_Msk                  (0x1U << FLASH_PECR_DATA_Pos)     /*!< 0x00000010 */
3046 #define FLASH_PECR_DATA                      FLASH_PECR_DATA_Msk               /*!< Data matrix selection */
3047 #define FLASH_PECR_FTDW_Pos                  (8U)
3048 #define FLASH_PECR_FTDW_Msk                  (0x1U << FLASH_PECR_FTDW_Pos)     /*!< 0x00000100 */
3049 #define FLASH_PECR_FTDW                      FLASH_PECR_FTDW_Msk               /*!< Fixed Time Data write for Word/Half Word/Byte programming */
3050 #define FLASH_PECR_ERASE_Pos                 (9U)
3051 #define FLASH_PECR_ERASE_Msk                 (0x1U << FLASH_PECR_ERASE_Pos)    /*!< 0x00000200 */
3052 #define FLASH_PECR_ERASE                     FLASH_PECR_ERASE_Msk              /*!< Page erasing mode */
3053 #define FLASH_PECR_FPRG_Pos                  (10U)
3054 #define FLASH_PECR_FPRG_Msk                  (0x1U << FLASH_PECR_FPRG_Pos)     /*!< 0x00000400 */
3055 #define FLASH_PECR_FPRG                      FLASH_PECR_FPRG_Msk               /*!< Fast Page/Half Page programming mode */
3056 #define FLASH_PECR_EOPIE_Pos                 (16U)
3057 #define FLASH_PECR_EOPIE_Msk                 (0x1U << FLASH_PECR_EOPIE_Pos)    /*!< 0x00010000 */
3058 #define FLASH_PECR_EOPIE                     FLASH_PECR_EOPIE_Msk              /*!< End of programming interrupt */
3059 #define FLASH_PECR_ERRIE_Pos                 (17U)
3060 #define FLASH_PECR_ERRIE_Msk                 (0x1U << FLASH_PECR_ERRIE_Pos)    /*!< 0x00020000 */
3061 #define FLASH_PECR_ERRIE                     FLASH_PECR_ERRIE_Msk              /*!< Error interrupt */
3062 #define FLASH_PECR_OBL_LAUNCH_Pos            (18U)
3063 #define FLASH_PECR_OBL_LAUNCH_Msk            (0x1U << FLASH_PECR_OBL_LAUNCH_Pos) /*!< 0x00040000 */
3064 #define FLASH_PECR_OBL_LAUNCH                FLASH_PECR_OBL_LAUNCH_Msk         /*!< Launch the option byte loading */
3065 
3066 /******************  Bit definition for FLASH_PDKEYR register  ******************/
3067 #define FLASH_PDKEYR_PDKEYR_Pos              (0U)
3068 #define FLASH_PDKEYR_PDKEYR_Msk              (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos) /*!< 0xFFFFFFFF */
3069 #define FLASH_PDKEYR_PDKEYR                  FLASH_PDKEYR_PDKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
3070 
3071 /******************  Bit definition for FLASH_PEKEYR register  ******************/
3072 #define FLASH_PEKEYR_PEKEYR_Pos              (0U)
3073 #define FLASH_PEKEYR_PEKEYR_Msk              (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos) /*!< 0xFFFFFFFF */
3074 #define FLASH_PEKEYR_PEKEYR                  FLASH_PEKEYR_PEKEYR_Msk           /*!< FLASH_PEC and data matrix Key */
3075 
3076 /******************  Bit definition for FLASH_PRGKEYR register  ******************/
3077 #define FLASH_PRGKEYR_PRGKEYR_Pos            (0U)
3078 #define FLASH_PRGKEYR_PRGKEYR_Msk            (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos) /*!< 0xFFFFFFFF */
3079 #define FLASH_PRGKEYR_PRGKEYR                FLASH_PRGKEYR_PRGKEYR_Msk         /*!< Program matrix Key */
3080 
3081 /******************  Bit definition for FLASH_OPTKEYR register  ******************/
3082 #define FLASH_OPTKEYR_OPTKEYR_Pos            (0U)
3083 #define FLASH_OPTKEYR_OPTKEYR_Msk            (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
3084 #define FLASH_OPTKEYR_OPTKEYR                FLASH_OPTKEYR_OPTKEYR_Msk         /*!< Option bytes matrix Key */
3085 
3086 /******************  Bit definition for FLASH_SR register  *******************/
3087 #define FLASH_SR_BSY_Pos                     (0U)
3088 #define FLASH_SR_BSY_Msk                     (0x1U << FLASH_SR_BSY_Pos)        /*!< 0x00000001 */
3089 #define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy */
3090 #define FLASH_SR_EOP_Pos                     (1U)
3091 #define FLASH_SR_EOP_Msk                     (0x1U << FLASH_SR_EOP_Pos)        /*!< 0x00000002 */
3092 #define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End Of Programming*/
3093 #define FLASH_SR_ENDHV_Pos                   (2U)
3094 #define FLASH_SR_ENDHV_Msk                   (0x1U << FLASH_SR_ENDHV_Pos)      /*!< 0x00000004 */
3095 #define FLASH_SR_ENDHV                       FLASH_SR_ENDHV_Msk                /*!< End of high voltage */
3096 #define FLASH_SR_READY_Pos                   (3U)
3097 #define FLASH_SR_READY_Msk                   (0x1U << FLASH_SR_READY_Pos)      /*!< 0x00000008 */
3098 #define FLASH_SR_READY                       FLASH_SR_READY_Msk                /*!< Flash ready after low power mode */
3099 
3100 #define FLASH_SR_WRPERR_Pos                  (8U)
3101 #define FLASH_SR_WRPERR_Msk                  (0x1U << FLASH_SR_WRPERR_Pos)     /*!< 0x00000100 */
3102 #define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protected error */
3103 #define FLASH_SR_PGAERR_Pos                  (9U)
3104 #define FLASH_SR_PGAERR_Msk                  (0x1U << FLASH_SR_PGAERR_Pos)     /*!< 0x00000200 */
3105 #define FLASH_SR_PGAERR                      FLASH_SR_PGAERR_Msk               /*!< Programming Alignment Error */
3106 #define FLASH_SR_SIZERR_Pos                  (10U)
3107 #define FLASH_SR_SIZERR_Msk                  (0x1U << FLASH_SR_SIZERR_Pos)     /*!< 0x00000400 */
3108 #define FLASH_SR_SIZERR                      FLASH_SR_SIZERR_Msk               /*!< Size error */
3109 #define FLASH_SR_OPTVERR_Pos                 (11U)
3110 #define FLASH_SR_OPTVERR_Msk                 (0x1U << FLASH_SR_OPTVERR_Pos)    /*!< 0x00000800 */
3111 #define FLASH_SR_OPTVERR                     FLASH_SR_OPTVERR_Msk              /*!< Option validity error */
3112 #define FLASH_SR_OPTVERRUSR_Pos              (12U)
3113 #define FLASH_SR_OPTVERRUSR_Msk              (0x1U << FLASH_SR_OPTVERRUSR_Pos) /*!< 0x00001000 */
3114 #define FLASH_SR_OPTVERRUSR                  FLASH_SR_OPTVERRUSR_Msk           /*!< Option User validity error */
3115 #define FLASH_SR_RDERR_Pos                   (13U)
3116 #define FLASH_SR_RDERR_Msk                   (0x1U << FLASH_SR_RDERR_Pos)      /*!< 0x00002000 */
3117 #define FLASH_SR_RDERR                       FLASH_SR_RDERR_Msk                /*!< Read protected error */
3118 
3119 /******************  Bit definition for FLASH_OBR register  *******************/
3120 #define FLASH_OBR_RDPRT_Pos                  (0U)
3121 #define FLASH_OBR_RDPRT_Msk                  (0xFFU << FLASH_OBR_RDPRT_Pos)    /*!< 0x000000FF */
3122 #define FLASH_OBR_RDPRT                      FLASH_OBR_RDPRT_Msk               /*!< Read Protection */
3123 #define FLASH_OBR_SPRMOD_Pos                 (8U)
3124 #define FLASH_OBR_SPRMOD_Msk                 (0x1U << FLASH_OBR_SPRMOD_Pos)    /*!< 0x00000100 */
3125 #define FLASH_OBR_SPRMOD                     FLASH_OBR_SPRMOD_Msk              /*!< Selection of protection mode of WPRi bits */
3126 #define FLASH_OBR_BOR_LEV_Pos                (16U)
3127 #define FLASH_OBR_BOR_LEV_Msk                (0xFU << FLASH_OBR_BOR_LEV_Pos)   /*!< 0x000F0000 */
3128 #define FLASH_OBR_BOR_LEV                    FLASH_OBR_BOR_LEV_Msk             /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
3129 #define FLASH_OBR_USER_Pos                   (20U)
3130 #define FLASH_OBR_USER_Msk                   (0x7U << FLASH_OBR_USER_Pos)      /*!< 0x00700000 */
3131 #define FLASH_OBR_USER                       FLASH_OBR_USER_Msk                /*!< User Option Bytes */
3132 #define FLASH_OBR_IWDG_SW_Pos                (20U)
3133 #define FLASH_OBR_IWDG_SW_Msk                (0x1U << FLASH_OBR_IWDG_SW_Pos)   /*!< 0x00100000 */
3134 #define FLASH_OBR_IWDG_SW                    FLASH_OBR_IWDG_SW_Msk             /*!< IWDG_SW */
3135 #define FLASH_OBR_nRST_STOP_Pos              (21U)
3136 #define FLASH_OBR_nRST_STOP_Msk              (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00200000 */
3137 #define FLASH_OBR_nRST_STOP                  FLASH_OBR_nRST_STOP_Msk           /*!< nRST_STOP */
3138 #define FLASH_OBR_nRST_STDBY_Pos             (22U)
3139 #define FLASH_OBR_nRST_STDBY_Msk             (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00400000 */
3140 #define FLASH_OBR_nRST_STDBY                 FLASH_OBR_nRST_STDBY_Msk          /*!< nRST_STDBY */
3141 
3142 /******************  Bit definition for FLASH_WRPR register  ******************/
3143 #define FLASH_WRPR1_WRP_Pos                  (0U)
3144 #define FLASH_WRPR1_WRP_Msk                  (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos) /*!< 0xFFFFFFFF */
3145 #define FLASH_WRPR1_WRP                      FLASH_WRPR1_WRP_Msk               /*!< Write Protect sectors 0  to 31  */
3146 #define FLASH_WRPR2_WRP_Pos                  (0U)
3147 #define FLASH_WRPR2_WRP_Msk                  (0xFFFFFFFFU << FLASH_WRPR2_WRP_Pos) /*!< 0xFFFFFFFF */
3148 #define FLASH_WRPR2_WRP                      FLASH_WRPR2_WRP_Msk               /*!< Write Protect sectors 32 to 63  */
3149 
3150 /******************************************************************************/
3151 /*                                                                            */
3152 /*                            General Purpose I/O                             */
3153 /*                                                                            */
3154 /******************************************************************************/
3155 /******************  Bits definition for GPIO_MODER register  *****************/
3156 #define GPIO_MODER_MODER0_Pos                (0U)
3157 #define GPIO_MODER_MODER0_Msk                (0x3U << GPIO_MODER_MODER0_Pos)   /*!< 0x00000003 */
3158 #define GPIO_MODER_MODER0                    GPIO_MODER_MODER0_Msk
3159 #define GPIO_MODER_MODER0_0                  (0x1U << GPIO_MODER_MODER0_Pos)   /*!< 0x00000001 */
3160 #define GPIO_MODER_MODER0_1                  (0x2U << GPIO_MODER_MODER0_Pos)   /*!< 0x00000002 */
3161 
3162 #define GPIO_MODER_MODER1_Pos                (2U)
3163 #define GPIO_MODER_MODER1_Msk                (0x3U << GPIO_MODER_MODER1_Pos)   /*!< 0x0000000C */
3164 #define GPIO_MODER_MODER1                    GPIO_MODER_MODER1_Msk
3165 #define GPIO_MODER_MODER1_0                  (0x1U << GPIO_MODER_MODER1_Pos)   /*!< 0x00000004 */
3166 #define GPIO_MODER_MODER1_1                  (0x2U << GPIO_MODER_MODER1_Pos)   /*!< 0x00000008 */
3167 
3168 #define GPIO_MODER_MODER2_Pos                (4U)
3169 #define GPIO_MODER_MODER2_Msk                (0x3U << GPIO_MODER_MODER2_Pos)   /*!< 0x00000030 */
3170 #define GPIO_MODER_MODER2                    GPIO_MODER_MODER2_Msk
3171 #define GPIO_MODER_MODER2_0                  (0x1U << GPIO_MODER_MODER2_Pos)   /*!< 0x00000010 */
3172 #define GPIO_MODER_MODER2_1                  (0x2U << GPIO_MODER_MODER2_Pos)   /*!< 0x00000020 */
3173 
3174 #define GPIO_MODER_MODER3_Pos                (6U)
3175 #define GPIO_MODER_MODER3_Msk                (0x3U << GPIO_MODER_MODER3_Pos)   /*!< 0x000000C0 */
3176 #define GPIO_MODER_MODER3                    GPIO_MODER_MODER3_Msk
3177 #define GPIO_MODER_MODER3_0                  (0x1U << GPIO_MODER_MODER3_Pos)   /*!< 0x00000040 */
3178 #define GPIO_MODER_MODER3_1                  (0x2U << GPIO_MODER_MODER3_Pos)   /*!< 0x00000080 */
3179 
3180 #define GPIO_MODER_MODER4_Pos                (8U)
3181 #define GPIO_MODER_MODER4_Msk                (0x3U << GPIO_MODER_MODER4_Pos)   /*!< 0x00000300 */
3182 #define GPIO_MODER_MODER4                    GPIO_MODER_MODER4_Msk
3183 #define GPIO_MODER_MODER4_0                  (0x1U << GPIO_MODER_MODER4_Pos)   /*!< 0x00000100 */
3184 #define GPIO_MODER_MODER4_1                  (0x2U << GPIO_MODER_MODER4_Pos)   /*!< 0x00000200 */
3185 
3186 #define GPIO_MODER_MODER5_Pos                (10U)
3187 #define GPIO_MODER_MODER5_Msk                (0x3U << GPIO_MODER_MODER5_Pos)   /*!< 0x00000C00 */
3188 #define GPIO_MODER_MODER5                    GPIO_MODER_MODER5_Msk
3189 #define GPIO_MODER_MODER5_0                  (0x1U << GPIO_MODER_MODER5_Pos)   /*!< 0x00000400 */
3190 #define GPIO_MODER_MODER5_1                  (0x2U << GPIO_MODER_MODER5_Pos)   /*!< 0x00000800 */
3191 
3192 #define GPIO_MODER_MODER6_Pos                (12U)
3193 #define GPIO_MODER_MODER6_Msk                (0x3U << GPIO_MODER_MODER6_Pos)   /*!< 0x00003000 */
3194 #define GPIO_MODER_MODER6                    GPIO_MODER_MODER6_Msk
3195 #define GPIO_MODER_MODER6_0                  (0x1U << GPIO_MODER_MODER6_Pos)   /*!< 0x00001000 */
3196 #define GPIO_MODER_MODER6_1                  (0x2U << GPIO_MODER_MODER6_Pos)   /*!< 0x00002000 */
3197 
3198 #define GPIO_MODER_MODER7_Pos                (14U)
3199 #define GPIO_MODER_MODER7_Msk                (0x3U << GPIO_MODER_MODER7_Pos)   /*!< 0x0000C000 */
3200 #define GPIO_MODER_MODER7                    GPIO_MODER_MODER7_Msk
3201 #define GPIO_MODER_MODER7_0                  (0x1U << GPIO_MODER_MODER7_Pos)   /*!< 0x00004000 */
3202 #define GPIO_MODER_MODER7_1                  (0x2U << GPIO_MODER_MODER7_Pos)   /*!< 0x00008000 */
3203 
3204 #define GPIO_MODER_MODER8_Pos                (16U)
3205 #define GPIO_MODER_MODER8_Msk                (0x3U << GPIO_MODER_MODER8_Pos)   /*!< 0x00030000 */
3206 #define GPIO_MODER_MODER8                    GPIO_MODER_MODER8_Msk
3207 #define GPIO_MODER_MODER8_0                  (0x1U << GPIO_MODER_MODER8_Pos)   /*!< 0x00010000 */
3208 #define GPIO_MODER_MODER8_1                  (0x2U << GPIO_MODER_MODER8_Pos)   /*!< 0x00020000 */
3209 
3210 #define GPIO_MODER_MODER9_Pos                (18U)
3211 #define GPIO_MODER_MODER9_Msk                (0x3U << GPIO_MODER_MODER9_Pos)   /*!< 0x000C0000 */
3212 #define GPIO_MODER_MODER9                    GPIO_MODER_MODER9_Msk
3213 #define GPIO_MODER_MODER9_0                  (0x1U << GPIO_MODER_MODER9_Pos)   /*!< 0x00040000 */
3214 #define GPIO_MODER_MODER9_1                  (0x2U << GPIO_MODER_MODER9_Pos)   /*!< 0x00080000 */
3215 
3216 #define GPIO_MODER_MODER10_Pos               (20U)
3217 #define GPIO_MODER_MODER10_Msk               (0x3U << GPIO_MODER_MODER10_Pos)  /*!< 0x00300000 */
3218 #define GPIO_MODER_MODER10                   GPIO_MODER_MODER10_Msk
3219 #define GPIO_MODER_MODER10_0                 (0x1U << GPIO_MODER_MODER10_Pos)  /*!< 0x00100000 */
3220 #define GPIO_MODER_MODER10_1                 (0x2U << GPIO_MODER_MODER10_Pos)  /*!< 0x00200000 */
3221 
3222 #define GPIO_MODER_MODER11_Pos               (22U)
3223 #define GPIO_MODER_MODER11_Msk               (0x3U << GPIO_MODER_MODER11_Pos)  /*!< 0x00C00000 */
3224 #define GPIO_MODER_MODER11                   GPIO_MODER_MODER11_Msk
3225 #define GPIO_MODER_MODER11_0                 (0x1U << GPIO_MODER_MODER11_Pos)  /*!< 0x00400000 */
3226 #define GPIO_MODER_MODER11_1                 (0x2U << GPIO_MODER_MODER11_Pos)  /*!< 0x00800000 */
3227 
3228 #define GPIO_MODER_MODER12_Pos               (24U)
3229 #define GPIO_MODER_MODER12_Msk               (0x3U << GPIO_MODER_MODER12_Pos)  /*!< 0x03000000 */
3230 #define GPIO_MODER_MODER12                   GPIO_MODER_MODER12_Msk
3231 #define GPIO_MODER_MODER12_0                 (0x1U << GPIO_MODER_MODER12_Pos)  /*!< 0x01000000 */
3232 #define GPIO_MODER_MODER12_1                 (0x2U << GPIO_MODER_MODER12_Pos)  /*!< 0x02000000 */
3233 
3234 #define GPIO_MODER_MODER13_Pos               (26U)
3235 #define GPIO_MODER_MODER13_Msk               (0x3U << GPIO_MODER_MODER13_Pos)  /*!< 0x0C000000 */
3236 #define GPIO_MODER_MODER13                   GPIO_MODER_MODER13_Msk
3237 #define GPIO_MODER_MODER13_0                 (0x1U << GPIO_MODER_MODER13_Pos)  /*!< 0x04000000 */
3238 #define GPIO_MODER_MODER13_1                 (0x2U << GPIO_MODER_MODER13_Pos)  /*!< 0x08000000 */
3239 
3240 #define GPIO_MODER_MODER14_Pos               (28U)
3241 #define GPIO_MODER_MODER14_Msk               (0x3U << GPIO_MODER_MODER14_Pos)  /*!< 0x30000000 */
3242 #define GPIO_MODER_MODER14                   GPIO_MODER_MODER14_Msk
3243 #define GPIO_MODER_MODER14_0                 (0x1U << GPIO_MODER_MODER14_Pos)  /*!< 0x10000000 */
3244 #define GPIO_MODER_MODER14_1                 (0x2U << GPIO_MODER_MODER14_Pos)  /*!< 0x20000000 */
3245 
3246 #define GPIO_MODER_MODER15_Pos               (30U)
3247 #define GPIO_MODER_MODER15_Msk               (0x3U << GPIO_MODER_MODER15_Pos)  /*!< 0xC0000000 */
3248 #define GPIO_MODER_MODER15                   GPIO_MODER_MODER15_Msk
3249 #define GPIO_MODER_MODER15_0                 (0x1U << GPIO_MODER_MODER15_Pos)  /*!< 0x40000000 */
3250 #define GPIO_MODER_MODER15_1                 (0x2U << GPIO_MODER_MODER15_Pos)  /*!< 0x80000000 */
3251 
3252 /******************  Bits definition for GPIO_OTYPER register  ****************/
3253 #define GPIO_OTYPER_OT_0                     (0x00000001U)
3254 #define GPIO_OTYPER_OT_1                     (0x00000002U)
3255 #define GPIO_OTYPER_OT_2                     (0x00000004U)
3256 #define GPIO_OTYPER_OT_3                     (0x00000008U)
3257 #define GPIO_OTYPER_OT_4                     (0x00000010U)
3258 #define GPIO_OTYPER_OT_5                     (0x00000020U)
3259 #define GPIO_OTYPER_OT_6                     (0x00000040U)
3260 #define GPIO_OTYPER_OT_7                     (0x00000080U)
3261 #define GPIO_OTYPER_OT_8                     (0x00000100U)
3262 #define GPIO_OTYPER_OT_9                     (0x00000200U)
3263 #define GPIO_OTYPER_OT_10                    (0x00000400U)
3264 #define GPIO_OTYPER_OT_11                    (0x00000800U)
3265 #define GPIO_OTYPER_OT_12                    (0x00001000U)
3266 #define GPIO_OTYPER_OT_13                    (0x00002000U)
3267 #define GPIO_OTYPER_OT_14                    (0x00004000U)
3268 #define GPIO_OTYPER_OT_15                    (0x00008000U)
3269 
3270 /******************  Bits definition for GPIO_OSPEEDR register  ***************/
3271 #define GPIO_OSPEEDER_OSPEEDR0_Pos           (0U)
3272 #define GPIO_OSPEEDER_OSPEEDR0_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000003 */
3273 #define GPIO_OSPEEDER_OSPEEDR0               GPIO_OSPEEDER_OSPEEDR0_Msk
3274 #define GPIO_OSPEEDER_OSPEEDR0_0             (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000001 */
3275 #define GPIO_OSPEEDER_OSPEEDR0_1             (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos) /*!< 0x00000002 */
3276 
3277 #define GPIO_OSPEEDER_OSPEEDR1_Pos           (2U)
3278 #define GPIO_OSPEEDER_OSPEEDR1_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x0000000C */
3279 #define GPIO_OSPEEDER_OSPEEDR1               GPIO_OSPEEDER_OSPEEDR1_Msk
3280 #define GPIO_OSPEEDER_OSPEEDR1_0             (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000004 */
3281 #define GPIO_OSPEEDER_OSPEEDR1_1             (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos) /*!< 0x00000008 */
3282 
3283 #define GPIO_OSPEEDER_OSPEEDR2_Pos           (4U)
3284 #define GPIO_OSPEEDER_OSPEEDR2_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000030 */
3285 #define GPIO_OSPEEDER_OSPEEDR2               GPIO_OSPEEDER_OSPEEDR2_Msk
3286 #define GPIO_OSPEEDER_OSPEEDR2_0             (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000010 */
3287 #define GPIO_OSPEEDER_OSPEEDR2_1             (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos) /*!< 0x00000020 */
3288 
3289 #define GPIO_OSPEEDER_OSPEEDR3_Pos           (6U)
3290 #define GPIO_OSPEEDER_OSPEEDR3_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x000000C0 */
3291 #define GPIO_OSPEEDER_OSPEEDR3               GPIO_OSPEEDER_OSPEEDR3_Msk
3292 #define GPIO_OSPEEDER_OSPEEDR3_0             (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000040 */
3293 #define GPIO_OSPEEDER_OSPEEDR3_1             (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos) /*!< 0x00000080 */
3294 
3295 #define GPIO_OSPEEDER_OSPEEDR4_Pos           (8U)
3296 #define GPIO_OSPEEDER_OSPEEDR4_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000300 */
3297 #define GPIO_OSPEEDER_OSPEEDR4               GPIO_OSPEEDER_OSPEEDR4_Msk
3298 #define GPIO_OSPEEDER_OSPEEDR4_0             (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000100 */
3299 #define GPIO_OSPEEDER_OSPEEDR4_1             (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos) /*!< 0x00000200 */
3300 
3301 #define GPIO_OSPEEDER_OSPEEDR5_Pos           (10U)
3302 #define GPIO_OSPEEDER_OSPEEDR5_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000C00 */
3303 #define GPIO_OSPEEDER_OSPEEDR5               GPIO_OSPEEDER_OSPEEDR5_Msk
3304 #define GPIO_OSPEEDER_OSPEEDR5_0             (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000400 */
3305 #define GPIO_OSPEEDER_OSPEEDR5_1             (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos) /*!< 0x00000800 */
3306 
3307 #define GPIO_OSPEEDER_OSPEEDR6_Pos           (12U)
3308 #define GPIO_OSPEEDER_OSPEEDR6_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00003000 */
3309 #define GPIO_OSPEEDER_OSPEEDR6               GPIO_OSPEEDER_OSPEEDR6_Msk
3310 #define GPIO_OSPEEDER_OSPEEDR6_0             (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00001000 */
3311 #define GPIO_OSPEEDER_OSPEEDR6_1             (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos) /*!< 0x00002000 */
3312 
3313 #define GPIO_OSPEEDER_OSPEEDR7_Pos           (14U)
3314 #define GPIO_OSPEEDER_OSPEEDR7_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x0000C000 */
3315 #define GPIO_OSPEEDER_OSPEEDR7               GPIO_OSPEEDER_OSPEEDR7_Msk
3316 #define GPIO_OSPEEDER_OSPEEDR7_0             (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00004000 */
3317 #define GPIO_OSPEEDER_OSPEEDR7_1             (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos) /*!< 0x00008000 */
3318 
3319 #define GPIO_OSPEEDER_OSPEEDR8_Pos           (16U)
3320 #define GPIO_OSPEEDER_OSPEEDR8_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00030000 */
3321 #define GPIO_OSPEEDER_OSPEEDR8               GPIO_OSPEEDER_OSPEEDR8_Msk
3322 #define GPIO_OSPEEDER_OSPEEDR8_0             (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00010000 */
3323 #define GPIO_OSPEEDER_OSPEEDR8_1             (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos) /*!< 0x00020000 */
3324 
3325 #define GPIO_OSPEEDER_OSPEEDR9_Pos           (18U)
3326 #define GPIO_OSPEEDER_OSPEEDR9_Msk           (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x000C0000 */
3327 #define GPIO_OSPEEDER_OSPEEDR9               GPIO_OSPEEDER_OSPEEDR9_Msk
3328 #define GPIO_OSPEEDER_OSPEEDR9_0             (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00040000 */
3329 #define GPIO_OSPEEDER_OSPEEDR9_1             (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos) /*!< 0x00080000 */
3330 
3331 #define GPIO_OSPEEDER_OSPEEDR10_Pos          (20U)
3332 #define GPIO_OSPEEDER_OSPEEDR10_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00300000 */
3333 #define GPIO_OSPEEDER_OSPEEDR10              GPIO_OSPEEDER_OSPEEDR10_Msk
3334 #define GPIO_OSPEEDER_OSPEEDR10_0            (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00100000 */
3335 #define GPIO_OSPEEDER_OSPEEDR10_1            (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos) /*!< 0x00200000 */
3336 
3337 #define GPIO_OSPEEDER_OSPEEDR11_Pos          (22U)
3338 #define GPIO_OSPEEDER_OSPEEDR11_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00C00000 */
3339 #define GPIO_OSPEEDER_OSPEEDR11              GPIO_OSPEEDER_OSPEEDR11_Msk
3340 #define GPIO_OSPEEDER_OSPEEDR11_0            (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00400000 */
3341 #define GPIO_OSPEEDER_OSPEEDR11_1            (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos) /*!< 0x00800000 */
3342 
3343 #define GPIO_OSPEEDER_OSPEEDR12_Pos          (24U)
3344 #define GPIO_OSPEEDER_OSPEEDR12_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x03000000 */
3345 #define GPIO_OSPEEDER_OSPEEDR12              GPIO_OSPEEDER_OSPEEDR12_Msk
3346 #define GPIO_OSPEEDER_OSPEEDR12_0            (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x01000000 */
3347 #define GPIO_OSPEEDER_OSPEEDR12_1            (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos) /*!< 0x02000000 */
3348 
3349 #define GPIO_OSPEEDER_OSPEEDR13_Pos          (26U)
3350 #define GPIO_OSPEEDER_OSPEEDR13_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x0C000000 */
3351 #define GPIO_OSPEEDER_OSPEEDR13              GPIO_OSPEEDER_OSPEEDR13_Msk
3352 #define GPIO_OSPEEDER_OSPEEDR13_0            (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x04000000 */
3353 #define GPIO_OSPEEDER_OSPEEDR13_1            (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos) /*!< 0x08000000 */
3354 
3355 #define GPIO_OSPEEDER_OSPEEDR14_Pos          (28U)
3356 #define GPIO_OSPEEDER_OSPEEDR14_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x30000000 */
3357 #define GPIO_OSPEEDER_OSPEEDR14              GPIO_OSPEEDER_OSPEEDR14_Msk
3358 #define GPIO_OSPEEDER_OSPEEDR14_0            (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x10000000 */
3359 #define GPIO_OSPEEDER_OSPEEDR14_1            (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos) /*!< 0x20000000 */
3360 
3361 #define GPIO_OSPEEDER_OSPEEDR15_Pos          (30U)
3362 #define GPIO_OSPEEDER_OSPEEDR15_Msk          (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0xC0000000 */
3363 #define GPIO_OSPEEDER_OSPEEDR15              GPIO_OSPEEDER_OSPEEDR15_Msk
3364 #define GPIO_OSPEEDER_OSPEEDR15_0            (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x40000000 */
3365 #define GPIO_OSPEEDER_OSPEEDR15_1            (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos) /*!< 0x80000000 */
3366 
3367 /******************  Bits definition for GPIO_PUPDR register  *****************/
3368 #define GPIO_PUPDR_PUPDR0_Pos                (0U)
3369 #define GPIO_PUPDR_PUPDR0_Msk                (0x3U << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000003 */
3370 #define GPIO_PUPDR_PUPDR0                    GPIO_PUPDR_PUPDR0_Msk
3371 #define GPIO_PUPDR_PUPDR0_0                  (0x1U << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000001 */
3372 #define GPIO_PUPDR_PUPDR0_1                  (0x2U << GPIO_PUPDR_PUPDR0_Pos)   /*!< 0x00000002 */
3373 
3374 #define GPIO_PUPDR_PUPDR1_Pos                (2U)
3375 #define GPIO_PUPDR_PUPDR1_Msk                (0x3U << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x0000000C */
3376 #define GPIO_PUPDR_PUPDR1                    GPIO_PUPDR_PUPDR1_Msk
3377 #define GPIO_PUPDR_PUPDR1_0                  (0x1U << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000004 */
3378 #define GPIO_PUPDR_PUPDR1_1                  (0x2U << GPIO_PUPDR_PUPDR1_Pos)   /*!< 0x00000008 */
3379 
3380 #define GPIO_PUPDR_PUPDR2_Pos                (4U)
3381 #define GPIO_PUPDR_PUPDR2_Msk                (0x3U << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000030 */
3382 #define GPIO_PUPDR_PUPDR2                    GPIO_PUPDR_PUPDR2_Msk
3383 #define GPIO_PUPDR_PUPDR2_0                  (0x1U << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000010 */
3384 #define GPIO_PUPDR_PUPDR2_1                  (0x2U << GPIO_PUPDR_PUPDR2_Pos)   /*!< 0x00000020 */
3385 
3386 #define GPIO_PUPDR_PUPDR3_Pos                (6U)
3387 #define GPIO_PUPDR_PUPDR3_Msk                (0x3U << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x000000C0 */
3388 #define GPIO_PUPDR_PUPDR3                    GPIO_PUPDR_PUPDR3_Msk
3389 #define GPIO_PUPDR_PUPDR3_0                  (0x1U << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000040 */
3390 #define GPIO_PUPDR_PUPDR3_1                  (0x2U << GPIO_PUPDR_PUPDR3_Pos)   /*!< 0x00000080 */
3391 
3392 #define GPIO_PUPDR_PUPDR4_Pos                (8U)
3393 #define GPIO_PUPDR_PUPDR4_Msk                (0x3U << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000300 */
3394 #define GPIO_PUPDR_PUPDR4                    GPIO_PUPDR_PUPDR4_Msk
3395 #define GPIO_PUPDR_PUPDR4_0                  (0x1U << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000100 */
3396 #define GPIO_PUPDR_PUPDR4_1                  (0x2U << GPIO_PUPDR_PUPDR4_Pos)   /*!< 0x00000200 */
3397 
3398 #define GPIO_PUPDR_PUPDR5_Pos                (10U)
3399 #define GPIO_PUPDR_PUPDR5_Msk                (0x3U << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000C00 */
3400 #define GPIO_PUPDR_PUPDR5                    GPIO_PUPDR_PUPDR5_Msk
3401 #define GPIO_PUPDR_PUPDR5_0                  (0x1U << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000400 */
3402 #define GPIO_PUPDR_PUPDR5_1                  (0x2U << GPIO_PUPDR_PUPDR5_Pos)   /*!< 0x00000800 */
3403 
3404 #define GPIO_PUPDR_PUPDR6_Pos                (12U)
3405 #define GPIO_PUPDR_PUPDR6_Msk                (0x3U << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00003000 */
3406 #define GPIO_PUPDR_PUPDR6                    GPIO_PUPDR_PUPDR6_Msk
3407 #define GPIO_PUPDR_PUPDR6_0                  (0x1U << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00001000 */
3408 #define GPIO_PUPDR_PUPDR6_1                  (0x2U << GPIO_PUPDR_PUPDR6_Pos)   /*!< 0x00002000 */
3409 
3410 #define GPIO_PUPDR_PUPDR7_Pos                (14U)
3411 #define GPIO_PUPDR_PUPDR7_Msk                (0x3U << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x0000C000 */
3412 #define GPIO_PUPDR_PUPDR7                    GPIO_PUPDR_PUPDR7_Msk
3413 #define GPIO_PUPDR_PUPDR7_0                  (0x1U << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00004000 */
3414 #define GPIO_PUPDR_PUPDR7_1                  (0x2U << GPIO_PUPDR_PUPDR7_Pos)   /*!< 0x00008000 */
3415 
3416 #define GPIO_PUPDR_PUPDR8_Pos                (16U)
3417 #define GPIO_PUPDR_PUPDR8_Msk                (0x3U << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00030000 */
3418 #define GPIO_PUPDR_PUPDR8                    GPIO_PUPDR_PUPDR8_Msk
3419 #define GPIO_PUPDR_PUPDR8_0                  (0x1U << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00010000 */
3420 #define GPIO_PUPDR_PUPDR8_1                  (0x2U << GPIO_PUPDR_PUPDR8_Pos)   /*!< 0x00020000 */
3421 
3422 #define GPIO_PUPDR_PUPDR9_Pos                (18U)
3423 #define GPIO_PUPDR_PUPDR9_Msk                (0x3U << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x000C0000 */
3424 #define GPIO_PUPDR_PUPDR9                    GPIO_PUPDR_PUPDR9_Msk
3425 #define GPIO_PUPDR_PUPDR9_0                  (0x1U << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00040000 */
3426 #define GPIO_PUPDR_PUPDR9_1                  (0x2U << GPIO_PUPDR_PUPDR9_Pos)   /*!< 0x00080000 */
3427 
3428 #define GPIO_PUPDR_PUPDR10_Pos               (20U)
3429 #define GPIO_PUPDR_PUPDR10_Msk               (0x3U << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00300000 */
3430 #define GPIO_PUPDR_PUPDR10                   GPIO_PUPDR_PUPDR10_Msk
3431 #define GPIO_PUPDR_PUPDR10_0                 (0x1U << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00100000 */
3432 #define GPIO_PUPDR_PUPDR10_1                 (0x2U << GPIO_PUPDR_PUPDR10_Pos)  /*!< 0x00200000 */
3433 
3434 #define GPIO_PUPDR_PUPDR11_Pos               (22U)
3435 #define GPIO_PUPDR_PUPDR11_Msk               (0x3U << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00C00000 */
3436 #define GPIO_PUPDR_PUPDR11                   GPIO_PUPDR_PUPDR11_Msk
3437 #define GPIO_PUPDR_PUPDR11_0                 (0x1U << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00400000 */
3438 #define GPIO_PUPDR_PUPDR11_1                 (0x2U << GPIO_PUPDR_PUPDR11_Pos)  /*!< 0x00800000 */
3439 
3440 #define GPIO_PUPDR_PUPDR12_Pos               (24U)
3441 #define GPIO_PUPDR_PUPDR12_Msk               (0x3U << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x03000000 */
3442 #define GPIO_PUPDR_PUPDR12                   GPIO_PUPDR_PUPDR12_Msk
3443 #define GPIO_PUPDR_PUPDR12_0                 (0x1U << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x01000000 */
3444 #define GPIO_PUPDR_PUPDR12_1                 (0x2U << GPIO_PUPDR_PUPDR12_Pos)  /*!< 0x02000000 */
3445 
3446 #define GPIO_PUPDR_PUPDR13_Pos               (26U)
3447 #define GPIO_PUPDR_PUPDR13_Msk               (0x3U << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x0C000000 */
3448 #define GPIO_PUPDR_PUPDR13                   GPIO_PUPDR_PUPDR13_Msk
3449 #define GPIO_PUPDR_PUPDR13_0                 (0x1U << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x04000000 */
3450 #define GPIO_PUPDR_PUPDR13_1                 (0x2U << GPIO_PUPDR_PUPDR13_Pos)  /*!< 0x08000000 */
3451 
3452 #define GPIO_PUPDR_PUPDR14_Pos               (28U)
3453 #define GPIO_PUPDR_PUPDR14_Msk               (0x3U << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x30000000 */
3454 #define GPIO_PUPDR_PUPDR14                   GPIO_PUPDR_PUPDR14_Msk
3455 #define GPIO_PUPDR_PUPDR14_0                 (0x1U << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x10000000 */
3456 #define GPIO_PUPDR_PUPDR14_1                 (0x2U << GPIO_PUPDR_PUPDR14_Pos)  /*!< 0x20000000 */
3457 #define GPIO_PUPDR_PUPDR15_Pos               (30U)
3458 #define GPIO_PUPDR_PUPDR15_Msk               (0x3U << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0xC0000000 */
3459 #define GPIO_PUPDR_PUPDR15                   GPIO_PUPDR_PUPDR15_Msk
3460 #define GPIO_PUPDR_PUPDR15_0                 (0x1U << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x40000000 */
3461 #define GPIO_PUPDR_PUPDR15_1                 (0x2U << GPIO_PUPDR_PUPDR15_Pos)  /*!< 0x80000000 */
3462 
3463 /******************  Bits definition for GPIO_IDR register  *******************/
3464 #define GPIO_IDR_IDR_0                       (0x00000001U)
3465 #define GPIO_IDR_IDR_1                       (0x00000002U)
3466 #define GPIO_IDR_IDR_2                       (0x00000004U)
3467 #define GPIO_IDR_IDR_3                       (0x00000008U)
3468 #define GPIO_IDR_IDR_4                       (0x00000010U)
3469 #define GPIO_IDR_IDR_5                       (0x00000020U)
3470 #define GPIO_IDR_IDR_6                       (0x00000040U)
3471 #define GPIO_IDR_IDR_7                       (0x00000080U)
3472 #define GPIO_IDR_IDR_8                       (0x00000100U)
3473 #define GPIO_IDR_IDR_9                       (0x00000200U)
3474 #define GPIO_IDR_IDR_10                      (0x00000400U)
3475 #define GPIO_IDR_IDR_11                      (0x00000800U)
3476 #define GPIO_IDR_IDR_12                      (0x00001000U)
3477 #define GPIO_IDR_IDR_13                      (0x00002000U)
3478 #define GPIO_IDR_IDR_14                      (0x00004000U)
3479 #define GPIO_IDR_IDR_15                      (0x00008000U)
3480 
3481 /******************  Bits definition for GPIO_ODR register  *******************/
3482 #define GPIO_ODR_ODR_0                       (0x00000001U)
3483 #define GPIO_ODR_ODR_1                       (0x00000002U)
3484 #define GPIO_ODR_ODR_2                       (0x00000004U)
3485 #define GPIO_ODR_ODR_3                       (0x00000008U)
3486 #define GPIO_ODR_ODR_4                       (0x00000010U)
3487 #define GPIO_ODR_ODR_5                       (0x00000020U)
3488 #define GPIO_ODR_ODR_6                       (0x00000040U)
3489 #define GPIO_ODR_ODR_7                       (0x00000080U)
3490 #define GPIO_ODR_ODR_8                       (0x00000100U)
3491 #define GPIO_ODR_ODR_9                       (0x00000200U)
3492 #define GPIO_ODR_ODR_10                      (0x00000400U)
3493 #define GPIO_ODR_ODR_11                      (0x00000800U)
3494 #define GPIO_ODR_ODR_12                      (0x00001000U)
3495 #define GPIO_ODR_ODR_13                      (0x00002000U)
3496 #define GPIO_ODR_ODR_14                      (0x00004000U)
3497 #define GPIO_ODR_ODR_15                      (0x00008000U)
3498 
3499 /******************  Bits definition for GPIO_BSRR register  ******************/
3500 #define GPIO_BSRR_BS_0                       (0x00000001U)
3501 #define GPIO_BSRR_BS_1                       (0x00000002U)
3502 #define GPIO_BSRR_BS_2                       (0x00000004U)
3503 #define GPIO_BSRR_BS_3                       (0x00000008U)
3504 #define GPIO_BSRR_BS_4                       (0x00000010U)
3505 #define GPIO_BSRR_BS_5                       (0x00000020U)
3506 #define GPIO_BSRR_BS_6                       (0x00000040U)
3507 #define GPIO_BSRR_BS_7                       (0x00000080U)
3508 #define GPIO_BSRR_BS_8                       (0x00000100U)
3509 #define GPIO_BSRR_BS_9                       (0x00000200U)
3510 #define GPIO_BSRR_BS_10                      (0x00000400U)
3511 #define GPIO_BSRR_BS_11                      (0x00000800U)
3512 #define GPIO_BSRR_BS_12                      (0x00001000U)
3513 #define GPIO_BSRR_BS_13                      (0x00002000U)
3514 #define GPIO_BSRR_BS_14                      (0x00004000U)
3515 #define GPIO_BSRR_BS_15                      (0x00008000U)
3516 #define GPIO_BSRR_BR_0                       (0x00010000U)
3517 #define GPIO_BSRR_BR_1                       (0x00020000U)
3518 #define GPIO_BSRR_BR_2                       (0x00040000U)
3519 #define GPIO_BSRR_BR_3                       (0x00080000U)
3520 #define GPIO_BSRR_BR_4                       (0x00100000U)
3521 #define GPIO_BSRR_BR_5                       (0x00200000U)
3522 #define GPIO_BSRR_BR_6                       (0x00400000U)
3523 #define GPIO_BSRR_BR_7                       (0x00800000U)
3524 #define GPIO_BSRR_BR_8                       (0x01000000U)
3525 #define GPIO_BSRR_BR_9                       (0x02000000U)
3526 #define GPIO_BSRR_BR_10                      (0x04000000U)
3527 #define GPIO_BSRR_BR_11                      (0x08000000U)
3528 #define GPIO_BSRR_BR_12                      (0x10000000U)
3529 #define GPIO_BSRR_BR_13                      (0x20000000U)
3530 #define GPIO_BSRR_BR_14                      (0x40000000U)
3531 #define GPIO_BSRR_BR_15                      (0x80000000U)
3532 
3533 /****************** Bit definition for GPIO_LCKR register  ********************/
3534 #define GPIO_LCKR_LCK0_Pos                   (0U)
3535 #define GPIO_LCKR_LCK0_Msk                   (0x1U << GPIO_LCKR_LCK0_Pos)      /*!< 0x00000001 */
3536 #define GPIO_LCKR_LCK0                       GPIO_LCKR_LCK0_Msk
3537 #define GPIO_LCKR_LCK1_Pos                   (1U)
3538 #define GPIO_LCKR_LCK1_Msk                   (0x1U << GPIO_LCKR_LCK1_Pos)      /*!< 0x00000002 */
3539 #define GPIO_LCKR_LCK1                       GPIO_LCKR_LCK1_Msk
3540 #define GPIO_LCKR_LCK2_Pos                   (2U)
3541 #define GPIO_LCKR_LCK2_Msk                   (0x1U << GPIO_LCKR_LCK2_Pos)      /*!< 0x00000004 */
3542 #define GPIO_LCKR_LCK2                       GPIO_LCKR_LCK2_Msk
3543 #define GPIO_LCKR_LCK3_Pos                   (3U)
3544 #define GPIO_LCKR_LCK3_Msk                   (0x1U << GPIO_LCKR_LCK3_Pos)      /*!< 0x00000008 */
3545 #define GPIO_LCKR_LCK3                       GPIO_LCKR_LCK3_Msk
3546 #define GPIO_LCKR_LCK4_Pos                   (4U)
3547 #define GPIO_LCKR_LCK4_Msk                   (0x1U << GPIO_LCKR_LCK4_Pos)      /*!< 0x00000010 */
3548 #define GPIO_LCKR_LCK4                       GPIO_LCKR_LCK4_Msk
3549 #define GPIO_LCKR_LCK5_Pos                   (5U)
3550 #define GPIO_LCKR_LCK5_Msk                   (0x1U << GPIO_LCKR_LCK5_Pos)      /*!< 0x00000020 */
3551 #define GPIO_LCKR_LCK5                       GPIO_LCKR_LCK5_Msk
3552 #define GPIO_LCKR_LCK6_Pos                   (6U)
3553 #define GPIO_LCKR_LCK6_Msk                   (0x1U << GPIO_LCKR_LCK6_Pos)      /*!< 0x00000040 */
3554 #define GPIO_LCKR_LCK6                       GPIO_LCKR_LCK6_Msk
3555 #define GPIO_LCKR_LCK7_Pos                   (7U)
3556 #define GPIO_LCKR_LCK7_Msk                   (0x1U << GPIO_LCKR_LCK7_Pos)      /*!< 0x00000080 */
3557 #define GPIO_LCKR_LCK7                       GPIO_LCKR_LCK7_Msk
3558 #define GPIO_LCKR_LCK8_Pos                   (8U)
3559 #define GPIO_LCKR_LCK8_Msk                   (0x1U << GPIO_LCKR_LCK8_Pos)      /*!< 0x00000100 */
3560 #define GPIO_LCKR_LCK8                       GPIO_LCKR_LCK8_Msk
3561 #define GPIO_LCKR_LCK9_Pos                   (9U)
3562 #define GPIO_LCKR_LCK9_Msk                   (0x1U << GPIO_LCKR_LCK9_Pos)      /*!< 0x00000200 */
3563 #define GPIO_LCKR_LCK9                       GPIO_LCKR_LCK9_Msk
3564 #define GPIO_LCKR_LCK10_Pos                  (10U)
3565 #define GPIO_LCKR_LCK10_Msk                  (0x1U << GPIO_LCKR_LCK10_Pos)     /*!< 0x00000400 */
3566 #define GPIO_LCKR_LCK10                      GPIO_LCKR_LCK10_Msk
3567 #define GPIO_LCKR_LCK11_Pos                  (11U)
3568 #define GPIO_LCKR_LCK11_Msk                  (0x1U << GPIO_LCKR_LCK11_Pos)     /*!< 0x00000800 */
3569 #define GPIO_LCKR_LCK11                      GPIO_LCKR_LCK11_Msk
3570 #define GPIO_LCKR_LCK12_Pos                  (12U)
3571 #define GPIO_LCKR_LCK12_Msk                  (0x1U << GPIO_LCKR_LCK12_Pos)     /*!< 0x00001000 */
3572 #define GPIO_LCKR_LCK12                      GPIO_LCKR_LCK12_Msk
3573 #define GPIO_LCKR_LCK13_Pos                  (13U)
3574 #define GPIO_LCKR_LCK13_Msk                  (0x1U << GPIO_LCKR_LCK13_Pos)     /*!< 0x00002000 */
3575 #define GPIO_LCKR_LCK13                      GPIO_LCKR_LCK13_Msk
3576 #define GPIO_LCKR_LCK14_Pos                  (14U)
3577 #define GPIO_LCKR_LCK14_Msk                  (0x1U << GPIO_LCKR_LCK14_Pos)     /*!< 0x00004000 */
3578 #define GPIO_LCKR_LCK14                      GPIO_LCKR_LCK14_Msk
3579 #define GPIO_LCKR_LCK15_Pos                  (15U)
3580 #define GPIO_LCKR_LCK15_Msk                  (0x1U << GPIO_LCKR_LCK15_Pos)     /*!< 0x00008000 */
3581 #define GPIO_LCKR_LCK15                      GPIO_LCKR_LCK15_Msk
3582 #define GPIO_LCKR_LCKK_Pos                   (16U)
3583 #define GPIO_LCKR_LCKK_Msk                   (0x1U << GPIO_LCKR_LCKK_Pos)      /*!< 0x00010000 */
3584 #define GPIO_LCKR_LCKK                       GPIO_LCKR_LCKK_Msk
3585 
3586 /****************** Bit definition for GPIO_AFRL register  ********************/
3587 #define GPIO_AFRL_AFSEL0_Pos                  (0U)
3588 #define GPIO_AFRL_AFSEL0_Msk                  (0xFU << GPIO_AFRL_AFSEL0_Pos)     /*!< 0x0000000F */
3589 #define GPIO_AFRL_AFSEL0                      GPIO_AFRL_AFSEL0_Msk
3590 #define GPIO_AFRL_AFSEL1_Pos                  (4U)
3591 #define GPIO_AFRL_AFSEL1_Msk                  (0xFU << GPIO_AFRL_AFSEL1_Pos)     /*!< 0x000000F0 */
3592 #define GPIO_AFRL_AFSEL1                      GPIO_AFRL_AFSEL1_Msk
3593 #define GPIO_AFRL_AFSEL2_Pos                  (8U)
3594 #define GPIO_AFRL_AFSEL2_Msk                  (0xFU << GPIO_AFRL_AFSEL2_Pos)     /*!< 0x00000F00 */
3595 #define GPIO_AFRL_AFSEL2                      GPIO_AFRL_AFSEL2_Msk
3596 #define GPIO_AFRL_AFSEL3_Pos                  (12U)
3597 #define GPIO_AFRL_AFSEL3_Msk                  (0xFU << GPIO_AFRL_AFSEL3_Pos)     /*!< 0x0000F000 */
3598 #define GPIO_AFRL_AFSEL3                      GPIO_AFRL_AFSEL3_Msk
3599 #define GPIO_AFRL_AFSEL4_Pos                  (16U)
3600 #define GPIO_AFRL_AFSEL4_Msk                  (0xFU << GPIO_AFRL_AFSEL4_Pos)     /*!< 0x000F0000 */
3601 #define GPIO_AFRL_AFSEL4                      GPIO_AFRL_AFSEL4_Msk
3602 #define GPIO_AFRL_AFSEL5_Pos                  (20U)
3603 #define GPIO_AFRL_AFSEL5_Msk                  (0xFU << GPIO_AFRL_AFSEL5_Pos)     /*!< 0x00F00000 */
3604 #define GPIO_AFRL_AFSEL5                      GPIO_AFRL_AFSEL5_Msk
3605 #define GPIO_AFRL_AFSEL6_Pos                  (24U)
3606 #define GPIO_AFRL_AFSEL6_Msk                  (0xFU << GPIO_AFRL_AFSEL6_Pos)     /*!< 0x0F000000 */
3607 #define GPIO_AFRL_AFSEL6                      GPIO_AFRL_AFSEL6_Msk
3608 #define GPIO_AFRL_AFSEL7_Pos                  (28U)
3609 #define GPIO_AFRL_AFSEL7_Msk                  (0xFU << GPIO_AFRL_AFSEL7_Pos)     /*!< 0xF0000000 */
3610 #define GPIO_AFRL_AFSEL7                      GPIO_AFRL_AFSEL7_Msk
3611 
3612 /****************** Bit definition for GPIO_AFRH register  ********************/
3613 #define GPIO_AFRH_AFSEL8_Pos                  (0U)
3614 #define GPIO_AFRH_AFSEL8_Msk                  (0xFU << GPIO_AFRH_AFSEL8_Pos)     /*!< 0x0000000F */
3615 #define GPIO_AFRH_AFSEL8                      GPIO_AFRH_AFSEL8_Msk
3616 #define GPIO_AFRH_AFSEL9_Pos                  (4U)
3617 #define GPIO_AFRH_AFSEL9_Msk                  (0xFU << GPIO_AFRH_AFSEL9_Pos)     /*!< 0x000000F0 */
3618 #define GPIO_AFRH_AFSEL9                      GPIO_AFRH_AFSEL9_Msk
3619 #define GPIO_AFRH_AFSEL10_Pos                  (8U)
3620 #define GPIO_AFRH_AFSEL10_Msk                  (0xFU << GPIO_AFRH_AFSEL10_Pos)     /*!< 0x00000F00 */
3621 #define GPIO_AFRH_AFSEL10                      GPIO_AFRH_AFSEL10_Msk
3622 #define GPIO_AFRH_AFSEL11_Pos                  (12U)
3623 #define GPIO_AFRH_AFSEL11_Msk                  (0xFU << GPIO_AFRH_AFSEL11_Pos)     /*!< 0x0000F000 */
3624 #define GPIO_AFRH_AFSEL11                      GPIO_AFRH_AFSEL11_Msk
3625 #define GPIO_AFRH_AFSEL12_Pos                  (16U)
3626 #define GPIO_AFRH_AFSEL12_Msk                  (0xFU << GPIO_AFRH_AFSEL12_Pos)     /*!< 0x000F0000 */
3627 #define GPIO_AFRH_AFSEL12                      GPIO_AFRH_AFSEL12_Msk
3628 #define GPIO_AFRH_AFSEL13_Pos                  (20U)
3629 #define GPIO_AFRH_AFSEL13_Msk                  (0xFU << GPIO_AFRH_AFSEL13_Pos)     /*!< 0x00F00000 */
3630 #define GPIO_AFRH_AFSEL13                      GPIO_AFRH_AFSEL13_Msk
3631 #define GPIO_AFRH_AFSEL14_Pos                  (24U)
3632 #define GPIO_AFRH_AFSEL14_Msk                  (0xFU << GPIO_AFRH_AFSEL14_Pos)     /*!< 0x0F000000 */
3633 #define GPIO_AFRH_AFSEL14                      GPIO_AFRH_AFSEL14_Msk
3634 #define GPIO_AFRH_AFSEL15_Pos                  (28U)
3635 #define GPIO_AFRH_AFSEL15_Msk                  (0xFU << GPIO_AFRH_AFSEL15_Pos)     /*!< 0xF0000000 */
3636 #define GPIO_AFRH_AFSEL15                      GPIO_AFRH_AFSEL15_Msk
3637 
3638 /****************** Bit definition for GPIO_BRR register  *********************/
3639 #define GPIO_BRR_BR_0                        (0x00000001U)
3640 #define GPIO_BRR_BR_1                        (0x00000002U)
3641 #define GPIO_BRR_BR_2                        (0x00000004U)
3642 #define GPIO_BRR_BR_3                        (0x00000008U)
3643 #define GPIO_BRR_BR_4                        (0x00000010U)
3644 #define GPIO_BRR_BR_5                        (0x00000020U)
3645 #define GPIO_BRR_BR_6                        (0x00000040U)
3646 #define GPIO_BRR_BR_7                        (0x00000080U)
3647 #define GPIO_BRR_BR_8                        (0x00000100U)
3648 #define GPIO_BRR_BR_9                        (0x00000200U)
3649 #define GPIO_BRR_BR_10                       (0x00000400U)
3650 #define GPIO_BRR_BR_11                       (0x00000800U)
3651 #define GPIO_BRR_BR_12                       (0x00001000U)
3652 #define GPIO_BRR_BR_13                       (0x00002000U)
3653 #define GPIO_BRR_BR_14                       (0x00004000U)
3654 #define GPIO_BRR_BR_15                       (0x00008000U)
3655 
3656 /******************************************************************************/
3657 /*                                                                            */
3658 /*                   Inter-integrated Circuit Interface (I2C)                 */
3659 /*                                                                            */
3660 /******************************************************************************/
3661 
3662 /*******************  Bit definition for I2C_CR1 register  ********************/
3663 #define I2C_CR1_PE_Pos                      (0U)
3664 #define I2C_CR1_PE_Msk                      (0x1U << I2C_CR1_PE_Pos)           /*!< 0x00000001 */
3665 #define I2C_CR1_PE                          I2C_CR1_PE_Msk                     /*!< Peripheral Enable */
3666 #define I2C_CR1_SMBUS_Pos                   (1U)
3667 #define I2C_CR1_SMBUS_Msk                   (0x1U << I2C_CR1_SMBUS_Pos)        /*!< 0x00000002 */
3668 #define I2C_CR1_SMBUS                       I2C_CR1_SMBUS_Msk                  /*!< SMBus Mode */
3669 #define I2C_CR1_SMBTYPE_Pos                 (3U)
3670 #define I2C_CR1_SMBTYPE_Msk                 (0x1U << I2C_CR1_SMBTYPE_Pos)      /*!< 0x00000008 */
3671 #define I2C_CR1_SMBTYPE                     I2C_CR1_SMBTYPE_Msk                /*!< SMBus Type */
3672 #define I2C_CR1_ENARP_Pos                   (4U)
3673 #define I2C_CR1_ENARP_Msk                   (0x1U << I2C_CR1_ENARP_Pos)        /*!< 0x00000010 */
3674 #define I2C_CR1_ENARP                       I2C_CR1_ENARP_Msk                  /*!< ARP Enable */
3675 #define I2C_CR1_ENPEC_Pos                   (5U)
3676 #define I2C_CR1_ENPEC_Msk                   (0x1U << I2C_CR1_ENPEC_Pos)        /*!< 0x00000020 */
3677 #define I2C_CR1_ENPEC                       I2C_CR1_ENPEC_Msk                  /*!< PEC Enable */
3678 #define I2C_CR1_ENGC_Pos                    (6U)
3679 #define I2C_CR1_ENGC_Msk                    (0x1U << I2C_CR1_ENGC_Pos)         /*!< 0x00000040 */
3680 #define I2C_CR1_ENGC                        I2C_CR1_ENGC_Msk                   /*!< General Call Enable */
3681 #define I2C_CR1_NOSTRETCH_Pos               (7U)
3682 #define I2C_CR1_NOSTRETCH_Msk               (0x1U << I2C_CR1_NOSTRETCH_Pos)    /*!< 0x00000080 */
3683 #define I2C_CR1_NOSTRETCH                   I2C_CR1_NOSTRETCH_Msk              /*!< Clock Stretching Disable (Slave mode) */
3684 #define I2C_CR1_START_Pos                   (8U)
3685 #define I2C_CR1_START_Msk                   (0x1U << I2C_CR1_START_Pos)        /*!< 0x00000100 */
3686 #define I2C_CR1_START                       I2C_CR1_START_Msk                  /*!< Start Generation */
3687 #define I2C_CR1_STOP_Pos                    (9U)
3688 #define I2C_CR1_STOP_Msk                    (0x1U << I2C_CR1_STOP_Pos)         /*!< 0x00000200 */
3689 #define I2C_CR1_STOP                        I2C_CR1_STOP_Msk                   /*!< Stop Generation */
3690 #define I2C_CR1_ACK_Pos                     (10U)
3691 #define I2C_CR1_ACK_Msk                     (0x1U << I2C_CR1_ACK_Pos)          /*!< 0x00000400 */
3692 #define I2C_CR1_ACK                         I2C_CR1_ACK_Msk                    /*!< Acknowledge Enable */
3693 #define I2C_CR1_POS_Pos                     (11U)
3694 #define I2C_CR1_POS_Msk                     (0x1U << I2C_CR1_POS_Pos)          /*!< 0x00000800 */
3695 #define I2C_CR1_POS                         I2C_CR1_POS_Msk                    /*!< Acknowledge/PEC Position (for data reception) */
3696 #define I2C_CR1_PEC_Pos                     (12U)
3697 #define I2C_CR1_PEC_Msk                     (0x1U << I2C_CR1_PEC_Pos)          /*!< 0x00001000 */
3698 #define I2C_CR1_PEC                         I2C_CR1_PEC_Msk                    /*!< Packet Error Checking */
3699 #define I2C_CR1_ALERT_Pos                   (13U)
3700 #define I2C_CR1_ALERT_Msk                   (0x1U << I2C_CR1_ALERT_Pos)        /*!< 0x00002000 */
3701 #define I2C_CR1_ALERT                       I2C_CR1_ALERT_Msk                  /*!< SMBus Alert */
3702 #define I2C_CR1_SWRST_Pos                   (15U)
3703 #define I2C_CR1_SWRST_Msk                   (0x1U << I2C_CR1_SWRST_Pos)        /*!< 0x00008000 */
3704 #define I2C_CR1_SWRST                       I2C_CR1_SWRST_Msk                  /*!< Software Reset */
3705 
3706 /*******************  Bit definition for I2C_CR2 register  ********************/
3707 #define I2C_CR2_FREQ_Pos                    (0U)
3708 #define I2C_CR2_FREQ_Msk                    (0x3FU << I2C_CR2_FREQ_Pos)        /*!< 0x0000003F */
3709 #define I2C_CR2_FREQ                        I2C_CR2_FREQ_Msk                   /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
3710 #define I2C_CR2_FREQ_0                      (0x01U << I2C_CR2_FREQ_Pos)        /*!< 0x00000001 */
3711 #define I2C_CR2_FREQ_1                      (0x02U << I2C_CR2_FREQ_Pos)        /*!< 0x00000002 */
3712 #define I2C_CR2_FREQ_2                      (0x04U << I2C_CR2_FREQ_Pos)        /*!< 0x00000004 */
3713 #define I2C_CR2_FREQ_3                      (0x08U << I2C_CR2_FREQ_Pos)        /*!< 0x00000008 */
3714 #define I2C_CR2_FREQ_4                      (0x10U << I2C_CR2_FREQ_Pos)        /*!< 0x00000010 */
3715 #define I2C_CR2_FREQ_5                      (0x20U << I2C_CR2_FREQ_Pos)        /*!< 0x00000020 */
3716 
3717 #define I2C_CR2_ITERREN_Pos                 (8U)
3718 #define I2C_CR2_ITERREN_Msk                 (0x1U << I2C_CR2_ITERREN_Pos)      /*!< 0x00000100 */
3719 #define I2C_CR2_ITERREN                     I2C_CR2_ITERREN_Msk                /*!< Error Interrupt Enable */
3720 #define I2C_CR2_ITEVTEN_Pos                 (9U)
3721 #define I2C_CR2_ITEVTEN_Msk                 (0x1U << I2C_CR2_ITEVTEN_Pos)      /*!< 0x00000200 */
3722 #define I2C_CR2_ITEVTEN                     I2C_CR2_ITEVTEN_Msk                /*!< Event Interrupt Enable */
3723 #define I2C_CR2_ITBUFEN_Pos                 (10U)
3724 #define I2C_CR2_ITBUFEN_Msk                 (0x1U << I2C_CR2_ITBUFEN_Pos)      /*!< 0x00000400 */
3725 #define I2C_CR2_ITBUFEN                     I2C_CR2_ITBUFEN_Msk                /*!< Buffer Interrupt Enable */
3726 #define I2C_CR2_DMAEN_Pos                   (11U)
3727 #define I2C_CR2_DMAEN_Msk                   (0x1U << I2C_CR2_DMAEN_Pos)        /*!< 0x00000800 */
3728 #define I2C_CR2_DMAEN                       I2C_CR2_DMAEN_Msk                  /*!< DMA Requests Enable */
3729 #define I2C_CR2_LAST_Pos                    (12U)
3730 #define I2C_CR2_LAST_Msk                    (0x1U << I2C_CR2_LAST_Pos)         /*!< 0x00001000 */
3731 #define I2C_CR2_LAST                        I2C_CR2_LAST_Msk                   /*!< DMA Last Transfer */
3732 
3733 /*******************  Bit definition for I2C_OAR1 register  *******************/
3734 #define I2C_OAR1_ADD1_7                     (0x000000FEU)                      /*!< Interface Address */
3735 #define I2C_OAR1_ADD8_9                     (0x00000300U)                      /*!< Interface Address */
3736 
3737 #define I2C_OAR1_ADD0_Pos                   (0U)
3738 #define I2C_OAR1_ADD0_Msk                   (0x1U << I2C_OAR1_ADD0_Pos)        /*!< 0x00000001 */
3739 #define I2C_OAR1_ADD0                       I2C_OAR1_ADD0_Msk                  /*!< Bit 0 */
3740 #define I2C_OAR1_ADD1_Pos                   (1U)
3741 #define I2C_OAR1_ADD1_Msk                   (0x1U << I2C_OAR1_ADD1_Pos)        /*!< 0x00000002 */
3742 #define I2C_OAR1_ADD1                       I2C_OAR1_ADD1_Msk                  /*!< Bit 1 */
3743 #define I2C_OAR1_ADD2_Pos                   (2U)
3744 #define I2C_OAR1_ADD2_Msk                   (0x1U << I2C_OAR1_ADD2_Pos)        /*!< 0x00000004 */
3745 #define I2C_OAR1_ADD2                       I2C_OAR1_ADD2_Msk                  /*!< Bit 2 */
3746 #define I2C_OAR1_ADD3_Pos                   (3U)
3747 #define I2C_OAR1_ADD3_Msk                   (0x1U << I2C_OAR1_ADD3_Pos)        /*!< 0x00000008 */
3748 #define I2C_OAR1_ADD3                       I2C_OAR1_ADD3_Msk                  /*!< Bit 3 */
3749 #define I2C_OAR1_ADD4_Pos                   (4U)
3750 #define I2C_OAR1_ADD4_Msk                   (0x1U << I2C_OAR1_ADD4_Pos)        /*!< 0x00000010 */
3751 #define I2C_OAR1_ADD4                       I2C_OAR1_ADD4_Msk                  /*!< Bit 4 */
3752 #define I2C_OAR1_ADD5_Pos                   (5U)
3753 #define I2C_OAR1_ADD5_Msk                   (0x1U << I2C_OAR1_ADD5_Pos)        /*!< 0x00000020 */
3754 #define I2C_OAR1_ADD5                       I2C_OAR1_ADD5_Msk                  /*!< Bit 5 */
3755 #define I2C_OAR1_ADD6_Pos                   (6U)
3756 #define I2C_OAR1_ADD6_Msk                   (0x1U << I2C_OAR1_ADD6_Pos)        /*!< 0x00000040 */
3757 #define I2C_OAR1_ADD6                       I2C_OAR1_ADD6_Msk                  /*!< Bit 6 */
3758 #define I2C_OAR1_ADD7_Pos                   (7U)
3759 #define I2C_OAR1_ADD7_Msk                   (0x1U << I2C_OAR1_ADD7_Pos)        /*!< 0x00000080 */
3760 #define I2C_OAR1_ADD7                       I2C_OAR1_ADD7_Msk                  /*!< Bit 7 */
3761 #define I2C_OAR1_ADD8_Pos                   (8U)
3762 #define I2C_OAR1_ADD8_Msk                   (0x1U << I2C_OAR1_ADD8_Pos)        /*!< 0x00000100 */
3763 #define I2C_OAR1_ADD8                       I2C_OAR1_ADD8_Msk                  /*!< Bit 8 */
3764 #define I2C_OAR1_ADD9_Pos                   (9U)
3765 #define I2C_OAR1_ADD9_Msk                   (0x1U << I2C_OAR1_ADD9_Pos)        /*!< 0x00000200 */
3766 #define I2C_OAR1_ADD9                       I2C_OAR1_ADD9_Msk                  /*!< Bit 9 */
3767 
3768 #define I2C_OAR1_ADDMODE_Pos                (15U)
3769 #define I2C_OAR1_ADDMODE_Msk                (0x1U << I2C_OAR1_ADDMODE_Pos)     /*!< 0x00008000 */
3770 #define I2C_OAR1_ADDMODE                    I2C_OAR1_ADDMODE_Msk               /*!< Addressing Mode (Slave mode) */
3771 
3772 /*******************  Bit definition for I2C_OAR2 register  *******************/
3773 #define I2C_OAR2_ENDUAL_Pos                 (0U)
3774 #define I2C_OAR2_ENDUAL_Msk                 (0x1U << I2C_OAR2_ENDUAL_Pos)      /*!< 0x00000001 */
3775 #define I2C_OAR2_ENDUAL                     I2C_OAR2_ENDUAL_Msk                /*!< Dual addressing mode enable */
3776 #define I2C_OAR2_ADD2_Pos                   (1U)
3777 #define I2C_OAR2_ADD2_Msk                   (0x7FU << I2C_OAR2_ADD2_Pos)       /*!< 0x000000FE */
3778 #define I2C_OAR2_ADD2                       I2C_OAR2_ADD2_Msk                  /*!< Interface address */
3779 
3780 /********************  Bit definition for I2C_DR register  ********************/
3781 #define I2C_DR_DR_Pos                       (0U)
3782 #define I2C_DR_DR_Msk                       (0xFFU << I2C_DR_DR_Pos)           /*!< 0x000000FF */
3783 #define I2C_DR_DR                           I2C_DR_DR_Msk                      /*!< 8-bit Data Register */
3784 
3785 /*******************  Bit definition for I2C_SR1 register  ********************/
3786 #define I2C_SR1_SB_Pos                      (0U)
3787 #define I2C_SR1_SB_Msk                      (0x1U << I2C_SR1_SB_Pos)           /*!< 0x00000001 */
3788 #define I2C_SR1_SB                          I2C_SR1_SB_Msk                     /*!< Start Bit (Master mode) */
3789 #define I2C_SR1_ADDR_Pos                    (1U)
3790 #define I2C_SR1_ADDR_Msk                    (0x1U << I2C_SR1_ADDR_Pos)         /*!< 0x00000002 */
3791 #define I2C_SR1_ADDR                        I2C_SR1_ADDR_Msk                   /*!< Address sent (master mode)/matched (slave mode) */
3792 #define I2C_SR1_BTF_Pos                     (2U)
3793 #define I2C_SR1_BTF_Msk                     (0x1U << I2C_SR1_BTF_Pos)          /*!< 0x00000004 */
3794 #define I2C_SR1_BTF                         I2C_SR1_BTF_Msk                    /*!< Byte Transfer Finished */
3795 #define I2C_SR1_ADD10_Pos                   (3U)
3796 #define I2C_SR1_ADD10_Msk                   (0x1U << I2C_SR1_ADD10_Pos)        /*!< 0x00000008 */
3797 #define I2C_SR1_ADD10                       I2C_SR1_ADD10_Msk                  /*!< 10-bit header sent (Master mode) */
3798 #define I2C_SR1_STOPF_Pos                   (4U)
3799 #define I2C_SR1_STOPF_Msk                   (0x1U << I2C_SR1_STOPF_Pos)        /*!< 0x00000010 */
3800 #define I2C_SR1_STOPF                       I2C_SR1_STOPF_Msk                  /*!< Stop detection (Slave mode) */
3801 #define I2C_SR1_RXNE_Pos                    (6U)
3802 #define I2C_SR1_RXNE_Msk                    (0x1U << I2C_SR1_RXNE_Pos)         /*!< 0x00000040 */
3803 #define I2C_SR1_RXNE                        I2C_SR1_RXNE_Msk                   /*!< Data Register not Empty (receivers) */
3804 #define I2C_SR1_TXE_Pos                     (7U)
3805 #define I2C_SR1_TXE_Msk                     (0x1U << I2C_SR1_TXE_Pos)          /*!< 0x00000080 */
3806 #define I2C_SR1_TXE                         I2C_SR1_TXE_Msk                    /*!< Data Register Empty (transmitters) */
3807 #define I2C_SR1_BERR_Pos                    (8U)
3808 #define I2C_SR1_BERR_Msk                    (0x1U << I2C_SR1_BERR_Pos)         /*!< 0x00000100 */
3809 #define I2C_SR1_BERR                        I2C_SR1_BERR_Msk                   /*!< Bus Error */
3810 #define I2C_SR1_ARLO_Pos                    (9U)
3811 #define I2C_SR1_ARLO_Msk                    (0x1U << I2C_SR1_ARLO_Pos)         /*!< 0x00000200 */
3812 #define I2C_SR1_ARLO                        I2C_SR1_ARLO_Msk                   /*!< Arbitration Lost (master mode) */
3813 #define I2C_SR1_AF_Pos                      (10U)
3814 #define I2C_SR1_AF_Msk                      (0x1U << I2C_SR1_AF_Pos)           /*!< 0x00000400 */
3815 #define I2C_SR1_AF                          I2C_SR1_AF_Msk                     /*!< Acknowledge Failure */
3816 #define I2C_SR1_OVR_Pos                     (11U)
3817 #define I2C_SR1_OVR_Msk                     (0x1U << I2C_SR1_OVR_Pos)          /*!< 0x00000800 */
3818 #define I2C_SR1_OVR                         I2C_SR1_OVR_Msk                    /*!< Overrun/Underrun */
3819 #define I2C_SR1_PECERR_Pos                  (12U)
3820 #define I2C_SR1_PECERR_Msk                  (0x1U << I2C_SR1_PECERR_Pos)       /*!< 0x00001000 */
3821 #define I2C_SR1_PECERR                      I2C_SR1_PECERR_Msk                 /*!< PEC Error in reception */
3822 #define I2C_SR1_TIMEOUT_Pos                 (14U)
3823 #define I2C_SR1_TIMEOUT_Msk                 (0x1U << I2C_SR1_TIMEOUT_Pos)      /*!< 0x00004000 */
3824 #define I2C_SR1_TIMEOUT                     I2C_SR1_TIMEOUT_Msk                /*!< Timeout or Tlow Error */
3825 #define I2C_SR1_SMBALERT_Pos                (15U)
3826 #define I2C_SR1_SMBALERT_Msk                (0x1U << I2C_SR1_SMBALERT_Pos)     /*!< 0x00008000 */
3827 #define I2C_SR1_SMBALERT                    I2C_SR1_SMBALERT_Msk               /*!< SMBus Alert */
3828 
3829 /*******************  Bit definition for I2C_SR2 register  ********************/
3830 #define I2C_SR2_MSL_Pos                     (0U)
3831 #define I2C_SR2_MSL_Msk                     (0x1U << I2C_SR2_MSL_Pos)          /*!< 0x00000001 */
3832 #define I2C_SR2_MSL                         I2C_SR2_MSL_Msk                    /*!< Master/Slave */
3833 #define I2C_SR2_BUSY_Pos                    (1U)
3834 #define I2C_SR2_BUSY_Msk                    (0x1U << I2C_SR2_BUSY_Pos)         /*!< 0x00000002 */
3835 #define I2C_SR2_BUSY                        I2C_SR2_BUSY_Msk                   /*!< Bus Busy */
3836 #define I2C_SR2_TRA_Pos                     (2U)
3837 #define I2C_SR2_TRA_Msk                     (0x1U << I2C_SR2_TRA_Pos)          /*!< 0x00000004 */
3838 #define I2C_SR2_TRA                         I2C_SR2_TRA_Msk                    /*!< Transmitter/Receiver */
3839 #define I2C_SR2_GENCALL_Pos                 (4U)
3840 #define I2C_SR2_GENCALL_Msk                 (0x1U << I2C_SR2_GENCALL_Pos)      /*!< 0x00000010 */
3841 #define I2C_SR2_GENCALL                     I2C_SR2_GENCALL_Msk                /*!< General Call Address (Slave mode) */
3842 #define I2C_SR2_SMBDEFAULT_Pos              (5U)
3843 #define I2C_SR2_SMBDEFAULT_Msk              (0x1U << I2C_SR2_SMBDEFAULT_Pos)   /*!< 0x00000020 */
3844 #define I2C_SR2_SMBDEFAULT                  I2C_SR2_SMBDEFAULT_Msk             /*!< SMBus Device Default Address (Slave mode) */
3845 #define I2C_SR2_SMBHOST_Pos                 (6U)
3846 #define I2C_SR2_SMBHOST_Msk                 (0x1U << I2C_SR2_SMBHOST_Pos)      /*!< 0x00000040 */
3847 #define I2C_SR2_SMBHOST                     I2C_SR2_SMBHOST_Msk                /*!< SMBus Host Header (Slave mode) */
3848 #define I2C_SR2_DUALF_Pos                   (7U)
3849 #define I2C_SR2_DUALF_Msk                   (0x1U << I2C_SR2_DUALF_Pos)        /*!< 0x00000080 */
3850 #define I2C_SR2_DUALF                       I2C_SR2_DUALF_Msk                  /*!< Dual Flag (Slave mode) */
3851 #define I2C_SR2_PEC_Pos                     (8U)
3852 #define I2C_SR2_PEC_Msk                     (0xFFU << I2C_SR2_PEC_Pos)         /*!< 0x0000FF00 */
3853 #define I2C_SR2_PEC                         I2C_SR2_PEC_Msk                    /*!< Packet Error Checking Register */
3854 
3855 /*******************  Bit definition for I2C_CCR register  ********************/
3856 #define I2C_CCR_CCR_Pos                     (0U)
3857 #define I2C_CCR_CCR_Msk                     (0xFFFU << I2C_CCR_CCR_Pos)        /*!< 0x00000FFF */
3858 #define I2C_CCR_CCR                         I2C_CCR_CCR_Msk                    /*!< Clock Control Register in Fast/Standard mode (Master mode) */
3859 #define I2C_CCR_DUTY_Pos                    (14U)
3860 #define I2C_CCR_DUTY_Msk                    (0x1U << I2C_CCR_DUTY_Pos)         /*!< 0x00004000 */
3861 #define I2C_CCR_DUTY                        I2C_CCR_DUTY_Msk                   /*!< Fast Mode Duty Cycle */
3862 #define I2C_CCR_FS_Pos                      (15U)
3863 #define I2C_CCR_FS_Msk                      (0x1U << I2C_CCR_FS_Pos)           /*!< 0x00008000 */
3864 #define I2C_CCR_FS                          I2C_CCR_FS_Msk                     /*!< I2C Master Mode Selection */
3865 
3866 /******************  Bit definition for I2C_TRISE register  *******************/
3867 #define I2C_TRISE_TRISE_Pos                 (0U)
3868 #define I2C_TRISE_TRISE_Msk                 (0x3FU << I2C_TRISE_TRISE_Pos)     /*!< 0x0000003F */
3869 #define I2C_TRISE_TRISE                     I2C_TRISE_TRISE_Msk                /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
3870 
3871 /******************************************************************************/
3872 /*                                                                            */
3873 /*                        Independent WATCHDOG (IWDG)                         */
3874 /*                                                                            */
3875 /******************************************************************************/
3876 
3877 /*******************  Bit definition for IWDG_KR register  ********************/
3878 #define IWDG_KR_KEY_Pos                     (0U)
3879 #define IWDG_KR_KEY_Msk                     (0xFFFFU << IWDG_KR_KEY_Pos)       /*!< 0x0000FFFF */
3880 #define IWDG_KR_KEY                         IWDG_KR_KEY_Msk                    /*!< Key value (write only, read 0000h) */
3881 
3882 /*******************  Bit definition for IWDG_PR register  ********************/
3883 #define IWDG_PR_PR_Pos                      (0U)
3884 #define IWDG_PR_PR_Msk                      (0x7U << IWDG_PR_PR_Pos)           /*!< 0x00000007 */
3885 #define IWDG_PR_PR                          IWDG_PR_PR_Msk                     /*!< PR[2:0] (Prescaler divider) */
3886 #define IWDG_PR_PR_0                        (0x1U << IWDG_PR_PR_Pos)           /*!< 0x00000001 */
3887 #define IWDG_PR_PR_1                        (0x2U << IWDG_PR_PR_Pos)           /*!< 0x00000002 */
3888 #define IWDG_PR_PR_2                        (0x4U << IWDG_PR_PR_Pos)           /*!< 0x00000004 */
3889 
3890 /*******************  Bit definition for IWDG_RLR register  *******************/
3891 #define IWDG_RLR_RL_Pos                     (0U)
3892 #define IWDG_RLR_RL_Msk                     (0xFFFU << IWDG_RLR_RL_Pos)        /*!< 0x00000FFF */
3893 #define IWDG_RLR_RL                         IWDG_RLR_RL_Msk                    /*!< Watchdog counter reload value */
3894 
3895 /*******************  Bit definition for IWDG_SR register  ********************/
3896 #define IWDG_SR_PVU_Pos                     (0U)
3897 #define IWDG_SR_PVU_Msk                     (0x1U << IWDG_SR_PVU_Pos)          /*!< 0x00000001 */
3898 #define IWDG_SR_PVU                         IWDG_SR_PVU_Msk                    /*!< Watchdog prescaler value update */
3899 #define IWDG_SR_RVU_Pos                     (1U)
3900 #define IWDG_SR_RVU_Msk                     (0x1U << IWDG_SR_RVU_Pos)          /*!< 0x00000002 */
3901 #define IWDG_SR_RVU                         IWDG_SR_RVU_Msk                    /*!< Watchdog counter reload value update */
3902 
3903 /******************************************************************************/
3904 /*                                                                            */
3905 /*                          LCD Controller (LCD)                              */
3906 /*                                                                            */
3907 /******************************************************************************/
3908 
3909 /*******************  Bit definition for LCD_CR register  *********************/
3910 #define LCD_CR_LCDEN_Pos           (0U)
3911 #define LCD_CR_LCDEN_Msk           (0x1U << LCD_CR_LCDEN_Pos)                  /*!< 0x00000001 */
3912 #define LCD_CR_LCDEN               LCD_CR_LCDEN_Msk                            /*!< LCD Enable Bit */
3913 #define LCD_CR_VSEL_Pos            (1U)
3914 #define LCD_CR_VSEL_Msk            (0x1U << LCD_CR_VSEL_Pos)                   /*!< 0x00000002 */
3915 #define LCD_CR_VSEL                LCD_CR_VSEL_Msk                             /*!< Voltage source selector Bit */
3916 
3917 #define LCD_CR_DUTY_Pos            (2U)
3918 #define LCD_CR_DUTY_Msk            (0x7U << LCD_CR_DUTY_Pos)                   /*!< 0x0000001C */
3919 #define LCD_CR_DUTY                LCD_CR_DUTY_Msk                             /*!< DUTY[2:0] bits (Duty selector) */
3920 #define LCD_CR_DUTY_0              (0x1U << LCD_CR_DUTY_Pos)                   /*!< 0x00000004 */
3921 #define LCD_CR_DUTY_1              (0x2U << LCD_CR_DUTY_Pos)                   /*!< 0x00000008 */
3922 #define LCD_CR_DUTY_2              (0x4U << LCD_CR_DUTY_Pos)                   /*!< 0x00000010 */
3923 
3924 #define LCD_CR_BIAS_Pos            (5U)
3925 #define LCD_CR_BIAS_Msk            (0x3U << LCD_CR_BIAS_Pos)                   /*!< 0x00000060 */
3926 #define LCD_CR_BIAS                LCD_CR_BIAS_Msk                             /*!< BIAS[1:0] bits (Bias selector) */
3927 #define LCD_CR_BIAS_0              (0x1U << LCD_CR_BIAS_Pos)                   /*!< 0x00000020 */
3928 #define LCD_CR_BIAS_1              (0x2U << LCD_CR_BIAS_Pos)                   /*!< 0x00000040 */
3929 
3930 #define LCD_CR_MUX_SEG_Pos         (7U)
3931 #define LCD_CR_MUX_SEG_Msk         (0x1U << LCD_CR_MUX_SEG_Pos)                /*!< 0x00000080 */
3932 #define LCD_CR_MUX_SEG             LCD_CR_MUX_SEG_Msk                          /*!< Mux Segment Enable Bit */
3933 
3934 /*******************  Bit definition for LCD_FCR register  ********************/
3935 #define LCD_FCR_HD_Pos             (0U)
3936 #define LCD_FCR_HD_Msk             (0x1U << LCD_FCR_HD_Pos)                    /*!< 0x00000001 */
3937 #define LCD_FCR_HD                 LCD_FCR_HD_Msk                              /*!< High Drive Enable Bit */
3938 #define LCD_FCR_SOFIE_Pos          (1U)
3939 #define LCD_FCR_SOFIE_Msk          (0x1U << LCD_FCR_SOFIE_Pos)                 /*!< 0x00000002 */
3940 #define LCD_FCR_SOFIE              LCD_FCR_SOFIE_Msk                           /*!< Start of Frame Interrupt Enable Bit */
3941 #define LCD_FCR_UDDIE_Pos          (3U)
3942 #define LCD_FCR_UDDIE_Msk          (0x1U << LCD_FCR_UDDIE_Pos)                 /*!< 0x00000008 */
3943 #define LCD_FCR_UDDIE              LCD_FCR_UDDIE_Msk                           /*!< Update Display Done Interrupt Enable Bit */
3944 
3945 #define LCD_FCR_PON_Pos            (4U)
3946 #define LCD_FCR_PON_Msk            (0x7U << LCD_FCR_PON_Pos)                   /*!< 0x00000070 */
3947 #define LCD_FCR_PON                LCD_FCR_PON_Msk                             /*!< PON[2:0] bits (Puls ON Duration) */
3948 #define LCD_FCR_PON_0              (0x1U << LCD_FCR_PON_Pos)                   /*!< 0x00000010 */
3949 #define LCD_FCR_PON_1              (0x2U << LCD_FCR_PON_Pos)                   /*!< 0x00000020 */
3950 #define LCD_FCR_PON_2              (0x4U << LCD_FCR_PON_Pos)                   /*!< 0x00000040 */
3951 
3952 #define LCD_FCR_DEAD_Pos           (7U)
3953 #define LCD_FCR_DEAD_Msk           (0x7U << LCD_FCR_DEAD_Pos)                  /*!< 0x00000380 */
3954 #define LCD_FCR_DEAD               LCD_FCR_DEAD_Msk                            /*!< DEAD[2:0] bits (DEAD Time) */
3955 #define LCD_FCR_DEAD_0             (0x1U << LCD_FCR_DEAD_Pos)                  /*!< 0x00000080 */
3956 #define LCD_FCR_DEAD_1             (0x2U << LCD_FCR_DEAD_Pos)                  /*!< 0x00000100 */
3957 #define LCD_FCR_DEAD_2             (0x4U << LCD_FCR_DEAD_Pos)                  /*!< 0x00000200 */
3958 
3959 #define LCD_FCR_CC_Pos             (10U)
3960 #define LCD_FCR_CC_Msk             (0x7U << LCD_FCR_CC_Pos)                    /*!< 0x00001C00 */
3961 #define LCD_FCR_CC                 LCD_FCR_CC_Msk                              /*!< CC[2:0] bits (Contrast Control) */
3962 #define LCD_FCR_CC_0               (0x1U << LCD_FCR_CC_Pos)                    /*!< 0x00000400 */
3963 #define LCD_FCR_CC_1               (0x2U << LCD_FCR_CC_Pos)                    /*!< 0x00000800 */
3964 #define LCD_FCR_CC_2               (0x4U << LCD_FCR_CC_Pos)                    /*!< 0x00001000 */
3965 
3966 #define LCD_FCR_BLINKF_Pos         (13U)
3967 #define LCD_FCR_BLINKF_Msk         (0x7U << LCD_FCR_BLINKF_Pos)                /*!< 0x0000E000 */
3968 #define LCD_FCR_BLINKF             LCD_FCR_BLINKF_Msk                          /*!< BLINKF[2:0] bits (Blink Frequency) */
3969 #define LCD_FCR_BLINKF_0           (0x1U << LCD_FCR_BLINKF_Pos)                /*!< 0x00002000 */
3970 #define LCD_FCR_BLINKF_1           (0x2U << LCD_FCR_BLINKF_Pos)                /*!< 0x00004000 */
3971 #define LCD_FCR_BLINKF_2           (0x4U << LCD_FCR_BLINKF_Pos)                /*!< 0x00008000 */
3972 
3973 #define LCD_FCR_BLINK_Pos          (16U)
3974 #define LCD_FCR_BLINK_Msk          (0x3U << LCD_FCR_BLINK_Pos)                 /*!< 0x00030000 */
3975 #define LCD_FCR_BLINK              LCD_FCR_BLINK_Msk                           /*!< BLINK[1:0] bits (Blink Enable) */
3976 #define LCD_FCR_BLINK_0            (0x1U << LCD_FCR_BLINK_Pos)                 /*!< 0x00010000 */
3977 #define LCD_FCR_BLINK_1            (0x2U << LCD_FCR_BLINK_Pos)                 /*!< 0x00020000 */
3978 
3979 #define LCD_FCR_DIV_Pos            (18U)
3980 #define LCD_FCR_DIV_Msk            (0xFU << LCD_FCR_DIV_Pos)                   /*!< 0x003C0000 */
3981 #define LCD_FCR_DIV                LCD_FCR_DIV_Msk                             /*!< DIV[3:0] bits (Divider) */
3982 #define LCD_FCR_PS_Pos             (22U)
3983 #define LCD_FCR_PS_Msk             (0xFU << LCD_FCR_PS_Pos)                    /*!< 0x03C00000 */
3984 #define LCD_FCR_PS                 LCD_FCR_PS_Msk                              /*!< PS[3:0] bits (Prescaler) */
3985 
3986 /*******************  Bit definition for LCD_SR register  *********************/
3987 #define LCD_SR_ENS_Pos             (0U)
3988 #define LCD_SR_ENS_Msk             (0x1U << LCD_SR_ENS_Pos)                    /*!< 0x00000001 */
3989 #define LCD_SR_ENS                 LCD_SR_ENS_Msk                              /*!< LCD Enabled Bit */
3990 #define LCD_SR_SOF_Pos             (1U)
3991 #define LCD_SR_SOF_Msk             (0x1U << LCD_SR_SOF_Pos)                    /*!< 0x00000002 */
3992 #define LCD_SR_SOF                 LCD_SR_SOF_Msk                              /*!< Start Of Frame Flag Bit */
3993 #define LCD_SR_UDR_Pos             (2U)
3994 #define LCD_SR_UDR_Msk             (0x1U << LCD_SR_UDR_Pos)                    /*!< 0x00000004 */
3995 #define LCD_SR_UDR                 LCD_SR_UDR_Msk                              /*!< Update Display Request Bit */
3996 #define LCD_SR_UDD_Pos             (3U)
3997 #define LCD_SR_UDD_Msk             (0x1U << LCD_SR_UDD_Pos)                    /*!< 0x00000008 */
3998 #define LCD_SR_UDD                 LCD_SR_UDD_Msk                              /*!< Update Display Done Flag Bit */
3999 #define LCD_SR_RDY_Pos             (4U)
4000 #define LCD_SR_RDY_Msk             (0x1U << LCD_SR_RDY_Pos)                    /*!< 0x00000010 */
4001 #define LCD_SR_RDY                 LCD_SR_RDY_Msk                              /*!< Ready Flag Bit */
4002 #define LCD_SR_FCRSR_Pos           (5U)
4003 #define LCD_SR_FCRSR_Msk           (0x1U << LCD_SR_FCRSR_Pos)                  /*!< 0x00000020 */
4004 #define LCD_SR_FCRSR               LCD_SR_FCRSR_Msk                            /*!< LCD FCR Register Synchronization Flag Bit */
4005 
4006 /*******************  Bit definition for LCD_CLR register  ********************/
4007 #define LCD_CLR_SOFC_Pos           (1U)
4008 #define LCD_CLR_SOFC_Msk           (0x1U << LCD_CLR_SOFC_Pos)                  /*!< 0x00000002 */
4009 #define LCD_CLR_SOFC               LCD_CLR_SOFC_Msk                            /*!< Start Of Frame Flag Clear Bit */
4010 #define LCD_CLR_UDDC_Pos           (3U)
4011 #define LCD_CLR_UDDC_Msk           (0x1U << LCD_CLR_UDDC_Pos)                  /*!< 0x00000008 */
4012 #define LCD_CLR_UDDC               LCD_CLR_UDDC_Msk                            /*!< Update Display Done Flag Clear Bit */
4013 
4014 /*******************  Bit definition for LCD_RAM register  ********************/
4015 #define LCD_RAM_SEGMENT_DATA_Pos   (0U)
4016 #define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)   /*!< 0xFFFFFFFF */
4017 #define LCD_RAM_SEGMENT_DATA       LCD_RAM_SEGMENT_DATA_Msk                    /*!< Segment Data Bits */
4018 
4019 /******************************************************************************/
4020 /*                                                                            */
4021 /*                          Power Control (PWR)                               */
4022 /*                                                                            */
4023 /******************************************************************************/
4024 
4025 #define PWR_PVD_SUPPORT                       /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
4026 
4027 /********************  Bit definition for PWR_CR register  ********************/
4028 #define PWR_CR_LPSDSR_Pos                   (0U)
4029 #define PWR_CR_LPSDSR_Msk                   (0x1U << PWR_CR_LPSDSR_Pos)        /*!< 0x00000001 */
4030 #define PWR_CR_LPSDSR                       PWR_CR_LPSDSR_Msk                  /*!< Low-power deepsleep/sleep/low power run */
4031 #define PWR_CR_PDDS_Pos                     (1U)
4032 #define PWR_CR_PDDS_Msk                     (0x1U << PWR_CR_PDDS_Pos)          /*!< 0x00000002 */
4033 #define PWR_CR_PDDS                         PWR_CR_PDDS_Msk                    /*!< Power Down Deepsleep */
4034 #define PWR_CR_CWUF_Pos                     (2U)
4035 #define PWR_CR_CWUF_Msk                     (0x1U << PWR_CR_CWUF_Pos)          /*!< 0x00000004 */
4036 #define PWR_CR_CWUF                         PWR_CR_CWUF_Msk                    /*!< Clear Wakeup Flag */
4037 #define PWR_CR_CSBF_Pos                     (3U)
4038 #define PWR_CR_CSBF_Msk                     (0x1U << PWR_CR_CSBF_Pos)          /*!< 0x00000008 */
4039 #define PWR_CR_CSBF                         PWR_CR_CSBF_Msk                    /*!< Clear Standby Flag */
4040 #define PWR_CR_PVDE_Pos                     (4U)
4041 #define PWR_CR_PVDE_Msk                     (0x1U << PWR_CR_PVDE_Pos)          /*!< 0x00000010 */
4042 #define PWR_CR_PVDE                         PWR_CR_PVDE_Msk                    /*!< Power Voltage Detector Enable */
4043 
4044 #define PWR_CR_PLS_Pos                      (5U)
4045 #define PWR_CR_PLS_Msk                      (0x7U << PWR_CR_PLS_Pos)           /*!< 0x000000E0 */
4046 #define PWR_CR_PLS                          PWR_CR_PLS_Msk                     /*!< PLS[2:0] bits (PVD Level Selection) */
4047 #define PWR_CR_PLS_0                        (0x1U << PWR_CR_PLS_Pos)           /*!< 0x00000020 */
4048 #define PWR_CR_PLS_1                        (0x2U << PWR_CR_PLS_Pos)           /*!< 0x00000040 */
4049 #define PWR_CR_PLS_2                        (0x4U << PWR_CR_PLS_Pos)           /*!< 0x00000080 */
4050 
4051 /*!< PVD level configuration */
4052 #define PWR_CR_PLS_LEV0                     (0x00000000U)                      /*!< PVD level 0 */
4053 #define PWR_CR_PLS_LEV1                     (0x00000020U)                      /*!< PVD level 1 */
4054 #define PWR_CR_PLS_LEV2                     (0x00000040U)                      /*!< PVD level 2 */
4055 #define PWR_CR_PLS_LEV3                     (0x00000060U)                      /*!< PVD level 3 */
4056 #define PWR_CR_PLS_LEV4                     (0x00000080U)                      /*!< PVD level 4 */
4057 #define PWR_CR_PLS_LEV5                     (0x000000A0U)                      /*!< PVD level 5 */
4058 #define PWR_CR_PLS_LEV6                     (0x000000C0U)                      /*!< PVD level 6 */
4059 #define PWR_CR_PLS_LEV7                     (0x000000E0U)                      /*!< PVD level 7 */
4060 
4061 #define PWR_CR_DBP_Pos                      (8U)
4062 #define PWR_CR_DBP_Msk                      (0x1U << PWR_CR_DBP_Pos)           /*!< 0x00000100 */
4063 #define PWR_CR_DBP                          PWR_CR_DBP_Msk                     /*!< Disable Backup Domain write protection */
4064 #define PWR_CR_ULP_Pos                      (9U)
4065 #define PWR_CR_ULP_Msk                      (0x1U << PWR_CR_ULP_Pos)           /*!< 0x00000200 */
4066 #define PWR_CR_ULP                          PWR_CR_ULP_Msk                     /*!< Ultra Low Power mode */
4067 #define PWR_CR_FWU_Pos                      (10U)
4068 #define PWR_CR_FWU_Msk                      (0x1U << PWR_CR_FWU_Pos)           /*!< 0x00000400 */
4069 #define PWR_CR_FWU                          PWR_CR_FWU_Msk                     /*!< Fast wakeup */
4070 
4071 #define PWR_CR_VOS_Pos                      (11U)
4072 #define PWR_CR_VOS_Msk                      (0x3U << PWR_CR_VOS_Pos)           /*!< 0x00001800 */
4073 #define PWR_CR_VOS                          PWR_CR_VOS_Msk                     /*!< VOS[1:0] bits (Voltage scaling range selection) */
4074 #define PWR_CR_VOS_0                        (0x1U << PWR_CR_VOS_Pos)           /*!< 0x00000800 */
4075 #define PWR_CR_VOS_1                        (0x2U << PWR_CR_VOS_Pos)           /*!< 0x00001000 */
4076 #define PWR_CR_LPRUN_Pos                    (14U)
4077 #define PWR_CR_LPRUN_Msk                    (0x1U << PWR_CR_LPRUN_Pos)         /*!< 0x00004000 */
4078 #define PWR_CR_LPRUN                        PWR_CR_LPRUN_Msk                   /*!< Low power run mode */
4079 
4080 /*******************  Bit definition for PWR_CSR register  ********************/
4081 #define PWR_CSR_WUF_Pos                     (0U)
4082 #define PWR_CSR_WUF_Msk                     (0x1U << PWR_CSR_WUF_Pos)          /*!< 0x00000001 */
4083 #define PWR_CSR_WUF                         PWR_CSR_WUF_Msk                    /*!< Wakeup Flag */
4084 #define PWR_CSR_SBF_Pos                     (1U)
4085 #define PWR_CSR_SBF_Msk                     (0x1U << PWR_CSR_SBF_Pos)          /*!< 0x00000002 */
4086 #define PWR_CSR_SBF                         PWR_CSR_SBF_Msk                    /*!< Standby Flag */
4087 #define PWR_CSR_PVDO_Pos                    (2U)
4088 #define PWR_CSR_PVDO_Msk                    (0x1U << PWR_CSR_PVDO_Pos)         /*!< 0x00000004 */
4089 #define PWR_CSR_PVDO                        PWR_CSR_PVDO_Msk                   /*!< PVD Output */
4090 #define PWR_CSR_VREFINTRDYF_Pos             (3U)
4091 #define PWR_CSR_VREFINTRDYF_Msk             (0x1U << PWR_CSR_VREFINTRDYF_Pos)  /*!< 0x00000008 */
4092 #define PWR_CSR_VREFINTRDYF                 PWR_CSR_VREFINTRDYF_Msk            /*!< Internal voltage reference (VREFINT) ready flag */
4093 #define PWR_CSR_VOSF_Pos                    (4U)
4094 #define PWR_CSR_VOSF_Msk                    (0x1U << PWR_CSR_VOSF_Pos)         /*!< 0x00000010 */
4095 #define PWR_CSR_VOSF                        PWR_CSR_VOSF_Msk                   /*!< Voltage Scaling select flag */
4096 #define PWR_CSR_REGLPF_Pos                  (5U)
4097 #define PWR_CSR_REGLPF_Msk                  (0x1U << PWR_CSR_REGLPF_Pos)       /*!< 0x00000020 */
4098 #define PWR_CSR_REGLPF                      PWR_CSR_REGLPF_Msk                 /*!< Regulator LP flag */
4099 
4100 #define PWR_CSR_EWUP1_Pos                   (8U)
4101 #define PWR_CSR_EWUP1_Msk                   (0x1U << PWR_CSR_EWUP1_Pos)        /*!< 0x00000100 */
4102 #define PWR_CSR_EWUP1                       PWR_CSR_EWUP1_Msk                  /*!< Enable WKUP pin 1 */
4103 #define PWR_CSR_EWUP2_Pos                   (9U)
4104 #define PWR_CSR_EWUP2_Msk                   (0x1U << PWR_CSR_EWUP2_Pos)        /*!< 0x00000200 */
4105 #define PWR_CSR_EWUP2                       PWR_CSR_EWUP2_Msk                  /*!< Enable WKUP pin 2 */
4106 #define PWR_CSR_EWUP3_Pos                   (10U)
4107 #define PWR_CSR_EWUP3_Msk                   (0x1U << PWR_CSR_EWUP3_Pos)        /*!< 0x00000400 */
4108 #define PWR_CSR_EWUP3                       PWR_CSR_EWUP3_Msk                  /*!< Enable WKUP pin 3 */
4109 
4110 /******************************************************************************/
4111 /*                                                                            */
4112 /*                      Reset and Clock Control (RCC)                         */
4113 /*                                                                            */
4114 /******************************************************************************/
4115 /*
4116 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
4117 */
4118 #define RCC_LSECSS_SUPPORT          /*!< LSE CSS feature support */
4119 
4120 /********************  Bit definition for RCC_CR register  ********************/
4121 #define RCC_CR_HSION_Pos                    (0U)
4122 #define RCC_CR_HSION_Msk                    (0x1U << RCC_CR_HSION_Pos)         /*!< 0x00000001 */
4123 #define RCC_CR_HSION                        RCC_CR_HSION_Msk                   /*!< Internal High Speed clock enable */
4124 #define RCC_CR_HSIRDY_Pos                   (1U)
4125 #define RCC_CR_HSIRDY_Msk                   (0x1U << RCC_CR_HSIRDY_Pos)        /*!< 0x00000002 */
4126 #define RCC_CR_HSIRDY                       RCC_CR_HSIRDY_Msk                  /*!< Internal High Speed clock ready flag */
4127 
4128 #define RCC_CR_MSION_Pos                    (8U)
4129 #define RCC_CR_MSION_Msk                    (0x1U << RCC_CR_MSION_Pos)         /*!< 0x00000100 */
4130 #define RCC_CR_MSION                        RCC_CR_MSION_Msk                   /*!< Internal Multi Speed clock enable */
4131 #define RCC_CR_MSIRDY_Pos                   (9U)
4132 #define RCC_CR_MSIRDY_Msk                   (0x1U << RCC_CR_MSIRDY_Pos)        /*!< 0x00000200 */
4133 #define RCC_CR_MSIRDY                       RCC_CR_MSIRDY_Msk                  /*!< Internal Multi Speed clock ready flag */
4134 
4135 #define RCC_CR_HSEON_Pos                    (16U)
4136 #define RCC_CR_HSEON_Msk                    (0x1U << RCC_CR_HSEON_Pos)         /*!< 0x00010000 */
4137 #define RCC_CR_HSEON                        RCC_CR_HSEON_Msk                   /*!< External High Speed clock enable */
4138 #define RCC_CR_HSERDY_Pos                   (17U)
4139 #define RCC_CR_HSERDY_Msk                   (0x1U << RCC_CR_HSERDY_Pos)        /*!< 0x00020000 */
4140 #define RCC_CR_HSERDY                       RCC_CR_HSERDY_Msk                  /*!< External High Speed clock ready flag */
4141 #define RCC_CR_HSEBYP_Pos                   (18U)
4142 #define RCC_CR_HSEBYP_Msk                   (0x1U << RCC_CR_HSEBYP_Pos)        /*!< 0x00040000 */
4143 #define RCC_CR_HSEBYP                       RCC_CR_HSEBYP_Msk                  /*!< External High Speed clock Bypass */
4144 
4145 #define RCC_CR_PLLON_Pos                    (24U)
4146 #define RCC_CR_PLLON_Msk                    (0x1U << RCC_CR_PLLON_Pos)         /*!< 0x01000000 */
4147 #define RCC_CR_PLLON                        RCC_CR_PLLON_Msk                   /*!< PLL enable */
4148 #define RCC_CR_PLLRDY_Pos                   (25U)
4149 #define RCC_CR_PLLRDY_Msk                   (0x1U << RCC_CR_PLLRDY_Pos)        /*!< 0x02000000 */
4150 #define RCC_CR_PLLRDY                       RCC_CR_PLLRDY_Msk                  /*!< PLL clock ready flag */
4151 #define RCC_CR_CSSON_Pos                    (28U)
4152 #define RCC_CR_CSSON_Msk                    (0x1U << RCC_CR_CSSON_Pos)         /*!< 0x10000000 */
4153 #define RCC_CR_CSSON                        RCC_CR_CSSON_Msk                   /*!< Clock Security System enable */
4154 
4155 #define RCC_CR_RTCPRE_Pos                   (29U)
4156 #define RCC_CR_RTCPRE_Msk                   (0x3U << RCC_CR_RTCPRE_Pos)        /*!< 0x60000000 */
4157 #define RCC_CR_RTCPRE                       RCC_CR_RTCPRE_Msk                  /*!< RTC/LCD Prescaler */
4158 #define RCC_CR_RTCPRE_0                     (0x20000000U)                      /*!< Bit0 */
4159 #define RCC_CR_RTCPRE_1                     (0x40000000U)                      /*!< Bit1 */
4160 
4161 /********************  Bit definition for RCC_ICSCR register  *****************/
4162 #define RCC_ICSCR_HSICAL_Pos                (0U)
4163 #define RCC_ICSCR_HSICAL_Msk                (0xFFU << RCC_ICSCR_HSICAL_Pos)    /*!< 0x000000FF */
4164 #define RCC_ICSCR_HSICAL                    RCC_ICSCR_HSICAL_Msk               /*!< Internal High Speed clock Calibration */
4165 #define RCC_ICSCR_HSITRIM_Pos               (8U)
4166 #define RCC_ICSCR_HSITRIM_Msk               (0x1FU << RCC_ICSCR_HSITRIM_Pos)   /*!< 0x00001F00 */
4167 #define RCC_ICSCR_HSITRIM                   RCC_ICSCR_HSITRIM_Msk              /*!< Internal High Speed clock trimming */
4168 
4169 #define RCC_ICSCR_MSIRANGE_Pos              (13U)
4170 #define RCC_ICSCR_MSIRANGE_Msk              (0x7U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000E000 */
4171 #define RCC_ICSCR_MSIRANGE                  RCC_ICSCR_MSIRANGE_Msk             /*!< Internal Multi Speed clock Range */
4172 #define RCC_ICSCR_MSIRANGE_0                (0x0U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00000000 */
4173 #define RCC_ICSCR_MSIRANGE_1                (0x1U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00002000 */
4174 #define RCC_ICSCR_MSIRANGE_2                (0x2U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00004000 */
4175 #define RCC_ICSCR_MSIRANGE_3                (0x3U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00006000 */
4176 #define RCC_ICSCR_MSIRANGE_4                (0x4U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x00008000 */
4177 #define RCC_ICSCR_MSIRANGE_5                (0x5U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000A000 */
4178 #define RCC_ICSCR_MSIRANGE_6                (0x6U << RCC_ICSCR_MSIRANGE_Pos)   /*!< 0x0000C000 */
4179 #define RCC_ICSCR_MSICAL_Pos                (16U)
4180 #define RCC_ICSCR_MSICAL_Msk                (0xFFU << RCC_ICSCR_MSICAL_Pos)    /*!< 0x00FF0000 */
4181 #define RCC_ICSCR_MSICAL                    RCC_ICSCR_MSICAL_Msk               /*!< Internal Multi Speed clock Calibration */
4182 #define RCC_ICSCR_MSITRIM_Pos               (24U)
4183 #define RCC_ICSCR_MSITRIM_Msk               (0xFFU << RCC_ICSCR_MSITRIM_Pos)   /*!< 0xFF000000 */
4184 #define RCC_ICSCR_MSITRIM                   RCC_ICSCR_MSITRIM_Msk              /*!< Internal Multi Speed clock trimming */
4185 
4186 /********************  Bit definition for RCC_CFGR register  ******************/
4187 #define RCC_CFGR_SW_Pos                     (0U)
4188 #define RCC_CFGR_SW_Msk                     (0x3U << RCC_CFGR_SW_Pos)          /*!< 0x00000003 */
4189 #define RCC_CFGR_SW                         RCC_CFGR_SW_Msk                    /*!< SW[1:0] bits (System clock Switch) */
4190 #define RCC_CFGR_SW_0                       (0x1U << RCC_CFGR_SW_Pos)          /*!< 0x00000001 */
4191 #define RCC_CFGR_SW_1                       (0x2U << RCC_CFGR_SW_Pos)          /*!< 0x00000002 */
4192 
4193 /*!< SW configuration */
4194 #define RCC_CFGR_SW_MSI                     (0x00000000U)                      /*!< MSI selected as system clock */
4195 #define RCC_CFGR_SW_HSI                     (0x00000001U)                      /*!< HSI selected as system clock */
4196 #define RCC_CFGR_SW_HSE                     (0x00000002U)                      /*!< HSE selected as system clock */
4197 #define RCC_CFGR_SW_PLL                     (0x00000003U)                      /*!< PLL selected as system clock */
4198 
4199 #define RCC_CFGR_SWS_Pos                    (2U)
4200 #define RCC_CFGR_SWS_Msk                    (0x3U << RCC_CFGR_SWS_Pos)         /*!< 0x0000000C */
4201 #define RCC_CFGR_SWS                        RCC_CFGR_SWS_Msk                   /*!< SWS[1:0] bits (System Clock Switch Status) */
4202 #define RCC_CFGR_SWS_0                      (0x1U << RCC_CFGR_SWS_Pos)         /*!< 0x00000004 */
4203 #define RCC_CFGR_SWS_1                      (0x2U << RCC_CFGR_SWS_Pos)         /*!< 0x00000008 */
4204 
4205 /*!< SWS configuration */
4206 #define RCC_CFGR_SWS_MSI                    (0x00000000U)                      /*!< MSI oscillator used as system clock */
4207 #define RCC_CFGR_SWS_HSI                    (0x00000004U)                      /*!< HSI oscillator used as system clock */
4208 #define RCC_CFGR_SWS_HSE                    (0x00000008U)                      /*!< HSE oscillator used as system clock */
4209 #define RCC_CFGR_SWS_PLL                    (0x0000000CU)                      /*!< PLL used as system clock */
4210 
4211 #define RCC_CFGR_HPRE_Pos                   (4U)
4212 #define RCC_CFGR_HPRE_Msk                   (0xFU << RCC_CFGR_HPRE_Pos)        /*!< 0x000000F0 */
4213 #define RCC_CFGR_HPRE                       RCC_CFGR_HPRE_Msk                  /*!< HPRE[3:0] bits (AHB prescaler) */
4214 #define RCC_CFGR_HPRE_0                     (0x1U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000010 */
4215 #define RCC_CFGR_HPRE_1                     (0x2U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000020 */
4216 #define RCC_CFGR_HPRE_2                     (0x4U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000040 */
4217 #define RCC_CFGR_HPRE_3                     (0x8U << RCC_CFGR_HPRE_Pos)        /*!< 0x00000080 */
4218 
4219 /*!< HPRE configuration */
4220 #define RCC_CFGR_HPRE_DIV1                  (0x00000000U)                      /*!< SYSCLK not divided */
4221 #define RCC_CFGR_HPRE_DIV2                  (0x00000080U)                      /*!< SYSCLK divided by 2 */
4222 #define RCC_CFGR_HPRE_DIV4                  (0x00000090U)                      /*!< SYSCLK divided by 4 */
4223 #define RCC_CFGR_HPRE_DIV8                  (0x000000A0U)                      /*!< SYSCLK divided by 8 */
4224 #define RCC_CFGR_HPRE_DIV16                 (0x000000B0U)                      /*!< SYSCLK divided by 16 */
4225 #define RCC_CFGR_HPRE_DIV64                 (0x000000C0U)                      /*!< SYSCLK divided by 64 */
4226 #define RCC_CFGR_HPRE_DIV128                (0x000000D0U)                      /*!< SYSCLK divided by 128 */
4227 #define RCC_CFGR_HPRE_DIV256                (0x000000E0U)                      /*!< SYSCLK divided by 256 */
4228 #define RCC_CFGR_HPRE_DIV512                (0x000000F0U)                      /*!< SYSCLK divided by 512 */
4229 
4230 #define RCC_CFGR_PPRE1_Pos                  (8U)
4231 #define RCC_CFGR_PPRE1_Msk                  (0x7U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000700 */
4232 #define RCC_CFGR_PPRE1                      RCC_CFGR_PPRE1_Msk                 /*!< PRE1[2:0] bits (APB1 prescaler) */
4233 #define RCC_CFGR_PPRE1_0                    (0x1U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000100 */
4234 #define RCC_CFGR_PPRE1_1                    (0x2U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000200 */
4235 #define RCC_CFGR_PPRE1_2                    (0x4U << RCC_CFGR_PPRE1_Pos)       /*!< 0x00000400 */
4236 
4237 /*!< PPRE1 configuration */
4238 #define RCC_CFGR_PPRE1_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
4239 #define RCC_CFGR_PPRE1_DIV2                 (0x00000400U)                      /*!< HCLK divided by 2 */
4240 #define RCC_CFGR_PPRE1_DIV4                 (0x00000500U)                      /*!< HCLK divided by 4 */
4241 #define RCC_CFGR_PPRE1_DIV8                 (0x00000600U)                      /*!< HCLK divided by 8 */
4242 #define RCC_CFGR_PPRE1_DIV16                (0x00000700U)                      /*!< HCLK divided by 16 */
4243 
4244 #define RCC_CFGR_PPRE2_Pos                  (11U)
4245 #define RCC_CFGR_PPRE2_Msk                  (0x7U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00003800 */
4246 #define RCC_CFGR_PPRE2                      RCC_CFGR_PPRE2_Msk                 /*!< PRE2[2:0] bits (APB2 prescaler) */
4247 #define RCC_CFGR_PPRE2_0                    (0x1U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00000800 */
4248 #define RCC_CFGR_PPRE2_1                    (0x2U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00001000 */
4249 #define RCC_CFGR_PPRE2_2                    (0x4U << RCC_CFGR_PPRE2_Pos)       /*!< 0x00002000 */
4250 
4251 /*!< PPRE2 configuration */
4252 #define RCC_CFGR_PPRE2_DIV1                 (0x00000000U)                      /*!< HCLK not divided */
4253 #define RCC_CFGR_PPRE2_DIV2                 (0x00002000U)                      /*!< HCLK divided by 2 */
4254 #define RCC_CFGR_PPRE2_DIV4                 (0x00002800U)                      /*!< HCLK divided by 4 */
4255 #define RCC_CFGR_PPRE2_DIV8                 (0x00003000U)                      /*!< HCLK divided by 8 */
4256 #define RCC_CFGR_PPRE2_DIV16                (0x00003800U)                      /*!< HCLK divided by 16 */
4257 
4258 /*!< PLL entry clock source*/
4259 #define RCC_CFGR_PLLSRC_Pos                 (16U)
4260 #define RCC_CFGR_PLLSRC_Msk                 (0x1U << RCC_CFGR_PLLSRC_Pos)      /*!< 0x00010000 */
4261 #define RCC_CFGR_PLLSRC                     RCC_CFGR_PLLSRC_Msk                /*!< PLL entry clock source */
4262 
4263 #define RCC_CFGR_PLLSRC_HSI                 (0x00000000U)                      /*!< HSI as PLL entry clock source */
4264 #define RCC_CFGR_PLLSRC_HSE                 (0x00010000U)                      /*!< HSE as PLL entry clock source */
4265 
4266 
4267 /*!< PLLMUL configuration */
4268 #define RCC_CFGR_PLLMUL_Pos                 (18U)
4269 #define RCC_CFGR_PLLMUL_Msk                 (0xFU << RCC_CFGR_PLLMUL_Pos)      /*!< 0x003C0000 */
4270 #define RCC_CFGR_PLLMUL                     RCC_CFGR_PLLMUL_Msk                /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
4271 #define RCC_CFGR_PLLMUL_0                   (0x1U << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00040000 */
4272 #define RCC_CFGR_PLLMUL_1                   (0x2U << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00080000 */
4273 #define RCC_CFGR_PLLMUL_2                   (0x4U << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00100000 */
4274 #define RCC_CFGR_PLLMUL_3                   (0x8U << RCC_CFGR_PLLMUL_Pos)      /*!< 0x00200000 */
4275 
4276 /*!< PLLMUL configuration */
4277 #define RCC_CFGR_PLLMUL3                    (0x00000000U)                      /*!< PLL input clock * 3 */
4278 #define RCC_CFGR_PLLMUL4                    (0x00040000U)                      /*!< PLL input clock * 4 */
4279 #define RCC_CFGR_PLLMUL6                    (0x00080000U)                      /*!< PLL input clock * 6 */
4280 #define RCC_CFGR_PLLMUL8                    (0x000C0000U)                      /*!< PLL input clock * 8 */
4281 #define RCC_CFGR_PLLMUL12                   (0x00100000U)                      /*!< PLL input clock * 12 */
4282 #define RCC_CFGR_PLLMUL16                   (0x00140000U)                      /*!< PLL input clock * 16 */
4283 #define RCC_CFGR_PLLMUL24                   (0x00180000U)                      /*!< PLL input clock * 24 */
4284 #define RCC_CFGR_PLLMUL32                   (0x001C0000U)                      /*!< PLL input clock * 32 */
4285 #define RCC_CFGR_PLLMUL48                   (0x00200000U)                      /*!< PLL input clock * 48 */
4286 
4287 /*!< PLLDIV configuration */
4288 #define RCC_CFGR_PLLDIV_Pos                 (22U)
4289 #define RCC_CFGR_PLLDIV_Msk                 (0x3U << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00C00000 */
4290 #define RCC_CFGR_PLLDIV                     RCC_CFGR_PLLDIV_Msk                /*!< PLLDIV[1:0] bits (PLL Output Division) */
4291 #define RCC_CFGR_PLLDIV_0                   (0x1U << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00400000 */
4292 #define RCC_CFGR_PLLDIV_1                   (0x2U << RCC_CFGR_PLLDIV_Pos)      /*!< 0x00800000 */
4293 
4294 
4295 /*!< PLLDIV configuration */
4296 #define RCC_CFGR_PLLDIV1                    (0x00000000U)                      /*!< PLL clock output = CKVCO / 1 */
4297 #define RCC_CFGR_PLLDIV2_Pos                (22U)
4298 #define RCC_CFGR_PLLDIV2_Msk                (0x1U << RCC_CFGR_PLLDIV2_Pos)     /*!< 0x00400000 */
4299 #define RCC_CFGR_PLLDIV2                    RCC_CFGR_PLLDIV2_Msk               /*!< PLL clock output = CKVCO / 2 */
4300 #define RCC_CFGR_PLLDIV3_Pos                (23U)
4301 #define RCC_CFGR_PLLDIV3_Msk                (0x1U << RCC_CFGR_PLLDIV3_Pos)     /*!< 0x00800000 */
4302 #define RCC_CFGR_PLLDIV3                    RCC_CFGR_PLLDIV3_Msk               /*!< PLL clock output = CKVCO / 3 */
4303 #define RCC_CFGR_PLLDIV4_Pos                (22U)
4304 #define RCC_CFGR_PLLDIV4_Msk                (0x3U << RCC_CFGR_PLLDIV4_Pos)     /*!< 0x00C00000 */
4305 #define RCC_CFGR_PLLDIV4                    RCC_CFGR_PLLDIV4_Msk               /*!< PLL clock output = CKVCO / 4 */
4306 
4307 
4308 #define RCC_CFGR_MCOSEL_Pos                 (24U)
4309 #define RCC_CFGR_MCOSEL_Msk                 (0x7U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x07000000 */
4310 #define RCC_CFGR_MCOSEL                     RCC_CFGR_MCOSEL_Msk                /*!< MCO[2:0] bits (Microcontroller Clock Output) */
4311 #define RCC_CFGR_MCOSEL_0                   (0x1U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x01000000 */
4312 #define RCC_CFGR_MCOSEL_1                   (0x2U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x02000000 */
4313 #define RCC_CFGR_MCOSEL_2                   (0x4U << RCC_CFGR_MCOSEL_Pos)      /*!< 0x04000000 */
4314 
4315 /*!< MCO configuration */
4316 #define RCC_CFGR_MCOSEL_NOCLOCK             (0x00000000U)                      /*!< No clock */
4317 #define RCC_CFGR_MCOSEL_SYSCLK_Pos          (24U)
4318 #define RCC_CFGR_MCOSEL_SYSCLK_Msk          (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos) /*!< 0x01000000 */
4319 #define RCC_CFGR_MCOSEL_SYSCLK              RCC_CFGR_MCOSEL_SYSCLK_Msk         /*!< System clock selected */
4320 #define RCC_CFGR_MCOSEL_HSI_Pos             (25U)
4321 #define RCC_CFGR_MCOSEL_HSI_Msk             (0x1U << RCC_CFGR_MCOSEL_HSI_Pos)  /*!< 0x02000000 */
4322 #define RCC_CFGR_MCOSEL_HSI                 RCC_CFGR_MCOSEL_HSI_Msk            /*!< Internal 16 MHz RC oscillator clock selected */
4323 #define RCC_CFGR_MCOSEL_MSI_Pos             (24U)
4324 #define RCC_CFGR_MCOSEL_MSI_Msk             (0x3U << RCC_CFGR_MCOSEL_MSI_Pos)  /*!< 0x03000000 */
4325 #define RCC_CFGR_MCOSEL_MSI                 RCC_CFGR_MCOSEL_MSI_Msk            /*!< Internal Medium Speed RC oscillator clock selected */
4326 #define RCC_CFGR_MCOSEL_HSE_Pos             (26U)
4327 #define RCC_CFGR_MCOSEL_HSE_Msk             (0x1U << RCC_CFGR_MCOSEL_HSE_Pos)  /*!< 0x04000000 */
4328 #define RCC_CFGR_MCOSEL_HSE                 RCC_CFGR_MCOSEL_HSE_Msk            /*!< External 1-25 MHz oscillator clock selected */
4329 #define RCC_CFGR_MCOSEL_PLL_Pos             (24U)
4330 #define RCC_CFGR_MCOSEL_PLL_Msk             (0x5U << RCC_CFGR_MCOSEL_PLL_Pos)  /*!< 0x05000000 */
4331 #define RCC_CFGR_MCOSEL_PLL                 RCC_CFGR_MCOSEL_PLL_Msk            /*!< PLL clock divided */
4332 #define RCC_CFGR_MCOSEL_LSI_Pos             (25U)
4333 #define RCC_CFGR_MCOSEL_LSI_Msk             (0x3U << RCC_CFGR_MCOSEL_LSI_Pos)  /*!< 0x06000000 */
4334 #define RCC_CFGR_MCOSEL_LSI                 RCC_CFGR_MCOSEL_LSI_Msk            /*!< LSI selected */
4335 #define RCC_CFGR_MCOSEL_LSE_Pos             (24U)
4336 #define RCC_CFGR_MCOSEL_LSE_Msk             (0x7U << RCC_CFGR_MCOSEL_LSE_Pos)  /*!< 0x07000000 */
4337 #define RCC_CFGR_MCOSEL_LSE                 RCC_CFGR_MCOSEL_LSE_Msk            /*!< LSE selected */
4338 
4339 #define RCC_CFGR_MCOPRE_Pos                 (28U)
4340 #define RCC_CFGR_MCOPRE_Msk                 (0x7U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x70000000 */
4341 #define RCC_CFGR_MCOPRE                     RCC_CFGR_MCOPRE_Msk                /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
4342 #define RCC_CFGR_MCOPRE_0                   (0x1U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x10000000 */
4343 #define RCC_CFGR_MCOPRE_1                   (0x2U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x20000000 */
4344 #define RCC_CFGR_MCOPRE_2                   (0x4U << RCC_CFGR_MCOPRE_Pos)      /*!< 0x40000000 */
4345 
4346 /*!< MCO Prescaler configuration */
4347 #define RCC_CFGR_MCOPRE_DIV1                (0x00000000U)                      /*!< MCO is divided by 1 */
4348 #define RCC_CFGR_MCOPRE_DIV2                (0x10000000U)                      /*!< MCO is divided by 2 */
4349 #define RCC_CFGR_MCOPRE_DIV4                (0x20000000U)                      /*!< MCO is divided by 4 */
4350 #define RCC_CFGR_MCOPRE_DIV8                (0x30000000U)                      /*!< MCO is divided by 8 */
4351 #define RCC_CFGR_MCOPRE_DIV16               (0x40000000U)                      /*!< MCO is divided by 16 */
4352 
4353 /* Legacy aliases */
4354 #define  RCC_CFGR_MCO_DIV1                  RCC_CFGR_MCOPRE_DIV1
4355 #define  RCC_CFGR_MCO_DIV2                  RCC_CFGR_MCOPRE_DIV2
4356 #define  RCC_CFGR_MCO_DIV4                  RCC_CFGR_MCOPRE_DIV4
4357 #define  RCC_CFGR_MCO_DIV8                  RCC_CFGR_MCOPRE_DIV8
4358 #define  RCC_CFGR_MCO_DIV16                 RCC_CFGR_MCOPRE_DIV16
4359 #define  RCC_CFGR_MCO_NOCLOCK               RCC_CFGR_MCOSEL_NOCLOCK
4360 #define  RCC_CFGR_MCO_SYSCLK                RCC_CFGR_MCOSEL_SYSCLK
4361 #define  RCC_CFGR_MCO_HSI                   RCC_CFGR_MCOSEL_HSI
4362 #define  RCC_CFGR_MCO_MSI                   RCC_CFGR_MCOSEL_MSI
4363 #define  RCC_CFGR_MCO_HSE                   RCC_CFGR_MCOSEL_HSE
4364 #define  RCC_CFGR_MCO_PLL                   RCC_CFGR_MCOSEL_PLL
4365 #define  RCC_CFGR_MCO_LSI                   RCC_CFGR_MCOSEL_LSI
4366 #define  RCC_CFGR_MCO_LSE                   RCC_CFGR_MCOSEL_LSE
4367 
4368 /*!<******************  Bit definition for RCC_CIR register  ********************/
4369 #define RCC_CIR_LSIRDYF_Pos                 (0U)
4370 #define RCC_CIR_LSIRDYF_Msk                 (0x1U << RCC_CIR_LSIRDYF_Pos)      /*!< 0x00000001 */
4371 #define RCC_CIR_LSIRDYF                     RCC_CIR_LSIRDYF_Msk                /*!< LSI Ready Interrupt flag */
4372 #define RCC_CIR_LSERDYF_Pos                 (1U)
4373 #define RCC_CIR_LSERDYF_Msk                 (0x1U << RCC_CIR_LSERDYF_Pos)      /*!< 0x00000002 */
4374 #define RCC_CIR_LSERDYF                     RCC_CIR_LSERDYF_Msk                /*!< LSE Ready Interrupt flag */
4375 #define RCC_CIR_HSIRDYF_Pos                 (2U)
4376 #define RCC_CIR_HSIRDYF_Msk                 (0x1U << RCC_CIR_HSIRDYF_Pos)      /*!< 0x00000004 */
4377 #define RCC_CIR_HSIRDYF                     RCC_CIR_HSIRDYF_Msk                /*!< HSI Ready Interrupt flag */
4378 #define RCC_CIR_HSERDYF_Pos                 (3U)
4379 #define RCC_CIR_HSERDYF_Msk                 (0x1U << RCC_CIR_HSERDYF_Pos)      /*!< 0x00000008 */
4380 #define RCC_CIR_HSERDYF                     RCC_CIR_HSERDYF_Msk                /*!< HSE Ready Interrupt flag */
4381 #define RCC_CIR_PLLRDYF_Pos                 (4U)
4382 #define RCC_CIR_PLLRDYF_Msk                 (0x1U << RCC_CIR_PLLRDYF_Pos)      /*!< 0x00000010 */
4383 #define RCC_CIR_PLLRDYF                     RCC_CIR_PLLRDYF_Msk                /*!< PLL Ready Interrupt flag */
4384 #define RCC_CIR_MSIRDYF_Pos                 (5U)
4385 #define RCC_CIR_MSIRDYF_Msk                 (0x1U << RCC_CIR_MSIRDYF_Pos)      /*!< 0x00000020 */
4386 #define RCC_CIR_MSIRDYF                     RCC_CIR_MSIRDYF_Msk                /*!< MSI Ready Interrupt flag */
4387 #define RCC_CIR_LSECSSF_Pos                 (6U)
4388 #define RCC_CIR_LSECSSF_Msk                 (0x1U << RCC_CIR_LSECSSF_Pos)      /*!< 0x00000040 */
4389 #define RCC_CIR_LSECSSF                     RCC_CIR_LSECSSF_Msk                /*!< LSE CSS Interrupt flag */
4390 #define RCC_CIR_CSSF_Pos                    (7U)
4391 #define RCC_CIR_CSSF_Msk                    (0x1U << RCC_CIR_CSSF_Pos)         /*!< 0x00000080 */
4392 #define RCC_CIR_CSSF                        RCC_CIR_CSSF_Msk                   /*!< Clock Security System Interrupt flag */
4393 
4394 #define RCC_CIR_LSIRDYIE_Pos                (8U)
4395 #define RCC_CIR_LSIRDYIE_Msk                (0x1U << RCC_CIR_LSIRDYIE_Pos)     /*!< 0x00000100 */
4396 #define RCC_CIR_LSIRDYIE                    RCC_CIR_LSIRDYIE_Msk               /*!< LSI Ready Interrupt Enable */
4397 #define RCC_CIR_LSERDYIE_Pos                (9U)
4398 #define RCC_CIR_LSERDYIE_Msk                (0x1U << RCC_CIR_LSERDYIE_Pos)     /*!< 0x00000200 */
4399 #define RCC_CIR_LSERDYIE                    RCC_CIR_LSERDYIE_Msk               /*!< LSE Ready Interrupt Enable */
4400 #define RCC_CIR_HSIRDYIE_Pos                (10U)
4401 #define RCC_CIR_HSIRDYIE_Msk                (0x1U << RCC_CIR_HSIRDYIE_Pos)     /*!< 0x00000400 */
4402 #define RCC_CIR_HSIRDYIE                    RCC_CIR_HSIRDYIE_Msk               /*!< HSI Ready Interrupt Enable */
4403 #define RCC_CIR_HSERDYIE_Pos                (11U)
4404 #define RCC_CIR_HSERDYIE_Msk                (0x1U << RCC_CIR_HSERDYIE_Pos)     /*!< 0x00000800 */
4405 #define RCC_CIR_HSERDYIE                    RCC_CIR_HSERDYIE_Msk               /*!< HSE Ready Interrupt Enable */
4406 #define RCC_CIR_PLLRDYIE_Pos                (12U)
4407 #define RCC_CIR_PLLRDYIE_Msk                (0x1U << RCC_CIR_PLLRDYIE_Pos)     /*!< 0x00001000 */
4408 #define RCC_CIR_PLLRDYIE                    RCC_CIR_PLLRDYIE_Msk               /*!< PLL Ready Interrupt Enable */
4409 #define RCC_CIR_MSIRDYIE_Pos                (13U)
4410 #define RCC_CIR_MSIRDYIE_Msk                (0x1U << RCC_CIR_MSIRDYIE_Pos)     /*!< 0x00002000 */
4411 #define RCC_CIR_MSIRDYIE                    RCC_CIR_MSIRDYIE_Msk               /*!< MSI Ready Interrupt Enable */
4412 #define RCC_CIR_LSECSSIE_Pos                (14U)
4413 #define RCC_CIR_LSECSSIE_Msk                (0x1U << RCC_CIR_LSECSSIE_Pos)     /*!< 0x00004000 */
4414 #define RCC_CIR_LSECSSIE                    RCC_CIR_LSECSSIE_Msk               /*!< LSE CSS Interrupt Enable */
4415 
4416 #define RCC_CIR_LSIRDYC_Pos                 (16U)
4417 #define RCC_CIR_LSIRDYC_Msk                 (0x1U << RCC_CIR_LSIRDYC_Pos)      /*!< 0x00010000 */
4418 #define RCC_CIR_LSIRDYC                     RCC_CIR_LSIRDYC_Msk                /*!< LSI Ready Interrupt Clear */
4419 #define RCC_CIR_LSERDYC_Pos                 (17U)
4420 #define RCC_CIR_LSERDYC_Msk                 (0x1U << RCC_CIR_LSERDYC_Pos)      /*!< 0x00020000 */
4421 #define RCC_CIR_LSERDYC                     RCC_CIR_LSERDYC_Msk                /*!< LSE Ready Interrupt Clear */
4422 #define RCC_CIR_HSIRDYC_Pos                 (18U)
4423 #define RCC_CIR_HSIRDYC_Msk                 (0x1U << RCC_CIR_HSIRDYC_Pos)      /*!< 0x00040000 */
4424 #define RCC_CIR_HSIRDYC                     RCC_CIR_HSIRDYC_Msk                /*!< HSI Ready Interrupt Clear */
4425 #define RCC_CIR_HSERDYC_Pos                 (19U)
4426 #define RCC_CIR_HSERDYC_Msk                 (0x1U << RCC_CIR_HSERDYC_Pos)      /*!< 0x00080000 */
4427 #define RCC_CIR_HSERDYC                     RCC_CIR_HSERDYC_Msk                /*!< HSE Ready Interrupt Clear */
4428 #define RCC_CIR_PLLRDYC_Pos                 (20U)
4429 #define RCC_CIR_PLLRDYC_Msk                 (0x1U << RCC_CIR_PLLRDYC_Pos)      /*!< 0x00100000 */
4430 #define RCC_CIR_PLLRDYC                     RCC_CIR_PLLRDYC_Msk                /*!< PLL Ready Interrupt Clear */
4431 #define RCC_CIR_MSIRDYC_Pos                 (21U)
4432 #define RCC_CIR_MSIRDYC_Msk                 (0x1U << RCC_CIR_MSIRDYC_Pos)      /*!< 0x00200000 */
4433 #define RCC_CIR_MSIRDYC                     RCC_CIR_MSIRDYC_Msk                /*!< MSI Ready Interrupt Clear */
4434 #define RCC_CIR_LSECSSC_Pos                 (22U)
4435 #define RCC_CIR_LSECSSC_Msk                 (0x1U << RCC_CIR_LSECSSC_Pos)      /*!< 0x00400000 */
4436 #define RCC_CIR_LSECSSC                     RCC_CIR_LSECSSC_Msk                /*!< LSE CSS Interrupt Clear */
4437 #define RCC_CIR_CSSC_Pos                    (23U)
4438 #define RCC_CIR_CSSC_Msk                    (0x1U << RCC_CIR_CSSC_Pos)         /*!< 0x00800000 */
4439 #define RCC_CIR_CSSC                        RCC_CIR_CSSC_Msk                   /*!< Clock Security System Interrupt Clear */
4440 
4441 /*****************  Bit definition for RCC_AHBRSTR register  ******************/
4442 #define RCC_AHBRSTR_GPIOARST_Pos            (0U)
4443 #define RCC_AHBRSTR_GPIOARST_Msk            (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00000001 */
4444 #define RCC_AHBRSTR_GPIOARST                RCC_AHBRSTR_GPIOARST_Msk           /*!< GPIO port A reset */
4445 #define RCC_AHBRSTR_GPIOBRST_Pos            (1U)
4446 #define RCC_AHBRSTR_GPIOBRST_Msk            (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00000002 */
4447 #define RCC_AHBRSTR_GPIOBRST                RCC_AHBRSTR_GPIOBRST_Msk           /*!< GPIO port B reset */
4448 #define RCC_AHBRSTR_GPIOCRST_Pos            (2U)
4449 #define RCC_AHBRSTR_GPIOCRST_Msk            (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00000004 */
4450 #define RCC_AHBRSTR_GPIOCRST                RCC_AHBRSTR_GPIOCRST_Msk           /*!< GPIO port C reset */
4451 #define RCC_AHBRSTR_GPIODRST_Pos            (3U)
4452 #define RCC_AHBRSTR_GPIODRST_Msk            (0x1U << RCC_AHBRSTR_GPIODRST_Pos) /*!< 0x00000008 */
4453 #define RCC_AHBRSTR_GPIODRST                RCC_AHBRSTR_GPIODRST_Msk           /*!< GPIO port D reset */
4454 #define RCC_AHBRSTR_GPIOERST_Pos            (4U)
4455 #define RCC_AHBRSTR_GPIOERST_Msk            (0x1U << RCC_AHBRSTR_GPIOERST_Pos) /*!< 0x00000010 */
4456 #define RCC_AHBRSTR_GPIOERST                RCC_AHBRSTR_GPIOERST_Msk           /*!< GPIO port E reset */
4457 #define RCC_AHBRSTR_GPIOHRST_Pos            (5U)
4458 #define RCC_AHBRSTR_GPIOHRST_Msk            (0x1U << RCC_AHBRSTR_GPIOHRST_Pos) /*!< 0x00000020 */
4459 #define RCC_AHBRSTR_GPIOHRST                RCC_AHBRSTR_GPIOHRST_Msk           /*!< GPIO port H reset */
4460 #define RCC_AHBRSTR_CRCRST_Pos              (12U)
4461 #define RCC_AHBRSTR_CRCRST_Msk              (0x1U << RCC_AHBRSTR_CRCRST_Pos)   /*!< 0x00001000 */
4462 #define RCC_AHBRSTR_CRCRST                  RCC_AHBRSTR_CRCRST_Msk             /*!< CRC reset */
4463 #define RCC_AHBRSTR_FLITFRST_Pos            (15U)
4464 #define RCC_AHBRSTR_FLITFRST_Msk            (0x1U << RCC_AHBRSTR_FLITFRST_Pos) /*!< 0x00008000 */
4465 #define RCC_AHBRSTR_FLITFRST                RCC_AHBRSTR_FLITFRST_Msk           /*!< FLITF reset */
4466 #define RCC_AHBRSTR_DMA1RST_Pos             (24U)
4467 #define RCC_AHBRSTR_DMA1RST_Msk             (0x1U << RCC_AHBRSTR_DMA1RST_Pos)  /*!< 0x01000000 */
4468 #define RCC_AHBRSTR_DMA1RST                 RCC_AHBRSTR_DMA1RST_Msk            /*!< DMA1 reset */
4469 #define RCC_AHBRSTR_DMA2RST_Pos             (25U)
4470 #define RCC_AHBRSTR_DMA2RST_Msk             (0x1U << RCC_AHBRSTR_DMA2RST_Pos)  /*!< 0x02000000 */
4471 #define RCC_AHBRSTR_DMA2RST                 RCC_AHBRSTR_DMA2RST_Msk            /*!< DMA2 reset */
4472 
4473 /*****************  Bit definition for RCC_APB2RSTR register  *****************/
4474 #define RCC_APB2RSTR_SYSCFGRST_Pos          (0U)
4475 #define RCC_APB2RSTR_SYSCFGRST_Msk          (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
4476 #define RCC_APB2RSTR_SYSCFGRST              RCC_APB2RSTR_SYSCFGRST_Msk         /*!< System Configuration SYSCFG reset */
4477 #define RCC_APB2RSTR_TIM9RST_Pos            (2U)
4478 #define RCC_APB2RSTR_TIM9RST_Msk            (0x1U << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00000004 */
4479 #define RCC_APB2RSTR_TIM9RST                RCC_APB2RSTR_TIM9RST_Msk           /*!< TIM9 reset */
4480 #define RCC_APB2RSTR_TIM10RST_Pos           (3U)
4481 #define RCC_APB2RSTR_TIM10RST_Msk           (0x1U << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00000008 */
4482 #define RCC_APB2RSTR_TIM10RST               RCC_APB2RSTR_TIM10RST_Msk          /*!< TIM10 reset */
4483 #define RCC_APB2RSTR_TIM11RST_Pos           (4U)
4484 #define RCC_APB2RSTR_TIM11RST_Msk           (0x1U << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00000010 */
4485 #define RCC_APB2RSTR_TIM11RST               RCC_APB2RSTR_TIM11RST_Msk          /*!< TIM11 reset */
4486 #define RCC_APB2RSTR_ADC1RST_Pos            (9U)
4487 #define RCC_APB2RSTR_ADC1RST_Msk            (0x1U << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */
4488 #define RCC_APB2RSTR_ADC1RST                RCC_APB2RSTR_ADC1RST_Msk           /*!< ADC1 reset */
4489 #define RCC_APB2RSTR_SPI1RST_Pos            (12U)
4490 #define RCC_APB2RSTR_SPI1RST_Msk            (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
4491 #define RCC_APB2RSTR_SPI1RST                RCC_APB2RSTR_SPI1RST_Msk           /*!< SPI1 reset */
4492 #define RCC_APB2RSTR_USART1RST_Pos          (14U)
4493 #define RCC_APB2RSTR_USART1RST_Msk          (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
4494 #define RCC_APB2RSTR_USART1RST              RCC_APB2RSTR_USART1RST_Msk         /*!< USART1 reset */
4495 
4496 /*****************  Bit definition for RCC_APB1RSTR register  *****************/
4497 #define RCC_APB1RSTR_TIM2RST_Pos            (0U)
4498 #define RCC_APB1RSTR_TIM2RST_Msk            (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
4499 #define RCC_APB1RSTR_TIM2RST                RCC_APB1RSTR_TIM2RST_Msk           /*!< Timer 2 reset */
4500 #define RCC_APB1RSTR_TIM3RST_Pos            (1U)
4501 #define RCC_APB1RSTR_TIM3RST_Msk            (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
4502 #define RCC_APB1RSTR_TIM3RST                RCC_APB1RSTR_TIM3RST_Msk           /*!< Timer 3 reset */
4503 #define RCC_APB1RSTR_TIM4RST_Pos            (2U)
4504 #define RCC_APB1RSTR_TIM4RST_Msk            (0x1U << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */
4505 #define RCC_APB1RSTR_TIM4RST                RCC_APB1RSTR_TIM4RST_Msk           /*!< Timer 4 reset */
4506 #define RCC_APB1RSTR_TIM5RST_Pos            (3U)
4507 #define RCC_APB1RSTR_TIM5RST_Msk            (0x1U << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */
4508 #define RCC_APB1RSTR_TIM5RST                RCC_APB1RSTR_TIM5RST_Msk           /*!< Timer 5 reset */
4509 #define RCC_APB1RSTR_TIM6RST_Pos            (4U)
4510 #define RCC_APB1RSTR_TIM6RST_Msk            (0x1U << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */
4511 #define RCC_APB1RSTR_TIM6RST                RCC_APB1RSTR_TIM6RST_Msk           /*!< Timer 6 reset */
4512 #define RCC_APB1RSTR_TIM7RST_Pos            (5U)
4513 #define RCC_APB1RSTR_TIM7RST_Msk            (0x1U << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */
4514 #define RCC_APB1RSTR_TIM7RST                RCC_APB1RSTR_TIM7RST_Msk           /*!< Timer 7 reset */
4515 #define RCC_APB1RSTR_LCDRST_Pos             (9U)
4516 #define RCC_APB1RSTR_LCDRST_Msk             (0x1U << RCC_APB1RSTR_LCDRST_Pos)  /*!< 0x00000200 */
4517 #define RCC_APB1RSTR_LCDRST                 RCC_APB1RSTR_LCDRST_Msk            /*!< LCD reset */
4518 #define RCC_APB1RSTR_WWDGRST_Pos            (11U)
4519 #define RCC_APB1RSTR_WWDGRST_Msk            (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
4520 #define RCC_APB1RSTR_WWDGRST                RCC_APB1RSTR_WWDGRST_Msk           /*!< Window Watchdog reset */
4521 #define RCC_APB1RSTR_SPI2RST_Pos            (14U)
4522 #define RCC_APB1RSTR_SPI2RST_Msk            (0x1U << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */
4523 #define RCC_APB1RSTR_SPI2RST                RCC_APB1RSTR_SPI2RST_Msk           /*!< SPI 2 reset */
4524 #define RCC_APB1RSTR_SPI3RST_Pos            (15U)
4525 #define RCC_APB1RSTR_SPI3RST_Msk            (0x1U << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */
4526 #define RCC_APB1RSTR_SPI3RST                RCC_APB1RSTR_SPI3RST_Msk           /*!< SPI 3 reset */
4527 #define RCC_APB1RSTR_USART2RST_Pos          (17U)
4528 #define RCC_APB1RSTR_USART2RST_Msk          (0x1U << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */
4529 #define RCC_APB1RSTR_USART2RST              RCC_APB1RSTR_USART2RST_Msk         /*!< USART 2 reset */
4530 #define RCC_APB1RSTR_USART3RST_Pos          (18U)
4531 #define RCC_APB1RSTR_USART3RST_Msk          (0x1U << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */
4532 #define RCC_APB1RSTR_USART3RST              RCC_APB1RSTR_USART3RST_Msk         /*!< USART 3 reset */
4533 #define RCC_APB1RSTR_I2C1RST_Pos            (21U)
4534 #define RCC_APB1RSTR_I2C1RST_Msk            (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
4535 #define RCC_APB1RSTR_I2C1RST                RCC_APB1RSTR_I2C1RST_Msk           /*!< I2C 1 reset */
4536 #define RCC_APB1RSTR_I2C2RST_Pos            (22U)
4537 #define RCC_APB1RSTR_I2C2RST_Msk            (0x1U << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */
4538 #define RCC_APB1RSTR_I2C2RST                RCC_APB1RSTR_I2C2RST_Msk           /*!< I2C 2 reset */
4539 #define RCC_APB1RSTR_USBRST_Pos             (23U)
4540 #define RCC_APB1RSTR_USBRST_Msk             (0x1U << RCC_APB1RSTR_USBRST_Pos)  /*!< 0x00800000 */
4541 #define RCC_APB1RSTR_USBRST                 RCC_APB1RSTR_USBRST_Msk            /*!< USB reset */
4542 #define RCC_APB1RSTR_PWRRST_Pos             (28U)
4543 #define RCC_APB1RSTR_PWRRST_Msk             (0x1U << RCC_APB1RSTR_PWRRST_Pos)  /*!< 0x10000000 */
4544 #define RCC_APB1RSTR_PWRRST                 RCC_APB1RSTR_PWRRST_Msk            /*!< Power interface reset */
4545 #define RCC_APB1RSTR_DACRST_Pos             (29U)
4546 #define RCC_APB1RSTR_DACRST_Msk             (0x1U << RCC_APB1RSTR_DACRST_Pos)  /*!< 0x20000000 */
4547 #define RCC_APB1RSTR_DACRST                 RCC_APB1RSTR_DACRST_Msk            /*!< DAC interface reset */
4548 #define RCC_APB1RSTR_COMPRST_Pos            (31U)
4549 #define RCC_APB1RSTR_COMPRST_Msk            (0x1U << RCC_APB1RSTR_COMPRST_Pos) /*!< 0x80000000 */
4550 #define RCC_APB1RSTR_COMPRST                RCC_APB1RSTR_COMPRST_Msk           /*!< Comparator interface reset */
4551 
4552 /******************  Bit definition for RCC_AHBENR register  ******************/
4553 #define RCC_AHBENR_GPIOAEN_Pos              (0U)
4554 #define RCC_AHBENR_GPIOAEN_Msk              (0x1U << RCC_AHBENR_GPIOAEN_Pos)   /*!< 0x00000001 */
4555 #define RCC_AHBENR_GPIOAEN                  RCC_AHBENR_GPIOAEN_Msk             /*!< GPIO port A clock enable */
4556 #define RCC_AHBENR_GPIOBEN_Pos              (1U)
4557 #define RCC_AHBENR_GPIOBEN_Msk              (0x1U << RCC_AHBENR_GPIOBEN_Pos)   /*!< 0x00000002 */
4558 #define RCC_AHBENR_GPIOBEN                  RCC_AHBENR_GPIOBEN_Msk             /*!< GPIO port B clock enable */
4559 #define RCC_AHBENR_GPIOCEN_Pos              (2U)
4560 #define RCC_AHBENR_GPIOCEN_Msk              (0x1U << RCC_AHBENR_GPIOCEN_Pos)   /*!< 0x00000004 */
4561 #define RCC_AHBENR_GPIOCEN                  RCC_AHBENR_GPIOCEN_Msk             /*!< GPIO port C clock enable */
4562 #define RCC_AHBENR_GPIODEN_Pos              (3U)
4563 #define RCC_AHBENR_GPIODEN_Msk              (0x1U << RCC_AHBENR_GPIODEN_Pos)   /*!< 0x00000008 */
4564 #define RCC_AHBENR_GPIODEN                  RCC_AHBENR_GPIODEN_Msk             /*!< GPIO port D clock enable */
4565 #define RCC_AHBENR_GPIOEEN_Pos              (4U)
4566 #define RCC_AHBENR_GPIOEEN_Msk              (0x1U << RCC_AHBENR_GPIOEEN_Pos)   /*!< 0x00000010 */
4567 #define RCC_AHBENR_GPIOEEN                  RCC_AHBENR_GPIOEEN_Msk             /*!< GPIO port E clock enable */
4568 #define RCC_AHBENR_GPIOHEN_Pos              (5U)
4569 #define RCC_AHBENR_GPIOHEN_Msk              (0x1U << RCC_AHBENR_GPIOHEN_Pos)   /*!< 0x00000020 */
4570 #define RCC_AHBENR_GPIOHEN                  RCC_AHBENR_GPIOHEN_Msk             /*!< GPIO port H clock enable */
4571 #define RCC_AHBENR_CRCEN_Pos                (12U)
4572 #define RCC_AHBENR_CRCEN_Msk                (0x1U << RCC_AHBENR_CRCEN_Pos)     /*!< 0x00001000 */
4573 #define RCC_AHBENR_CRCEN                    RCC_AHBENR_CRCEN_Msk               /*!< CRC clock enable */
4574 #define RCC_AHBENR_FLITFEN_Pos              (15U)
4575 #define RCC_AHBENR_FLITFEN_Msk              (0x1U << RCC_AHBENR_FLITFEN_Pos)   /*!< 0x00008000 */
4576 #define RCC_AHBENR_FLITFEN                  RCC_AHBENR_FLITFEN_Msk             /*!< FLITF clock enable (has effect only when
4577                                                                                 the Flash memory is in power down mode) */
4578 #define RCC_AHBENR_DMA1EN_Pos               (24U)
4579 #define RCC_AHBENR_DMA1EN_Msk               (0x1U << RCC_AHBENR_DMA1EN_Pos)    /*!< 0x01000000 */
4580 #define RCC_AHBENR_DMA1EN                   RCC_AHBENR_DMA1EN_Msk              /*!< DMA1 clock enable */
4581 #define RCC_AHBENR_DMA2EN_Pos               (25U)
4582 #define RCC_AHBENR_DMA2EN_Msk               (0x1U << RCC_AHBENR_DMA2EN_Pos)    /*!< 0x02000000 */
4583 #define RCC_AHBENR_DMA2EN                   RCC_AHBENR_DMA2EN_Msk              /*!< DMA2 clock enable */
4584 
4585 /******************  Bit definition for RCC_APB2ENR register  *****************/
4586 #define RCC_APB2ENR_SYSCFGEN_Pos            (0U)
4587 #define RCC_APB2ENR_SYSCFGEN_Msk            (0x1U << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00000001 */
4588 #define RCC_APB2ENR_SYSCFGEN                RCC_APB2ENR_SYSCFGEN_Msk           /*!< System Configuration SYSCFG clock enable */
4589 #define RCC_APB2ENR_TIM9EN_Pos              (2U)
4590 #define RCC_APB2ENR_TIM9EN_Msk              (0x1U << RCC_APB2ENR_TIM9EN_Pos)   /*!< 0x00000004 */
4591 #define RCC_APB2ENR_TIM9EN                  RCC_APB2ENR_TIM9EN_Msk             /*!< TIM9 interface clock enable */
4592 #define RCC_APB2ENR_TIM10EN_Pos             (3U)
4593 #define RCC_APB2ENR_TIM10EN_Msk             (0x1U << RCC_APB2ENR_TIM10EN_Pos)  /*!< 0x00000008 */
4594 #define RCC_APB2ENR_TIM10EN                 RCC_APB2ENR_TIM10EN_Msk            /*!< TIM10 interface clock enable */
4595 #define RCC_APB2ENR_TIM11EN_Pos             (4U)
4596 #define RCC_APB2ENR_TIM11EN_Msk             (0x1U << RCC_APB2ENR_TIM11EN_Pos)  /*!< 0x00000010 */
4597 #define RCC_APB2ENR_TIM11EN                 RCC_APB2ENR_TIM11EN_Msk            /*!< TIM11 Timer clock enable */
4598 #define RCC_APB2ENR_ADC1EN_Pos              (9U)
4599 #define RCC_APB2ENR_ADC1EN_Msk              (0x1U << RCC_APB2ENR_ADC1EN_Pos)   /*!< 0x00000200 */
4600 #define RCC_APB2ENR_ADC1EN                  RCC_APB2ENR_ADC1EN_Msk             /*!< ADC1 clock enable */
4601 #define RCC_APB2ENR_SPI1EN_Pos              (12U)
4602 #define RCC_APB2ENR_SPI1EN_Msk              (0x1U << RCC_APB2ENR_SPI1EN_Pos)   /*!< 0x00001000 */
4603 #define RCC_APB2ENR_SPI1EN                  RCC_APB2ENR_SPI1EN_Msk             /*!< SPI1 clock enable */
4604 #define RCC_APB2ENR_USART1EN_Pos            (14U)
4605 #define RCC_APB2ENR_USART1EN_Msk            (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
4606 #define RCC_APB2ENR_USART1EN                RCC_APB2ENR_USART1EN_Msk           /*!< USART1 clock enable */
4607 
4608 /*****************  Bit definition for RCC_APB1ENR register  ******************/
4609 #define RCC_APB1ENR_TIM2EN_Pos              (0U)
4610 #define RCC_APB1ENR_TIM2EN_Msk              (0x1U << RCC_APB1ENR_TIM2EN_Pos)   /*!< 0x00000001 */
4611 #define RCC_APB1ENR_TIM2EN                  RCC_APB1ENR_TIM2EN_Msk             /*!< Timer 2 clock enabled*/
4612 #define RCC_APB1ENR_TIM3EN_Pos              (1U)
4613 #define RCC_APB1ENR_TIM3EN_Msk              (0x1U << RCC_APB1ENR_TIM3EN_Pos)   /*!< 0x00000002 */
4614 #define RCC_APB1ENR_TIM3EN                  RCC_APB1ENR_TIM3EN_Msk             /*!< Timer 3 clock enable */
4615 #define RCC_APB1ENR_TIM4EN_Pos              (2U)
4616 #define RCC_APB1ENR_TIM4EN_Msk              (0x1U << RCC_APB1ENR_TIM4EN_Pos)   /*!< 0x00000004 */
4617 #define RCC_APB1ENR_TIM4EN                  RCC_APB1ENR_TIM4EN_Msk             /*!< Timer 4 clock enable */
4618 #define RCC_APB1ENR_TIM5EN_Pos              (3U)
4619 #define RCC_APB1ENR_TIM5EN_Msk              (0x1U << RCC_APB1ENR_TIM5EN_Pos)   /*!< 0x00000008 */
4620 #define RCC_APB1ENR_TIM5EN                  RCC_APB1ENR_TIM5EN_Msk             /*!< Timer 5 clock enable */
4621 #define RCC_APB1ENR_TIM6EN_Pos              (4U)
4622 #define RCC_APB1ENR_TIM6EN_Msk              (0x1U << RCC_APB1ENR_TIM6EN_Pos)   /*!< 0x00000010 */
4623 #define RCC_APB1ENR_TIM6EN                  RCC_APB1ENR_TIM6EN_Msk             /*!< Timer 6 clock enable */
4624 #define RCC_APB1ENR_TIM7EN_Pos              (5U)
4625 #define RCC_APB1ENR_TIM7EN_Msk              (0x1U << RCC_APB1ENR_TIM7EN_Pos)   /*!< 0x00000020 */
4626 #define RCC_APB1ENR_TIM7EN                  RCC_APB1ENR_TIM7EN_Msk             /*!< Timer 7 clock enable */
4627 #define RCC_APB1ENR_LCDEN_Pos               (9U)
4628 #define RCC_APB1ENR_LCDEN_Msk               (0x1U << RCC_APB1ENR_LCDEN_Pos)    /*!< 0x00000200 */
4629 #define RCC_APB1ENR_LCDEN                   RCC_APB1ENR_LCDEN_Msk              /*!< LCD clock enable */
4630 #define RCC_APB1ENR_WWDGEN_Pos              (11U)
4631 #define RCC_APB1ENR_WWDGEN_Msk              (0x1U << RCC_APB1ENR_WWDGEN_Pos)   /*!< 0x00000800 */
4632 #define RCC_APB1ENR_WWDGEN                  RCC_APB1ENR_WWDGEN_Msk             /*!< Window Watchdog clock enable */
4633 #define RCC_APB1ENR_SPI2EN_Pos              (14U)
4634 #define RCC_APB1ENR_SPI2EN_Msk              (0x1U << RCC_APB1ENR_SPI2EN_Pos)   /*!< 0x00004000 */
4635 #define RCC_APB1ENR_SPI2EN                  RCC_APB1ENR_SPI2EN_Msk             /*!< SPI 2 clock enable */
4636 #define RCC_APB1ENR_SPI3EN_Pos              (15U)
4637 #define RCC_APB1ENR_SPI3EN_Msk              (0x1U << RCC_APB1ENR_SPI3EN_Pos)   /*!< 0x00008000 */
4638 #define RCC_APB1ENR_SPI3EN                  RCC_APB1ENR_SPI3EN_Msk             /*!< SPI 3 clock enable */
4639 #define RCC_APB1ENR_USART2EN_Pos            (17U)
4640 #define RCC_APB1ENR_USART2EN_Msk            (0x1U << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */
4641 #define RCC_APB1ENR_USART2EN                RCC_APB1ENR_USART2EN_Msk           /*!< USART 2 clock enable */
4642 #define RCC_APB1ENR_USART3EN_Pos            (18U)
4643 #define RCC_APB1ENR_USART3EN_Msk            (0x1U << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */
4644 #define RCC_APB1ENR_USART3EN                RCC_APB1ENR_USART3EN_Msk           /*!< USART 3 clock enable */
4645 #define RCC_APB1ENR_I2C1EN_Pos              (21U)
4646 #define RCC_APB1ENR_I2C1EN_Msk              (0x1U << RCC_APB1ENR_I2C1EN_Pos)   /*!< 0x00200000 */
4647 #define RCC_APB1ENR_I2C1EN                  RCC_APB1ENR_I2C1EN_Msk             /*!< I2C 1 clock enable */
4648 #define RCC_APB1ENR_I2C2EN_Pos              (22U)
4649 #define RCC_APB1ENR_I2C2EN_Msk              (0x1U << RCC_APB1ENR_I2C2EN_Pos)   /*!< 0x00400000 */
4650 #define RCC_APB1ENR_I2C2EN                  RCC_APB1ENR_I2C2EN_Msk             /*!< I2C 2 clock enable */
4651 #define RCC_APB1ENR_USBEN_Pos               (23U)
4652 #define RCC_APB1ENR_USBEN_Msk               (0x1U << RCC_APB1ENR_USBEN_Pos)    /*!< 0x00800000 */
4653 #define RCC_APB1ENR_USBEN                   RCC_APB1ENR_USBEN_Msk              /*!< USB clock enable */
4654 #define RCC_APB1ENR_PWREN_Pos               (28U)
4655 #define RCC_APB1ENR_PWREN_Msk               (0x1U << RCC_APB1ENR_PWREN_Pos)    /*!< 0x10000000 */
4656 #define RCC_APB1ENR_PWREN                   RCC_APB1ENR_PWREN_Msk              /*!< Power interface clock enable */
4657 #define RCC_APB1ENR_DACEN_Pos               (29U)
4658 #define RCC_APB1ENR_DACEN_Msk               (0x1U << RCC_APB1ENR_DACEN_Pos)    /*!< 0x20000000 */
4659 #define RCC_APB1ENR_DACEN                   RCC_APB1ENR_DACEN_Msk              /*!< DAC interface clock enable */
4660 #define RCC_APB1ENR_COMPEN_Pos              (31U)
4661 #define RCC_APB1ENR_COMPEN_Msk              (0x1U << RCC_APB1ENR_COMPEN_Pos)   /*!< 0x80000000 */
4662 #define RCC_APB1ENR_COMPEN                  RCC_APB1ENR_COMPEN_Msk             /*!< Comparator interface clock enable */
4663 
4664 /******************  Bit definition for RCC_AHBLPENR register  ****************/
4665 #define RCC_AHBLPENR_GPIOALPEN_Pos          (0U)
4666 #define RCC_AHBLPENR_GPIOALPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
4667 #define RCC_AHBLPENR_GPIOALPEN              RCC_AHBLPENR_GPIOALPEN_Msk         /*!< GPIO port A clock enabled in sleep mode */
4668 #define RCC_AHBLPENR_GPIOBLPEN_Pos          (1U)
4669 #define RCC_AHBLPENR_GPIOBLPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
4670 #define RCC_AHBLPENR_GPIOBLPEN              RCC_AHBLPENR_GPIOBLPEN_Msk         /*!< GPIO port B clock enabled in sleep mode */
4671 #define RCC_AHBLPENR_GPIOCLPEN_Pos          (2U)
4672 #define RCC_AHBLPENR_GPIOCLPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
4673 #define RCC_AHBLPENR_GPIOCLPEN              RCC_AHBLPENR_GPIOCLPEN_Msk         /*!< GPIO port C clock enabled in sleep mode */
4674 #define RCC_AHBLPENR_GPIODLPEN_Pos          (3U)
4675 #define RCC_AHBLPENR_GPIODLPEN_Msk          (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
4676 #define RCC_AHBLPENR_GPIODLPEN              RCC_AHBLPENR_GPIODLPEN_Msk         /*!< GPIO port D clock enabled in sleep mode */
4677 #define RCC_AHBLPENR_GPIOELPEN_Pos          (4U)
4678 #define RCC_AHBLPENR_GPIOELPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
4679 #define RCC_AHBLPENR_GPIOELPEN              RCC_AHBLPENR_GPIOELPEN_Msk         /*!< GPIO port E clock enabled in sleep mode */
4680 #define RCC_AHBLPENR_GPIOHLPEN_Pos          (5U)
4681 #define RCC_AHBLPENR_GPIOHLPEN_Msk          (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos) /*!< 0x00000020 */
4682 #define RCC_AHBLPENR_GPIOHLPEN              RCC_AHBLPENR_GPIOHLPEN_Msk         /*!< GPIO port H clock enabled in sleep mode */
4683 #define RCC_AHBLPENR_CRCLPEN_Pos            (12U)
4684 #define RCC_AHBLPENR_CRCLPEN_Msk            (0x1U << RCC_AHBLPENR_CRCLPEN_Pos) /*!< 0x00001000 */
4685 #define RCC_AHBLPENR_CRCLPEN                RCC_AHBLPENR_CRCLPEN_Msk           /*!< CRC clock enabled in sleep mode */
4686 #define RCC_AHBLPENR_FLITFLPEN_Pos          (15U)
4687 #define RCC_AHBLPENR_FLITFLPEN_Msk          (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos) /*!< 0x00008000 */
4688 #define RCC_AHBLPENR_FLITFLPEN              RCC_AHBLPENR_FLITFLPEN_Msk         /*!< Flash Interface clock enabled in sleep mode
4689                                                                                 (has effect only when the Flash memory is
4690                                                                                  in power down mode) */
4691 #define RCC_AHBLPENR_SRAMLPEN_Pos           (16U)
4692 #define RCC_AHBLPENR_SRAMLPEN_Msk           (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos) /*!< 0x00010000 */
4693 #define RCC_AHBLPENR_SRAMLPEN               RCC_AHBLPENR_SRAMLPEN_Msk          /*!< SRAM clock enabled in sleep mode */
4694 #define RCC_AHBLPENR_DMA1LPEN_Pos           (24U)
4695 #define RCC_AHBLPENR_DMA1LPEN_Msk           (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos) /*!< 0x01000000 */
4696 #define RCC_AHBLPENR_DMA1LPEN               RCC_AHBLPENR_DMA1LPEN_Msk          /*!< DMA1 clock enabled in sleep mode */
4697 #define RCC_AHBLPENR_DMA2LPEN_Pos           (25U)
4698 #define RCC_AHBLPENR_DMA2LPEN_Msk           (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos) /*!< 0x02000000 */
4699 #define RCC_AHBLPENR_DMA2LPEN               RCC_AHBLPENR_DMA2LPEN_Msk          /*!< DMA2 clock enabled in sleep mode */
4700 
4701 /******************  Bit definition for RCC_APB2LPENR register  ***************/
4702 #define RCC_APB2LPENR_SYSCFGLPEN_Pos        (0U)
4703 #define RCC_APB2LPENR_SYSCFGLPEN_Msk        (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00000001 */
4704 #define RCC_APB2LPENR_SYSCFGLPEN            RCC_APB2LPENR_SYSCFGLPEN_Msk       /*!< System Configuration SYSCFG clock enabled in sleep mode */
4705 #define RCC_APB2LPENR_TIM9LPEN_Pos          (2U)
4706 #define RCC_APB2LPENR_TIM9LPEN_Msk          (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00000004 */
4707 #define RCC_APB2LPENR_TIM9LPEN              RCC_APB2LPENR_TIM9LPEN_Msk         /*!< TIM9 interface clock enabled in sleep mode */
4708 #define RCC_APB2LPENR_TIM10LPEN_Pos         (3U)
4709 #define RCC_APB2LPENR_TIM10LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00000008 */
4710 #define RCC_APB2LPENR_TIM10LPEN             RCC_APB2LPENR_TIM10LPEN_Msk        /*!< TIM10 interface clock enabled in sleep mode */
4711 #define RCC_APB2LPENR_TIM11LPEN_Pos         (4U)
4712 #define RCC_APB2LPENR_TIM11LPEN_Msk         (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00000010 */
4713 #define RCC_APB2LPENR_TIM11LPEN             RCC_APB2LPENR_TIM11LPEN_Msk        /*!< TIM11 Timer clock enabled in sleep mode */
4714 #define RCC_APB2LPENR_ADC1LPEN_Pos          (9U)
4715 #define RCC_APB2LPENR_ADC1LPEN_Msk          (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000200 */
4716 #define RCC_APB2LPENR_ADC1LPEN              RCC_APB2LPENR_ADC1LPEN_Msk         /*!< ADC1 clock enabled in sleep mode */
4717 #define RCC_APB2LPENR_SPI1LPEN_Pos          (12U)
4718 #define RCC_APB2LPENR_SPI1LPEN_Msk          (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
4719 #define RCC_APB2LPENR_SPI1LPEN              RCC_APB2LPENR_SPI1LPEN_Msk         /*!< SPI1 clock enabled in sleep mode */
4720 #define RCC_APB2LPENR_USART1LPEN_Pos        (14U)
4721 #define RCC_APB2LPENR_USART1LPEN_Msk        (0x1U << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00004000 */
4722 #define RCC_APB2LPENR_USART1LPEN            RCC_APB2LPENR_USART1LPEN_Msk       /*!< USART1 clock enabled in sleep mode */
4723 
4724 /*****************  Bit definition for RCC_APB1LPENR register  ****************/
4725 #define RCC_APB1LPENR_TIM2LPEN_Pos          (0U)
4726 #define RCC_APB1LPENR_TIM2LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
4727 #define RCC_APB1LPENR_TIM2LPEN              RCC_APB1LPENR_TIM2LPEN_Msk         /*!< Timer 2 clock enabled in sleep mode */
4728 #define RCC_APB1LPENR_TIM3LPEN_Pos          (1U)
4729 #define RCC_APB1LPENR_TIM3LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
4730 #define RCC_APB1LPENR_TIM3LPEN              RCC_APB1LPENR_TIM3LPEN_Msk         /*!< Timer 3 clock enabled in sleep mode */
4731 #define RCC_APB1LPENR_TIM4LPEN_Pos          (2U)
4732 #define RCC_APB1LPENR_TIM4LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
4733 #define RCC_APB1LPENR_TIM4LPEN              RCC_APB1LPENR_TIM4LPEN_Msk         /*!< Timer 4 clock enabled in sleep mode */
4734 #define RCC_APB1LPENR_TIM5LPEN_Pos          (3U)
4735 #define RCC_APB1LPENR_TIM5LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
4736 #define RCC_APB1LPENR_TIM5LPEN              RCC_APB1LPENR_TIM5LPEN_Msk         /*!< Timer 5 clock enabled in sleep mode */
4737 #define RCC_APB1LPENR_TIM6LPEN_Pos          (4U)
4738 #define RCC_APB1LPENR_TIM6LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
4739 #define RCC_APB1LPENR_TIM6LPEN              RCC_APB1LPENR_TIM6LPEN_Msk         /*!< Timer 6 clock enabled in sleep mode */
4740 #define RCC_APB1LPENR_TIM7LPEN_Pos          (5U)
4741 #define RCC_APB1LPENR_TIM7LPEN_Msk          (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
4742 #define RCC_APB1LPENR_TIM7LPEN              RCC_APB1LPENR_TIM7LPEN_Msk         /*!< Timer 7 clock enabled in sleep mode */
4743 #define RCC_APB1LPENR_LCDLPEN_Pos           (9U)
4744 #define RCC_APB1LPENR_LCDLPEN_Msk           (0x1U << RCC_APB1LPENR_LCDLPEN_Pos) /*!< 0x00000200 */
4745 #define RCC_APB1LPENR_LCDLPEN               RCC_APB1LPENR_LCDLPEN_Msk          /*!< LCD clock enabled in sleep mode */
4746 #define RCC_APB1LPENR_WWDGLPEN_Pos          (11U)
4747 #define RCC_APB1LPENR_WWDGLPEN_Msk          (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */
4748 #define RCC_APB1LPENR_WWDGLPEN              RCC_APB1LPENR_WWDGLPEN_Msk         /*!< Window Watchdog clock enabled in sleep mode */
4749 #define RCC_APB1LPENR_SPI2LPEN_Pos          (14U)
4750 #define RCC_APB1LPENR_SPI2LPEN_Msk          (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
4751 #define RCC_APB1LPENR_SPI2LPEN              RCC_APB1LPENR_SPI2LPEN_Msk         /*!< SPI 2 clock enabled in sleep mode */
4752 #define RCC_APB1LPENR_SPI3LPEN_Pos          (15U)
4753 #define RCC_APB1LPENR_SPI3LPEN_Msk          (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
4754 #define RCC_APB1LPENR_SPI3LPEN              RCC_APB1LPENR_SPI3LPEN_Msk         /*!< SPI 3 clock enabled in sleep mode */
4755 #define RCC_APB1LPENR_USART2LPEN_Pos        (17U)
4756 #define RCC_APB1LPENR_USART2LPEN_Msk        (0x1U << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */
4757 #define RCC_APB1LPENR_USART2LPEN            RCC_APB1LPENR_USART2LPEN_Msk       /*!< USART 2 clock enabled in sleep mode */
4758 #define RCC_APB1LPENR_USART3LPEN_Pos        (18U)
4759 #define RCC_APB1LPENR_USART3LPEN_Msk        (0x1U << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */
4760 #define RCC_APB1LPENR_USART3LPEN            RCC_APB1LPENR_USART3LPEN_Msk       /*!< USART 3 clock enabled in sleep mode */
4761 #define RCC_APB1LPENR_I2C1LPEN_Pos          (21U)
4762 #define RCC_APB1LPENR_I2C1LPEN_Msk          (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
4763 #define RCC_APB1LPENR_I2C1LPEN              RCC_APB1LPENR_I2C1LPEN_Msk         /*!< I2C 1 clock enabled in sleep mode */
4764 #define RCC_APB1LPENR_I2C2LPEN_Pos          (22U)
4765 #define RCC_APB1LPENR_I2C2LPEN_Msk          (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
4766 #define RCC_APB1LPENR_I2C2LPEN              RCC_APB1LPENR_I2C2LPEN_Msk         /*!< I2C 2 clock enabled in sleep mode */
4767 #define RCC_APB1LPENR_USBLPEN_Pos           (23U)
4768 #define RCC_APB1LPENR_USBLPEN_Msk           (0x1U << RCC_APB1LPENR_USBLPEN_Pos) /*!< 0x00800000 */
4769 #define RCC_APB1LPENR_USBLPEN               RCC_APB1LPENR_USBLPEN_Msk          /*!< USB clock enabled in sleep mode */
4770 #define RCC_APB1LPENR_PWRLPEN_Pos           (28U)
4771 #define RCC_APB1LPENR_PWRLPEN_Msk           (0x1U << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */
4772 #define RCC_APB1LPENR_PWRLPEN               RCC_APB1LPENR_PWRLPEN_Msk          /*!< Power interface clock enabled in sleep mode */
4773 #define RCC_APB1LPENR_DACLPEN_Pos           (29U)
4774 #define RCC_APB1LPENR_DACLPEN_Msk           (0x1U << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */
4775 #define RCC_APB1LPENR_DACLPEN               RCC_APB1LPENR_DACLPEN_Msk          /*!< DAC interface clock enabled in sleep mode */
4776 #define RCC_APB1LPENR_COMPLPEN_Pos          (31U)
4777 #define RCC_APB1LPENR_COMPLPEN_Msk          (0x1U << RCC_APB1LPENR_COMPLPEN_Pos) /*!< 0x80000000 */
4778 #define RCC_APB1LPENR_COMPLPEN              RCC_APB1LPENR_COMPLPEN_Msk         /*!< Comparator interface clock enabled in sleep mode*/
4779 
4780 /*******************  Bit definition for RCC_CSR register  ********************/
4781 #define RCC_CSR_LSION_Pos                   (0U)
4782 #define RCC_CSR_LSION_Msk                   (0x1U << RCC_CSR_LSION_Pos)        /*!< 0x00000001 */
4783 #define RCC_CSR_LSION                       RCC_CSR_LSION_Msk                  /*!< Internal Low Speed oscillator enable */
4784 #define RCC_CSR_LSIRDY_Pos                  (1U)
4785 #define RCC_CSR_LSIRDY_Msk                  (0x1U << RCC_CSR_LSIRDY_Pos)       /*!< 0x00000002 */
4786 #define RCC_CSR_LSIRDY                      RCC_CSR_LSIRDY_Msk                 /*!< Internal Low Speed oscillator Ready */
4787 
4788 #define RCC_CSR_LSEON_Pos                   (8U)
4789 #define RCC_CSR_LSEON_Msk                   (0x1U << RCC_CSR_LSEON_Pos)        /*!< 0x00000100 */
4790 #define RCC_CSR_LSEON                       RCC_CSR_LSEON_Msk                  /*!< External Low Speed oscillator enable */
4791 #define RCC_CSR_LSERDY_Pos                  (9U)
4792 #define RCC_CSR_LSERDY_Msk                  (0x1U << RCC_CSR_LSERDY_Pos)       /*!< 0x00000200 */
4793 #define RCC_CSR_LSERDY                      RCC_CSR_LSERDY_Msk                 /*!< External Low Speed oscillator Ready */
4794 #define RCC_CSR_LSEBYP_Pos                  (10U)
4795 #define RCC_CSR_LSEBYP_Msk                  (0x1U << RCC_CSR_LSEBYP_Pos)       /*!< 0x00000400 */
4796 #define RCC_CSR_LSEBYP                      RCC_CSR_LSEBYP_Msk                 /*!< External Low Speed oscillator Bypass */
4797 
4798 #define RCC_CSR_LSECSSON_Pos                (11U)
4799 #define RCC_CSR_LSECSSON_Msk                (0x1U << RCC_CSR_LSECSSON_Pos)     /*!< 0x00000800 */
4800 #define RCC_CSR_LSECSSON                    RCC_CSR_LSECSSON_Msk               /*!< External Low Speed oscillator CSS Enable */
4801 #define RCC_CSR_LSECSSD_Pos                 (12U)
4802 #define RCC_CSR_LSECSSD_Msk                 (0x1U << RCC_CSR_LSECSSD_Pos)      /*!< 0x00001000 */
4803 #define RCC_CSR_LSECSSD                     RCC_CSR_LSECSSD_Msk                /*!< External Low Speed oscillator CSS Detected */
4804 
4805 #define RCC_CSR_RTCSEL_Pos                  (16U)
4806 #define RCC_CSR_RTCSEL_Msk                  (0x3U << RCC_CSR_RTCSEL_Pos)       /*!< 0x00030000 */
4807 #define RCC_CSR_RTCSEL                      RCC_CSR_RTCSEL_Msk                 /*!< RTCSEL[1:0] bits (RTC clock source selection) */
4808 #define RCC_CSR_RTCSEL_0                    (0x1U << RCC_CSR_RTCSEL_Pos)       /*!< 0x00010000 */
4809 #define RCC_CSR_RTCSEL_1                    (0x2U << RCC_CSR_RTCSEL_Pos)       /*!< 0x00020000 */
4810 
4811 /*!< RTC congiguration */
4812 #define RCC_CSR_RTCSEL_NOCLOCK              (0x00000000U)                      /*!< No clock */
4813 #define RCC_CSR_RTCSEL_LSE_Pos              (16U)
4814 #define RCC_CSR_RTCSEL_LSE_Msk              (0x1U << RCC_CSR_RTCSEL_LSE_Pos)   /*!< 0x00010000 */
4815 #define RCC_CSR_RTCSEL_LSE                  RCC_CSR_RTCSEL_LSE_Msk             /*!< LSE oscillator clock used as RTC clock */
4816 #define RCC_CSR_RTCSEL_LSI_Pos              (17U)
4817 #define RCC_CSR_RTCSEL_LSI_Msk              (0x1U << RCC_CSR_RTCSEL_LSI_Pos)   /*!< 0x00020000 */
4818 #define RCC_CSR_RTCSEL_LSI                  RCC_CSR_RTCSEL_LSI_Msk             /*!< LSI oscillator clock used as RTC clock */
4819 #define RCC_CSR_RTCSEL_HSE_Pos              (16U)
4820 #define RCC_CSR_RTCSEL_HSE_Msk              (0x3U << RCC_CSR_RTCSEL_HSE_Pos)   /*!< 0x00030000 */
4821 #define RCC_CSR_RTCSEL_HSE                  RCC_CSR_RTCSEL_HSE_Msk             /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
4822 
4823 #define RCC_CSR_RTCEN_Pos                   (22U)
4824 #define RCC_CSR_RTCEN_Msk                   (0x1U << RCC_CSR_RTCEN_Pos)        /*!< 0x00400000 */
4825 #define RCC_CSR_RTCEN                       RCC_CSR_RTCEN_Msk                  /*!< RTC clock enable */
4826 #define RCC_CSR_RTCRST_Pos                  (23U)
4827 #define RCC_CSR_RTCRST_Msk                  (0x1U << RCC_CSR_RTCRST_Pos)       /*!< 0x00800000 */
4828 #define RCC_CSR_RTCRST                      RCC_CSR_RTCRST_Msk                 /*!< RTC reset  */
4829 
4830 #define RCC_CSR_RMVF_Pos                    (24U)
4831 #define RCC_CSR_RMVF_Msk                    (0x1U << RCC_CSR_RMVF_Pos)         /*!< 0x01000000 */
4832 #define RCC_CSR_RMVF                        RCC_CSR_RMVF_Msk                   /*!< Remove reset flag */
4833 #define RCC_CSR_OBLRSTF_Pos                 (25U)
4834 #define RCC_CSR_OBLRSTF_Msk                 (0x1U << RCC_CSR_OBLRSTF_Pos)      /*!< 0x02000000 */
4835 #define RCC_CSR_OBLRSTF                     RCC_CSR_OBLRSTF_Msk                /*!< Option Bytes Loader reset flag */
4836 #define RCC_CSR_PINRSTF_Pos                 (26U)
4837 #define RCC_CSR_PINRSTF_Msk                 (0x1U << RCC_CSR_PINRSTF_Pos)      /*!< 0x04000000 */
4838 #define RCC_CSR_PINRSTF                     RCC_CSR_PINRSTF_Msk                /*!< PIN reset flag */
4839 #define RCC_CSR_PORRSTF_Pos                 (27U)
4840 #define RCC_CSR_PORRSTF_Msk                 (0x1U << RCC_CSR_PORRSTF_Pos)      /*!< 0x08000000 */
4841 #define RCC_CSR_PORRSTF                     RCC_CSR_PORRSTF_Msk                /*!< POR/PDR reset flag */
4842 #define RCC_CSR_SFTRSTF_Pos                 (28U)
4843 #define RCC_CSR_SFTRSTF_Msk                 (0x1U << RCC_CSR_SFTRSTF_Pos)      /*!< 0x10000000 */
4844 #define RCC_CSR_SFTRSTF                     RCC_CSR_SFTRSTF_Msk                /*!< Software Reset flag */
4845 #define RCC_CSR_IWDGRSTF_Pos                (29U)
4846 #define RCC_CSR_IWDGRSTF_Msk                (0x1U << RCC_CSR_IWDGRSTF_Pos)     /*!< 0x20000000 */
4847 #define RCC_CSR_IWDGRSTF                    RCC_CSR_IWDGRSTF_Msk               /*!< Independent Watchdog reset flag */
4848 #define RCC_CSR_WWDGRSTF_Pos                (30U)
4849 #define RCC_CSR_WWDGRSTF_Msk                (0x1U << RCC_CSR_WWDGRSTF_Pos)     /*!< 0x40000000 */
4850 #define RCC_CSR_WWDGRSTF                    RCC_CSR_WWDGRSTF_Msk               /*!< Window watchdog reset flag */
4851 #define RCC_CSR_LPWRRSTF_Pos                (31U)
4852 #define RCC_CSR_LPWRRSTF_Msk                (0x1U << RCC_CSR_LPWRRSTF_Pos)     /*!< 0x80000000 */
4853 #define RCC_CSR_LPWRRSTF                    RCC_CSR_LPWRRSTF_Msk               /*!< Low-Power reset flag */
4854 
4855 /******************************************************************************/
4856 /*                                                                            */
4857 /*                           Real-Time Clock (RTC)                            */
4858 /*                                                                            */
4859 /******************************************************************************/
4860 /*
4861 * @brief Specific device feature definitions  (not present on all devices in the STM32F0 serie)
4862 */
4863 #define RTC_TAMPER1_SUPPORT       /*!< TAMPER 1 feature support */
4864 #define RTC_TAMPER2_SUPPORT       /*!< TAMPER 2 feature support */
4865 #define RTC_TAMPER3_SUPPORT       /*!< TAMPER 3 feature support */
4866 #define RTC_BACKUP_SUPPORT        /*!< BACKUP register feature support */
4867 #define RTC_WAKEUP_SUPPORT        /*!< WAKEUP feature support */
4868 #define RTC_SMOOTHCALIB_SUPPORT   /*!< Smooth digital calibration feature support */
4869 #define RTC_SUBSECOND_SUPPORT     /*!< Sub-second feature support */
4870 
4871 /********************  Bits definition for RTC_TR register  *******************/
4872 #define RTC_TR_PM_Pos                        (22U)
4873 #define RTC_TR_PM_Msk                        (0x1U << RTC_TR_PM_Pos)           /*!< 0x00400000 */
4874 #define RTC_TR_PM                            RTC_TR_PM_Msk
4875 #define RTC_TR_HT_Pos                        (20U)
4876 #define RTC_TR_HT_Msk                        (0x3U << RTC_TR_HT_Pos)           /*!< 0x00300000 */
4877 #define RTC_TR_HT                            RTC_TR_HT_Msk
4878 #define RTC_TR_HT_0                          (0x1U << RTC_TR_HT_Pos)           /*!< 0x00100000 */
4879 #define RTC_TR_HT_1                          (0x2U << RTC_TR_HT_Pos)           /*!< 0x00200000 */
4880 #define RTC_TR_HU_Pos                        (16U)
4881 #define RTC_TR_HU_Msk                        (0xFU << RTC_TR_HU_Pos)           /*!< 0x000F0000 */
4882 #define RTC_TR_HU                            RTC_TR_HU_Msk
4883 #define RTC_TR_HU_0                          (0x1U << RTC_TR_HU_Pos)           /*!< 0x00010000 */
4884 #define RTC_TR_HU_1                          (0x2U << RTC_TR_HU_Pos)           /*!< 0x00020000 */
4885 #define RTC_TR_HU_2                          (0x4U << RTC_TR_HU_Pos)           /*!< 0x00040000 */
4886 #define RTC_TR_HU_3                          (0x8U << RTC_TR_HU_Pos)           /*!< 0x00080000 */
4887 #define RTC_TR_MNT_Pos                       (12U)
4888 #define RTC_TR_MNT_Msk                       (0x7U << RTC_TR_MNT_Pos)          /*!< 0x00007000 */
4889 #define RTC_TR_MNT                           RTC_TR_MNT_Msk
4890 #define RTC_TR_MNT_0                         (0x1U << RTC_TR_MNT_Pos)          /*!< 0x00001000 */
4891 #define RTC_TR_MNT_1                         (0x2U << RTC_TR_MNT_Pos)          /*!< 0x00002000 */
4892 #define RTC_TR_MNT_2                         (0x4U << RTC_TR_MNT_Pos)          /*!< 0x00004000 */
4893 #define RTC_TR_MNU_Pos                       (8U)
4894 #define RTC_TR_MNU_Msk                       (0xFU << RTC_TR_MNU_Pos)          /*!< 0x00000F00 */
4895 #define RTC_TR_MNU                           RTC_TR_MNU_Msk
4896 #define RTC_TR_MNU_0                         (0x1U << RTC_TR_MNU_Pos)          /*!< 0x00000100 */
4897 #define RTC_TR_MNU_1                         (0x2U << RTC_TR_MNU_Pos)          /*!< 0x00000200 */
4898 #define RTC_TR_MNU_2                         (0x4U << RTC_TR_MNU_Pos)          /*!< 0x00000400 */
4899 #define RTC_TR_MNU_3                         (0x8U << RTC_TR_MNU_Pos)          /*!< 0x00000800 */
4900 #define RTC_TR_ST_Pos                        (4U)
4901 #define RTC_TR_ST_Msk                        (0x7U << RTC_TR_ST_Pos)           /*!< 0x00000070 */
4902 #define RTC_TR_ST                            RTC_TR_ST_Msk
4903 #define RTC_TR_ST_0                          (0x1U << RTC_TR_ST_Pos)           /*!< 0x00000010 */
4904 #define RTC_TR_ST_1                          (0x2U << RTC_TR_ST_Pos)           /*!< 0x00000020 */
4905 #define RTC_TR_ST_2                          (0x4U << RTC_TR_ST_Pos)           /*!< 0x00000040 */
4906 #define RTC_TR_SU_Pos                        (0U)
4907 #define RTC_TR_SU_Msk                        (0xFU << RTC_TR_SU_Pos)           /*!< 0x0000000F */
4908 #define RTC_TR_SU                            RTC_TR_SU_Msk
4909 #define RTC_TR_SU_0                          (0x1U << RTC_TR_SU_Pos)           /*!< 0x00000001 */
4910 #define RTC_TR_SU_1                          (0x2U << RTC_TR_SU_Pos)           /*!< 0x00000002 */
4911 #define RTC_TR_SU_2                          (0x4U << RTC_TR_SU_Pos)           /*!< 0x00000004 */
4912 #define RTC_TR_SU_3                          (0x8U << RTC_TR_SU_Pos)           /*!< 0x00000008 */
4913 
4914 /********************  Bits definition for RTC_DR register  *******************/
4915 #define RTC_DR_YT_Pos                        (20U)
4916 #define RTC_DR_YT_Msk                        (0xFU << RTC_DR_YT_Pos)           /*!< 0x00F00000 */
4917 #define RTC_DR_YT                            RTC_DR_YT_Msk
4918 #define RTC_DR_YT_0                          (0x1U << RTC_DR_YT_Pos)           /*!< 0x00100000 */
4919 #define RTC_DR_YT_1                          (0x2U << RTC_DR_YT_Pos)           /*!< 0x00200000 */
4920 #define RTC_DR_YT_2                          (0x4U << RTC_DR_YT_Pos)           /*!< 0x00400000 */
4921 #define RTC_DR_YT_3                          (0x8U << RTC_DR_YT_Pos)           /*!< 0x00800000 */
4922 #define RTC_DR_YU_Pos                        (16U)
4923 #define RTC_DR_YU_Msk                        (0xFU << RTC_DR_YU_Pos)           /*!< 0x000F0000 */
4924 #define RTC_DR_YU                            RTC_DR_YU_Msk
4925 #define RTC_DR_YU_0                          (0x1U << RTC_DR_YU_Pos)           /*!< 0x00010000 */
4926 #define RTC_DR_YU_1                          (0x2U << RTC_DR_YU_Pos)           /*!< 0x00020000 */
4927 #define RTC_DR_YU_2                          (0x4U << RTC_DR_YU_Pos)           /*!< 0x00040000 */
4928 #define RTC_DR_YU_3                          (0x8U << RTC_DR_YU_Pos)           /*!< 0x00080000 */
4929 #define RTC_DR_WDU_Pos                       (13U)
4930 #define RTC_DR_WDU_Msk                       (0x7U << RTC_DR_WDU_Pos)          /*!< 0x0000E000 */
4931 #define RTC_DR_WDU                           RTC_DR_WDU_Msk
4932 #define RTC_DR_WDU_0                         (0x1U << RTC_DR_WDU_Pos)          /*!< 0x00002000 */
4933 #define RTC_DR_WDU_1                         (0x2U << RTC_DR_WDU_Pos)          /*!< 0x00004000 */
4934 #define RTC_DR_WDU_2                         (0x4U << RTC_DR_WDU_Pos)          /*!< 0x00008000 */
4935 #define RTC_DR_MT_Pos                        (12U)
4936 #define RTC_DR_MT_Msk                        (0x1U << RTC_DR_MT_Pos)           /*!< 0x00001000 */
4937 #define RTC_DR_MT                            RTC_DR_MT_Msk
4938 #define RTC_DR_MU_Pos                        (8U)
4939 #define RTC_DR_MU_Msk                        (0xFU << RTC_DR_MU_Pos)           /*!< 0x00000F00 */
4940 #define RTC_DR_MU                            RTC_DR_MU_Msk
4941 #define RTC_DR_MU_0                          (0x1U << RTC_DR_MU_Pos)           /*!< 0x00000100 */
4942 #define RTC_DR_MU_1                          (0x2U << RTC_DR_MU_Pos)           /*!< 0x00000200 */
4943 #define RTC_DR_MU_2                          (0x4U << RTC_DR_MU_Pos)           /*!< 0x00000400 */
4944 #define RTC_DR_MU_3                          (0x8U << RTC_DR_MU_Pos)           /*!< 0x00000800 */
4945 #define RTC_DR_DT_Pos                        (4U)
4946 #define RTC_DR_DT_Msk                        (0x3U << RTC_DR_DT_Pos)           /*!< 0x00000030 */
4947 #define RTC_DR_DT                            RTC_DR_DT_Msk
4948 #define RTC_DR_DT_0                          (0x1U << RTC_DR_DT_Pos)           /*!< 0x00000010 */
4949 #define RTC_DR_DT_1                          (0x2U << RTC_DR_DT_Pos)           /*!< 0x00000020 */
4950 #define RTC_DR_DU_Pos                        (0U)
4951 #define RTC_DR_DU_Msk                        (0xFU << RTC_DR_DU_Pos)           /*!< 0x0000000F */
4952 #define RTC_DR_DU                            RTC_DR_DU_Msk
4953 #define RTC_DR_DU_0                          (0x1U << RTC_DR_DU_Pos)           /*!< 0x00000001 */
4954 #define RTC_DR_DU_1                          (0x2U << RTC_DR_DU_Pos)           /*!< 0x00000002 */
4955 #define RTC_DR_DU_2                          (0x4U << RTC_DR_DU_Pos)           /*!< 0x00000004 */
4956 #define RTC_DR_DU_3                          (0x8U << RTC_DR_DU_Pos)           /*!< 0x00000008 */
4957 
4958 /********************  Bits definition for RTC_CR register  *******************/
4959 #define RTC_CR_COE_Pos                       (23U)
4960 #define RTC_CR_COE_Msk                       (0x1U << RTC_CR_COE_Pos)          /*!< 0x00800000 */
4961 #define RTC_CR_COE                           RTC_CR_COE_Msk
4962 #define RTC_CR_OSEL_Pos                      (21U)
4963 #define RTC_CR_OSEL_Msk                      (0x3U << RTC_CR_OSEL_Pos)         /*!< 0x00600000 */
4964 #define RTC_CR_OSEL                          RTC_CR_OSEL_Msk
4965 #define RTC_CR_OSEL_0                        (0x1U << RTC_CR_OSEL_Pos)         /*!< 0x00200000 */
4966 #define RTC_CR_OSEL_1                        (0x2U << RTC_CR_OSEL_Pos)         /*!< 0x00400000 */
4967 #define RTC_CR_POL_Pos                       (20U)
4968 #define RTC_CR_POL_Msk                       (0x1U << RTC_CR_POL_Pos)          /*!< 0x00100000 */
4969 #define RTC_CR_POL                           RTC_CR_POL_Msk
4970 #define RTC_CR_COSEL_Pos                     (19U)
4971 #define RTC_CR_COSEL_Msk                     (0x1U << RTC_CR_COSEL_Pos)        /*!< 0x00080000 */
4972 #define RTC_CR_COSEL                         RTC_CR_COSEL_Msk
4973 #define RTC_CR_BKP_Pos                       (18U)
4974 #define RTC_CR_BKP_Msk                       (0x1U << RTC_CR_BKP_Pos)          /*!< 0x00040000 */
4975 #define RTC_CR_BKP                           RTC_CR_BKP_Msk
4976 #define RTC_CR_SUB1H_Pos                     (17U)
4977 #define RTC_CR_SUB1H_Msk                     (0x1U << RTC_CR_SUB1H_Pos)        /*!< 0x00020000 */
4978 #define RTC_CR_SUB1H                         RTC_CR_SUB1H_Msk
4979 #define RTC_CR_ADD1H_Pos                     (16U)
4980 #define RTC_CR_ADD1H_Msk                     (0x1U << RTC_CR_ADD1H_Pos)        /*!< 0x00010000 */
4981 #define RTC_CR_ADD1H                         RTC_CR_ADD1H_Msk
4982 #define RTC_CR_TSIE_Pos                      (15U)
4983 #define RTC_CR_TSIE_Msk                      (0x1U << RTC_CR_TSIE_Pos)         /*!< 0x00008000 */
4984 #define RTC_CR_TSIE                          RTC_CR_TSIE_Msk
4985 #define RTC_CR_WUTIE_Pos                     (14U)
4986 #define RTC_CR_WUTIE_Msk                     (0x1U << RTC_CR_WUTIE_Pos)        /*!< 0x00004000 */
4987 #define RTC_CR_WUTIE                         RTC_CR_WUTIE_Msk
4988 #define RTC_CR_ALRBIE_Pos                    (13U)
4989 #define RTC_CR_ALRBIE_Msk                    (0x1U << RTC_CR_ALRBIE_Pos)       /*!< 0x00002000 */
4990 #define RTC_CR_ALRBIE                        RTC_CR_ALRBIE_Msk
4991 #define RTC_CR_ALRAIE_Pos                    (12U)
4992 #define RTC_CR_ALRAIE_Msk                    (0x1U << RTC_CR_ALRAIE_Pos)       /*!< 0x00001000 */
4993 #define RTC_CR_ALRAIE                        RTC_CR_ALRAIE_Msk
4994 #define RTC_CR_TSE_Pos                       (11U)
4995 #define RTC_CR_TSE_Msk                       (0x1U << RTC_CR_TSE_Pos)          /*!< 0x00000800 */
4996 #define RTC_CR_TSE                           RTC_CR_TSE_Msk
4997 #define RTC_CR_WUTE_Pos                      (10U)
4998 #define RTC_CR_WUTE_Msk                      (0x1U << RTC_CR_WUTE_Pos)         /*!< 0x00000400 */
4999 #define RTC_CR_WUTE                          RTC_CR_WUTE_Msk
5000 #define RTC_CR_ALRBE_Pos                     (9U)
5001 #define RTC_CR_ALRBE_Msk                     (0x1U << RTC_CR_ALRBE_Pos)        /*!< 0x00000200 */
5002 #define RTC_CR_ALRBE                         RTC_CR_ALRBE_Msk
5003 #define RTC_CR_ALRAE_Pos                     (8U)
5004 #define RTC_CR_ALRAE_Msk                     (0x1U << RTC_CR_ALRAE_Pos)        /*!< 0x00000100 */
5005 #define RTC_CR_ALRAE                         RTC_CR_ALRAE_Msk
5006 #define RTC_CR_DCE_Pos                       (7U)
5007 #define RTC_CR_DCE_Msk                       (0x1U << RTC_CR_DCE_Pos)          /*!< 0x00000080 */
5008 #define RTC_CR_DCE                           RTC_CR_DCE_Msk
5009 #define RTC_CR_FMT_Pos                       (6U)
5010 #define RTC_CR_FMT_Msk                       (0x1U << RTC_CR_FMT_Pos)          /*!< 0x00000040 */
5011 #define RTC_CR_FMT                           RTC_CR_FMT_Msk
5012 #define RTC_CR_BYPSHAD_Pos                   (5U)
5013 #define RTC_CR_BYPSHAD_Msk                   (0x1U << RTC_CR_BYPSHAD_Pos)      /*!< 0x00000020 */
5014 #define RTC_CR_BYPSHAD                       RTC_CR_BYPSHAD_Msk
5015 #define RTC_CR_REFCKON_Pos                   (4U)
5016 #define RTC_CR_REFCKON_Msk                   (0x1U << RTC_CR_REFCKON_Pos)      /*!< 0x00000010 */
5017 #define RTC_CR_REFCKON                       RTC_CR_REFCKON_Msk
5018 #define RTC_CR_TSEDGE_Pos                    (3U)
5019 #define RTC_CR_TSEDGE_Msk                    (0x1U << RTC_CR_TSEDGE_Pos)       /*!< 0x00000008 */
5020 #define RTC_CR_TSEDGE                        RTC_CR_TSEDGE_Msk
5021 #define RTC_CR_WUCKSEL_Pos                   (0U)
5022 #define RTC_CR_WUCKSEL_Msk                   (0x7U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000007 */
5023 #define RTC_CR_WUCKSEL                       RTC_CR_WUCKSEL_Msk
5024 #define RTC_CR_WUCKSEL_0                     (0x1U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000001 */
5025 #define RTC_CR_WUCKSEL_1                     (0x2U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000002 */
5026 #define RTC_CR_WUCKSEL_2                     (0x4U << RTC_CR_WUCKSEL_Pos)      /*!< 0x00000004 */
5027 
5028 /* Legacy defines */
5029 #define  RTC_CR_BCK_Pos RTC_CR_BKP_Pos
5030 #define  RTC_CR_BCK_Msk RTC_CR_BKP_Msk
5031 #define  RTC_CR_BCK     RTC_CR_BKP
5032 
5033 /********************  Bits definition for RTC_ISR register  ******************/
5034 #define RTC_ISR_RECALPF_Pos                  (16U)
5035 #define RTC_ISR_RECALPF_Msk                  (0x1U << RTC_ISR_RECALPF_Pos)     /*!< 0x00010000 */
5036 #define RTC_ISR_RECALPF                      RTC_ISR_RECALPF_Msk
5037 #define RTC_ISR_TAMP3F_Pos                   (15U)
5038 #define RTC_ISR_TAMP3F_Msk                   (0x1U << RTC_ISR_TAMP3F_Pos)      /*!< 0x00008000 */
5039 #define RTC_ISR_TAMP3F                       RTC_ISR_TAMP3F_Msk
5040 #define RTC_ISR_TAMP2F_Pos                   (14U)
5041 #define RTC_ISR_TAMP2F_Msk                   (0x1U << RTC_ISR_TAMP2F_Pos)      /*!< 0x00004000 */
5042 #define RTC_ISR_TAMP2F                       RTC_ISR_TAMP2F_Msk
5043 #define RTC_ISR_TAMP1F_Pos                   (13U)
5044 #define RTC_ISR_TAMP1F_Msk                   (0x1U << RTC_ISR_TAMP1F_Pos)      /*!< 0x00002000 */
5045 #define RTC_ISR_TAMP1F                       RTC_ISR_TAMP1F_Msk
5046 #define RTC_ISR_TSOVF_Pos                    (12U)
5047 #define RTC_ISR_TSOVF_Msk                    (0x1U << RTC_ISR_TSOVF_Pos)       /*!< 0x00001000 */
5048 #define RTC_ISR_TSOVF                        RTC_ISR_TSOVF_Msk
5049 #define RTC_ISR_TSF_Pos                      (11U)
5050 #define RTC_ISR_TSF_Msk                      (0x1U << RTC_ISR_TSF_Pos)         /*!< 0x00000800 */
5051 #define RTC_ISR_TSF                          RTC_ISR_TSF_Msk
5052 #define RTC_ISR_WUTF_Pos                     (10U)
5053 #define RTC_ISR_WUTF_Msk                     (0x1U << RTC_ISR_WUTF_Pos)        /*!< 0x00000400 */
5054 #define RTC_ISR_WUTF                         RTC_ISR_WUTF_Msk
5055 #define RTC_ISR_ALRBF_Pos                    (9U)
5056 #define RTC_ISR_ALRBF_Msk                    (0x1U << RTC_ISR_ALRBF_Pos)       /*!< 0x00000200 */
5057 #define RTC_ISR_ALRBF                        RTC_ISR_ALRBF_Msk
5058 #define RTC_ISR_ALRAF_Pos                    (8U)
5059 #define RTC_ISR_ALRAF_Msk                    (0x1U << RTC_ISR_ALRAF_Pos)       /*!< 0x00000100 */
5060 #define RTC_ISR_ALRAF                        RTC_ISR_ALRAF_Msk
5061 #define RTC_ISR_INIT_Pos                     (7U)
5062 #define RTC_ISR_INIT_Msk                     (0x1U << RTC_ISR_INIT_Pos)        /*!< 0x00000080 */
5063 #define RTC_ISR_INIT                         RTC_ISR_INIT_Msk
5064 #define RTC_ISR_INITF_Pos                    (6U)
5065 #define RTC_ISR_INITF_Msk                    (0x1U << RTC_ISR_INITF_Pos)       /*!< 0x00000040 */
5066 #define RTC_ISR_INITF                        RTC_ISR_INITF_Msk
5067 #define RTC_ISR_RSF_Pos                      (5U)
5068 #define RTC_ISR_RSF_Msk                      (0x1U << RTC_ISR_RSF_Pos)         /*!< 0x00000020 */
5069 #define RTC_ISR_RSF                          RTC_ISR_RSF_Msk
5070 #define RTC_ISR_INITS_Pos                    (4U)
5071 #define RTC_ISR_INITS_Msk                    (0x1U << RTC_ISR_INITS_Pos)       /*!< 0x00000010 */
5072 #define RTC_ISR_INITS                        RTC_ISR_INITS_Msk
5073 #define RTC_ISR_SHPF_Pos                     (3U)
5074 #define RTC_ISR_SHPF_Msk                     (0x1U << RTC_ISR_SHPF_Pos)        /*!< 0x00000008 */
5075 #define RTC_ISR_SHPF                         RTC_ISR_SHPF_Msk
5076 #define RTC_ISR_WUTWF_Pos                    (2U)
5077 #define RTC_ISR_WUTWF_Msk                    (0x1U << RTC_ISR_WUTWF_Pos)       /*!< 0x00000004 */
5078 #define RTC_ISR_WUTWF                        RTC_ISR_WUTWF_Msk
5079 #define RTC_ISR_ALRBWF_Pos                   (1U)
5080 #define RTC_ISR_ALRBWF_Msk                   (0x1U << RTC_ISR_ALRBWF_Pos)      /*!< 0x00000002 */
5081 #define RTC_ISR_ALRBWF                       RTC_ISR_ALRBWF_Msk
5082 #define RTC_ISR_ALRAWF_Pos                   (0U)
5083 #define RTC_ISR_ALRAWF_Msk                   (0x1U << RTC_ISR_ALRAWF_Pos)      /*!< 0x00000001 */
5084 #define RTC_ISR_ALRAWF                       RTC_ISR_ALRAWF_Msk
5085 
5086 /********************  Bits definition for RTC_PRER register  *****************/
5087 #define RTC_PRER_PREDIV_A_Pos                (16U)
5088 #define RTC_PRER_PREDIV_A_Msk                (0x7FU << RTC_PRER_PREDIV_A_Pos)  /*!< 0x007F0000 */
5089 #define RTC_PRER_PREDIV_A                    RTC_PRER_PREDIV_A_Msk
5090 #define RTC_PRER_PREDIV_S_Pos                (0U)
5091 #define RTC_PRER_PREDIV_S_Msk                (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
5092 #define RTC_PRER_PREDIV_S                    RTC_PRER_PREDIV_S_Msk
5093 
5094 /********************  Bits definition for RTC_WUTR register  *****************/
5095 #define RTC_WUTR_WUT_Pos                     (0U)
5096 #define RTC_WUTR_WUT_Msk                     (0xFFFFU << RTC_WUTR_WUT_Pos)     /*!< 0x0000FFFF */
5097 #define RTC_WUTR_WUT                         RTC_WUTR_WUT_Msk
5098 
5099 /********************  Bits definition for RTC_CALIBR register  ***************/
5100 #define RTC_CALIBR_DCS_Pos                   (7U)
5101 #define RTC_CALIBR_DCS_Msk                   (0x1U << RTC_CALIBR_DCS_Pos)      /*!< 0x00000080 */
5102 #define RTC_CALIBR_DCS                       RTC_CALIBR_DCS_Msk
5103 #define RTC_CALIBR_DC_Pos                    (0U)
5104 #define RTC_CALIBR_DC_Msk                    (0x1FU << RTC_CALIBR_DC_Pos)      /*!< 0x0000001F */
5105 #define RTC_CALIBR_DC                        RTC_CALIBR_DC_Msk
5106 
5107 /********************  Bits definition for RTC_ALRMAR register  ***************/
5108 #define RTC_ALRMAR_MSK4_Pos                  (31U)
5109 #define RTC_ALRMAR_MSK4_Msk                  (0x1U << RTC_ALRMAR_MSK4_Pos)     /*!< 0x80000000 */
5110 #define RTC_ALRMAR_MSK4                      RTC_ALRMAR_MSK4_Msk
5111 #define RTC_ALRMAR_WDSEL_Pos                 (30U)
5112 #define RTC_ALRMAR_WDSEL_Msk                 (0x1U << RTC_ALRMAR_WDSEL_Pos)    /*!< 0x40000000 */
5113 #define RTC_ALRMAR_WDSEL                     RTC_ALRMAR_WDSEL_Msk
5114 #define RTC_ALRMAR_DT_Pos                    (28U)
5115 #define RTC_ALRMAR_DT_Msk                    (0x3U << RTC_ALRMAR_DT_Pos)       /*!< 0x30000000 */
5116 #define RTC_ALRMAR_DT                        RTC_ALRMAR_DT_Msk
5117 #define RTC_ALRMAR_DT_0                      (0x1U << RTC_ALRMAR_DT_Pos)       /*!< 0x10000000 */
5118 #define RTC_ALRMAR_DT_1                      (0x2U << RTC_ALRMAR_DT_Pos)       /*!< 0x20000000 */
5119 #define RTC_ALRMAR_DU_Pos                    (24U)
5120 #define RTC_ALRMAR_DU_Msk                    (0xFU << RTC_ALRMAR_DU_Pos)       /*!< 0x0F000000 */
5121 #define RTC_ALRMAR_DU                        RTC_ALRMAR_DU_Msk
5122 #define RTC_ALRMAR_DU_0                      (0x1U << RTC_ALRMAR_DU_Pos)       /*!< 0x01000000 */
5123 #define RTC_ALRMAR_DU_1                      (0x2U << RTC_ALRMAR_DU_Pos)       /*!< 0x02000000 */
5124 #define RTC_ALRMAR_DU_2                      (0x4U << RTC_ALRMAR_DU_Pos)       /*!< 0x04000000 */
5125 #define RTC_ALRMAR_DU_3                      (0x8U << RTC_ALRMAR_DU_Pos)       /*!< 0x08000000 */
5126 #define RTC_ALRMAR_MSK3_Pos                  (23U)
5127 #define RTC_ALRMAR_MSK3_Msk                  (0x1U << RTC_ALRMAR_MSK3_Pos)     /*!< 0x00800000 */
5128 #define RTC_ALRMAR_MSK3                      RTC_ALRMAR_MSK3_Msk
5129 #define RTC_ALRMAR_PM_Pos                    (22U)
5130 #define RTC_ALRMAR_PM_Msk                    (0x1U << RTC_ALRMAR_PM_Pos)       /*!< 0x00400000 */
5131 #define RTC_ALRMAR_PM                        RTC_ALRMAR_PM_Msk
5132 #define RTC_ALRMAR_HT_Pos                    (20U)
5133 #define RTC_ALRMAR_HT_Msk                    (0x3U << RTC_ALRMAR_HT_Pos)       /*!< 0x00300000 */
5134 #define RTC_ALRMAR_HT                        RTC_ALRMAR_HT_Msk
5135 #define RTC_ALRMAR_HT_0                      (0x1U << RTC_ALRMAR_HT_Pos)       /*!< 0x00100000 */
5136 #define RTC_ALRMAR_HT_1                      (0x2U << RTC_ALRMAR_HT_Pos)       /*!< 0x00200000 */
5137 #define RTC_ALRMAR_HU_Pos                    (16U)
5138 #define RTC_ALRMAR_HU_Msk                    (0xFU << RTC_ALRMAR_HU_Pos)       /*!< 0x000F0000 */
5139 #define RTC_ALRMAR_HU                        RTC_ALRMAR_HU_Msk
5140 #define RTC_ALRMAR_HU_0                      (0x1U << RTC_ALRMAR_HU_Pos)       /*!< 0x00010000 */
5141 #define RTC_ALRMAR_HU_1                      (0x2U << RTC_ALRMAR_HU_Pos)       /*!< 0x00020000 */
5142 #define RTC_ALRMAR_HU_2                      (0x4U << RTC_ALRMAR_HU_Pos)       /*!< 0x00040000 */
5143 #define RTC_ALRMAR_HU_3                      (0x8U << RTC_ALRMAR_HU_Pos)       /*!< 0x00080000 */
5144 #define RTC_ALRMAR_MSK2_Pos                  (15U)
5145 #define RTC_ALRMAR_MSK2_Msk                  (0x1U << RTC_ALRMAR_MSK2_Pos)     /*!< 0x00008000 */
5146 #define RTC_ALRMAR_MSK2                      RTC_ALRMAR_MSK2_Msk
5147 #define RTC_ALRMAR_MNT_Pos                   (12U)
5148 #define RTC_ALRMAR_MNT_Msk                   (0x7U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00007000 */
5149 #define RTC_ALRMAR_MNT                       RTC_ALRMAR_MNT_Msk
5150 #define RTC_ALRMAR_MNT_0                     (0x1U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00001000 */
5151 #define RTC_ALRMAR_MNT_1                     (0x2U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00002000 */
5152 #define RTC_ALRMAR_MNT_2                     (0x4U << RTC_ALRMAR_MNT_Pos)      /*!< 0x00004000 */
5153 #define RTC_ALRMAR_MNU_Pos                   (8U)
5154 #define RTC_ALRMAR_MNU_Msk                   (0xFU << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000F00 */
5155 #define RTC_ALRMAR_MNU                       RTC_ALRMAR_MNU_Msk
5156 #define RTC_ALRMAR_MNU_0                     (0x1U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000100 */
5157 #define RTC_ALRMAR_MNU_1                     (0x2U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000200 */
5158 #define RTC_ALRMAR_MNU_2                     (0x4U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000400 */
5159 #define RTC_ALRMAR_MNU_3                     (0x8U << RTC_ALRMAR_MNU_Pos)      /*!< 0x00000800 */
5160 #define RTC_ALRMAR_MSK1_Pos                  (7U)
5161 #define RTC_ALRMAR_MSK1_Msk                  (0x1U << RTC_ALRMAR_MSK1_Pos)     /*!< 0x00000080 */
5162 #define RTC_ALRMAR_MSK1                      RTC_ALRMAR_MSK1_Msk
5163 #define RTC_ALRMAR_ST_Pos                    (4U)
5164 #define RTC_ALRMAR_ST_Msk                    (0x7U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000070 */
5165 #define RTC_ALRMAR_ST                        RTC_ALRMAR_ST_Msk
5166 #define RTC_ALRMAR_ST_0                      (0x1U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000010 */
5167 #define RTC_ALRMAR_ST_1                      (0x2U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000020 */
5168 #define RTC_ALRMAR_ST_2                      (0x4U << RTC_ALRMAR_ST_Pos)       /*!< 0x00000040 */
5169 #define RTC_ALRMAR_SU_Pos                    (0U)
5170 #define RTC_ALRMAR_SU_Msk                    (0xFU << RTC_ALRMAR_SU_Pos)       /*!< 0x0000000F */
5171 #define RTC_ALRMAR_SU                        RTC_ALRMAR_SU_Msk
5172 #define RTC_ALRMAR_SU_0                      (0x1U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000001 */
5173 #define RTC_ALRMAR_SU_1                      (0x2U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000002 */
5174 #define RTC_ALRMAR_SU_2                      (0x4U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000004 */
5175 #define RTC_ALRMAR_SU_3                      (0x8U << RTC_ALRMAR_SU_Pos)       /*!< 0x00000008 */
5176 
5177 /********************  Bits definition for RTC_ALRMBR register  ***************/
5178 #define RTC_ALRMBR_MSK4_Pos                  (31U)
5179 #define RTC_ALRMBR_MSK4_Msk                  (0x1U << RTC_ALRMBR_MSK4_Pos)     /*!< 0x80000000 */
5180 #define RTC_ALRMBR_MSK4                      RTC_ALRMBR_MSK4_Msk
5181 #define RTC_ALRMBR_WDSEL_Pos                 (30U)
5182 #define RTC_ALRMBR_WDSEL_Msk                 (0x1U << RTC_ALRMBR_WDSEL_Pos)    /*!< 0x40000000 */
5183 #define RTC_ALRMBR_WDSEL                     RTC_ALRMBR_WDSEL_Msk
5184 #define RTC_ALRMBR_DT_Pos                    (28U)
5185 #define RTC_ALRMBR_DT_Msk                    (0x3U << RTC_ALRMBR_DT_Pos)       /*!< 0x30000000 */
5186 #define RTC_ALRMBR_DT                        RTC_ALRMBR_DT_Msk
5187 #define RTC_ALRMBR_DT_0                      (0x1U << RTC_ALRMBR_DT_Pos)       /*!< 0x10000000 */
5188 #define RTC_ALRMBR_DT_1                      (0x2U << RTC_ALRMBR_DT_Pos)       /*!< 0x20000000 */
5189 #define RTC_ALRMBR_DU_Pos                    (24U)
5190 #define RTC_ALRMBR_DU_Msk                    (0xFU << RTC_ALRMBR_DU_Pos)       /*!< 0x0F000000 */
5191 #define RTC_ALRMBR_DU                        RTC_ALRMBR_DU_Msk
5192 #define RTC_ALRMBR_DU_0                      (0x1U << RTC_ALRMBR_DU_Pos)       /*!< 0x01000000 */
5193 #define RTC_ALRMBR_DU_1                      (0x2U << RTC_ALRMBR_DU_Pos)       /*!< 0x02000000 */
5194 #define RTC_ALRMBR_DU_2                      (0x4U << RTC_ALRMBR_DU_Pos)       /*!< 0x04000000 */
5195 #define RTC_ALRMBR_DU_3                      (0x8U << RTC_ALRMBR_DU_Pos)       /*!< 0x08000000 */
5196 #define RTC_ALRMBR_MSK3_Pos                  (23U)
5197 #define RTC_ALRMBR_MSK3_Msk                  (0x1U << RTC_ALRMBR_MSK3_Pos)     /*!< 0x00800000 */
5198 #define RTC_ALRMBR_MSK3                      RTC_ALRMBR_MSK3_Msk
5199 #define RTC_ALRMBR_PM_Pos                    (22U)
5200 #define RTC_ALRMBR_PM_Msk                    (0x1U << RTC_ALRMBR_PM_Pos)       /*!< 0x00400000 */
5201 #define RTC_ALRMBR_PM                        RTC_ALRMBR_PM_Msk
5202 #define RTC_ALRMBR_HT_Pos                    (20U)
5203 #define RTC_ALRMBR_HT_Msk                    (0x3U << RTC_ALRMBR_HT_Pos)       /*!< 0x00300000 */
5204 #define RTC_ALRMBR_HT                        RTC_ALRMBR_HT_Msk
5205 #define RTC_ALRMBR_HT_0                      (0x1U << RTC_ALRMBR_HT_Pos)       /*!< 0x00100000 */
5206 #define RTC_ALRMBR_HT_1                      (0x2U << RTC_ALRMBR_HT_Pos)       /*!< 0x00200000 */
5207 #define RTC_ALRMBR_HU_Pos                    (16U)
5208 #define RTC_ALRMBR_HU_Msk                    (0xFU << RTC_ALRMBR_HU_Pos)       /*!< 0x000F0000 */
5209 #define RTC_ALRMBR_HU                        RTC_ALRMBR_HU_Msk
5210 #define RTC_ALRMBR_HU_0                      (0x1U << RTC_ALRMBR_HU_Pos)       /*!< 0x00010000 */
5211 #define RTC_ALRMBR_HU_1                      (0x2U << RTC_ALRMBR_HU_Pos)       /*!< 0x00020000 */
5212 #define RTC_ALRMBR_HU_2                      (0x4U << RTC_ALRMBR_HU_Pos)       /*!< 0x00040000 */
5213 #define RTC_ALRMBR_HU_3                      (0x8U << RTC_ALRMBR_HU_Pos)       /*!< 0x00080000 */
5214 #define RTC_ALRMBR_MSK2_Pos                  (15U)
5215 #define RTC_ALRMBR_MSK2_Msk                  (0x1U << RTC_ALRMBR_MSK2_Pos)     /*!< 0x00008000 */
5216 #define RTC_ALRMBR_MSK2                      RTC_ALRMBR_MSK2_Msk
5217 #define RTC_ALRMBR_MNT_Pos                   (12U)
5218 #define RTC_ALRMBR_MNT_Msk                   (0x7U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00007000 */
5219 #define RTC_ALRMBR_MNT                       RTC_ALRMBR_MNT_Msk
5220 #define RTC_ALRMBR_MNT_0                     (0x1U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00001000 */
5221 #define RTC_ALRMBR_MNT_1                     (0x2U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00002000 */
5222 #define RTC_ALRMBR_MNT_2                     (0x4U << RTC_ALRMBR_MNT_Pos)      /*!< 0x00004000 */
5223 #define RTC_ALRMBR_MNU_Pos                   (8U)
5224 #define RTC_ALRMBR_MNU_Msk                   (0xFU << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000F00 */
5225 #define RTC_ALRMBR_MNU                       RTC_ALRMBR_MNU_Msk
5226 #define RTC_ALRMBR_MNU_0                     (0x1U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000100 */
5227 #define RTC_ALRMBR_MNU_1                     (0x2U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000200 */
5228 #define RTC_ALRMBR_MNU_2                     (0x4U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000400 */
5229 #define RTC_ALRMBR_MNU_3                     (0x8U << RTC_ALRMBR_MNU_Pos)      /*!< 0x00000800 */
5230 #define RTC_ALRMBR_MSK1_Pos                  (7U)
5231 #define RTC_ALRMBR_MSK1_Msk                  (0x1U << RTC_ALRMBR_MSK1_Pos)     /*!< 0x00000080 */
5232 #define RTC_ALRMBR_MSK1                      RTC_ALRMBR_MSK1_Msk
5233 #define RTC_ALRMBR_ST_Pos                    (4U)
5234 #define RTC_ALRMBR_ST_Msk                    (0x7U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000070 */
5235 #define RTC_ALRMBR_ST                        RTC_ALRMBR_ST_Msk
5236 #define RTC_ALRMBR_ST_0                      (0x1U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000010 */
5237 #define RTC_ALRMBR_ST_1                      (0x2U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000020 */
5238 #define RTC_ALRMBR_ST_2                      (0x4U << RTC_ALRMBR_ST_Pos)       /*!< 0x00000040 */
5239 #define RTC_ALRMBR_SU_Pos                    (0U)
5240 #define RTC_ALRMBR_SU_Msk                    (0xFU << RTC_ALRMBR_SU_Pos)       /*!< 0x0000000F */
5241 #define RTC_ALRMBR_SU                        RTC_ALRMBR_SU_Msk
5242 #define RTC_ALRMBR_SU_0                      (0x1U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000001 */
5243 #define RTC_ALRMBR_SU_1                      (0x2U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000002 */
5244 #define RTC_ALRMBR_SU_2                      (0x4U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000004 */
5245 #define RTC_ALRMBR_SU_3                      (0x8U << RTC_ALRMBR_SU_Pos)       /*!< 0x00000008 */
5246 
5247 /********************  Bits definition for RTC_WPR register  ******************/
5248 #define RTC_WPR_KEY_Pos                      (0U)
5249 #define RTC_WPR_KEY_Msk                      (0xFFU << RTC_WPR_KEY_Pos)        /*!< 0x000000FF */
5250 #define RTC_WPR_KEY                          RTC_WPR_KEY_Msk
5251 
5252 /********************  Bits definition for RTC_SSR register  ******************/
5253 #define RTC_SSR_SS_Pos                       (0U)
5254 #define RTC_SSR_SS_Msk                       (0xFFFFU << RTC_SSR_SS_Pos)       /*!< 0x0000FFFF */
5255 #define RTC_SSR_SS                           RTC_SSR_SS_Msk
5256 
5257 /********************  Bits definition for RTC_SHIFTR register  ***************/
5258 #define RTC_SHIFTR_SUBFS_Pos                 (0U)
5259 #define RTC_SHIFTR_SUBFS_Msk                 (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
5260 #define RTC_SHIFTR_SUBFS                     RTC_SHIFTR_SUBFS_Msk
5261 #define RTC_SHIFTR_ADD1S_Pos                 (31U)
5262 #define RTC_SHIFTR_ADD1S_Msk                 (0x1U << RTC_SHIFTR_ADD1S_Pos)    /*!< 0x80000000 */
5263 #define RTC_SHIFTR_ADD1S                     RTC_SHIFTR_ADD1S_Msk
5264 
5265 /********************  Bits definition for RTC_TSTR register  *****************/
5266 #define RTC_TSTR_PM_Pos                      (22U)
5267 #define RTC_TSTR_PM_Msk                      (0x1U << RTC_TSTR_PM_Pos)         /*!< 0x00400000 */
5268 #define RTC_TSTR_PM                          RTC_TSTR_PM_Msk
5269 #define RTC_TSTR_HT_Pos                      (20U)
5270 #define RTC_TSTR_HT_Msk                      (0x3U << RTC_TSTR_HT_Pos)         /*!< 0x00300000 */
5271 #define RTC_TSTR_HT                          RTC_TSTR_HT_Msk
5272 #define RTC_TSTR_HT_0                        (0x1U << RTC_TSTR_HT_Pos)         /*!< 0x00100000 */
5273 #define RTC_TSTR_HT_1                        (0x2U << RTC_TSTR_HT_Pos)         /*!< 0x00200000 */
5274 #define RTC_TSTR_HU_Pos                      (16U)
5275 #define RTC_TSTR_HU_Msk                      (0xFU << RTC_TSTR_HU_Pos)         /*!< 0x000F0000 */
5276 #define RTC_TSTR_HU                          RTC_TSTR_HU_Msk
5277 #define RTC_TSTR_HU_0                        (0x1U << RTC_TSTR_HU_Pos)         /*!< 0x00010000 */
5278 #define RTC_TSTR_HU_1                        (0x2U << RTC_TSTR_HU_Pos)         /*!< 0x00020000 */
5279 #define RTC_TSTR_HU_2                        (0x4U << RTC_TSTR_HU_Pos)         /*!< 0x00040000 */
5280 #define RTC_TSTR_HU_3                        (0x8U << RTC_TSTR_HU_Pos)         /*!< 0x00080000 */
5281 #define RTC_TSTR_MNT_Pos                     (12U)
5282 #define RTC_TSTR_MNT_Msk                     (0x7U << RTC_TSTR_MNT_Pos)        /*!< 0x00007000 */
5283 #define RTC_TSTR_MNT                         RTC_TSTR_MNT_Msk
5284 #define RTC_TSTR_MNT_0                       (0x1U << RTC_TSTR_MNT_Pos)        /*!< 0x00001000 */
5285 #define RTC_TSTR_MNT_1                       (0x2U << RTC_TSTR_MNT_Pos)        /*!< 0x00002000 */
5286 #define RTC_TSTR_MNT_2                       (0x4U << RTC_TSTR_MNT_Pos)        /*!< 0x00004000 */
5287 #define RTC_TSTR_MNU_Pos                     (8U)
5288 #define RTC_TSTR_MNU_Msk                     (0xFU << RTC_TSTR_MNU_Pos)        /*!< 0x00000F00 */
5289 #define RTC_TSTR_MNU                         RTC_TSTR_MNU_Msk
5290 #define RTC_TSTR_MNU_0                       (0x1U << RTC_TSTR_MNU_Pos)        /*!< 0x00000100 */
5291 #define RTC_TSTR_MNU_1                       (0x2U << RTC_TSTR_MNU_Pos)        /*!< 0x00000200 */
5292 #define RTC_TSTR_MNU_2                       (0x4U << RTC_TSTR_MNU_Pos)        /*!< 0x00000400 */
5293 #define RTC_TSTR_MNU_3                       (0x8U << RTC_TSTR_MNU_Pos)        /*!< 0x00000800 */
5294 #define RTC_TSTR_ST_Pos                      (4U)
5295 #define RTC_TSTR_ST_Msk                      (0x7U << RTC_TSTR_ST_Pos)         /*!< 0x00000070 */
5296 #define RTC_TSTR_ST                          RTC_TSTR_ST_Msk
5297 #define RTC_TSTR_ST_0                        (0x1U << RTC_TSTR_ST_Pos)         /*!< 0x00000010 */
5298 #define RTC_TSTR_ST_1                        (0x2U << RTC_TSTR_ST_Pos)         /*!< 0x00000020 */
5299 #define RTC_TSTR_ST_2                        (0x4U << RTC_TSTR_ST_Pos)         /*!< 0x00000040 */
5300 #define RTC_TSTR_SU_Pos                      (0U)
5301 #define RTC_TSTR_SU_Msk                      (0xFU << RTC_TSTR_SU_Pos)         /*!< 0x0000000F */
5302 #define RTC_TSTR_SU                          RTC_TSTR_SU_Msk
5303 #define RTC_TSTR_SU_0                        (0x1U << RTC_TSTR_SU_Pos)         /*!< 0x00000001 */
5304 #define RTC_TSTR_SU_1                        (0x2U << RTC_TSTR_SU_Pos)         /*!< 0x00000002 */
5305 #define RTC_TSTR_SU_2                        (0x4U << RTC_TSTR_SU_Pos)         /*!< 0x00000004 */
5306 #define RTC_TSTR_SU_3                        (0x8U << RTC_TSTR_SU_Pos)         /*!< 0x00000008 */
5307 
5308 /********************  Bits definition for RTC_TSDR register  *****************/
5309 #define RTC_TSDR_WDU_Pos                     (13U)
5310 #define RTC_TSDR_WDU_Msk                     (0x7U << RTC_TSDR_WDU_Pos)        /*!< 0x0000E000 */
5311 #define RTC_TSDR_WDU                         RTC_TSDR_WDU_Msk
5312 #define RTC_TSDR_WDU_0                       (0x1U << RTC_TSDR_WDU_Pos)        /*!< 0x00002000 */
5313 #define RTC_TSDR_WDU_1                       (0x2U << RTC_TSDR_WDU_Pos)        /*!< 0x00004000 */
5314 #define RTC_TSDR_WDU_2                       (0x4U << RTC_TSDR_WDU_Pos)        /*!< 0x00008000 */
5315 #define RTC_TSDR_MT_Pos                      (12U)
5316 #define RTC_TSDR_MT_Msk                      (0x1U << RTC_TSDR_MT_Pos)         /*!< 0x00001000 */
5317 #define RTC_TSDR_MT                          RTC_TSDR_MT_Msk
5318 #define RTC_TSDR_MU_Pos                      (8U)
5319 #define RTC_TSDR_MU_Msk                      (0xFU << RTC_TSDR_MU_Pos)         /*!< 0x00000F00 */
5320 #define RTC_TSDR_MU                          RTC_TSDR_MU_Msk
5321 #define RTC_TSDR_MU_0                        (0x1U << RTC_TSDR_MU_Pos)         /*!< 0x00000100 */
5322 #define RTC_TSDR_MU_1                        (0x2U << RTC_TSDR_MU_Pos)         /*!< 0x00000200 */
5323 #define RTC_TSDR_MU_2                        (0x4U << RTC_TSDR_MU_Pos)         /*!< 0x00000400 */
5324 #define RTC_TSDR_MU_3                        (0x8U << RTC_TSDR_MU_Pos)         /*!< 0x00000800 */
5325 #define RTC_TSDR_DT_Pos                      (4U)
5326 #define RTC_TSDR_DT_Msk                      (0x3U << RTC_TSDR_DT_Pos)         /*!< 0x00000030 */
5327 #define RTC_TSDR_DT                          RTC_TSDR_DT_Msk
5328 #define RTC_TSDR_DT_0                        (0x1U << RTC_TSDR_DT_Pos)         /*!< 0x00000010 */
5329 #define RTC_TSDR_DT_1                        (0x2U << RTC_TSDR_DT_Pos)         /*!< 0x00000020 */
5330 #define RTC_TSDR_DU_Pos                      (0U)
5331 #define RTC_TSDR_DU_Msk                      (0xFU << RTC_TSDR_DU_Pos)         /*!< 0x0000000F */
5332 #define RTC_TSDR_DU                          RTC_TSDR_DU_Msk
5333 #define RTC_TSDR_DU_0                        (0x1U << RTC_TSDR_DU_Pos)         /*!< 0x00000001 */
5334 #define RTC_TSDR_DU_1                        (0x2U << RTC_TSDR_DU_Pos)         /*!< 0x00000002 */
5335 #define RTC_TSDR_DU_2                        (0x4U << RTC_TSDR_DU_Pos)         /*!< 0x00000004 */
5336 #define RTC_TSDR_DU_3                        (0x8U << RTC_TSDR_DU_Pos)         /*!< 0x00000008 */
5337 
5338 /********************  Bits definition for RTC_TSSSR register  ****************/
5339 #define RTC_TSSSR_SS_Pos                     (0U)
5340 #define RTC_TSSSR_SS_Msk                     (0xFFFFU << RTC_TSSSR_SS_Pos)     /*!< 0x0000FFFF */
5341 #define RTC_TSSSR_SS                         RTC_TSSSR_SS_Msk
5342 
5343 /********************  Bits definition for RTC_CAL register  *****************/
5344 #define RTC_CALR_CALP_Pos                    (15U)
5345 #define RTC_CALR_CALP_Msk                    (0x1U << RTC_CALR_CALP_Pos)       /*!< 0x00008000 */
5346 #define RTC_CALR_CALP                        RTC_CALR_CALP_Msk
5347 #define RTC_CALR_CALW8_Pos                   (14U)
5348 #define RTC_CALR_CALW8_Msk                   (0x1U << RTC_CALR_CALW8_Pos)      /*!< 0x00004000 */
5349 #define RTC_CALR_CALW8                       RTC_CALR_CALW8_Msk
5350 #define RTC_CALR_CALW16_Pos                  (13U)
5351 #define RTC_CALR_CALW16_Msk                  (0x1U << RTC_CALR_CALW16_Pos)     /*!< 0x00002000 */
5352 #define RTC_CALR_CALW16                      RTC_CALR_CALW16_Msk
5353 #define RTC_CALR_CALM_Pos                    (0U)
5354 #define RTC_CALR_CALM_Msk                    (0x1FFU << RTC_CALR_CALM_Pos)     /*!< 0x000001FF */
5355 #define RTC_CALR_CALM                        RTC_CALR_CALM_Msk
5356 #define RTC_CALR_CALM_0                      (0x001U << RTC_CALR_CALM_Pos)     /*!< 0x00000001 */
5357 #define RTC_CALR_CALM_1                      (0x002U << RTC_CALR_CALM_Pos)     /*!< 0x00000002 */
5358 #define RTC_CALR_CALM_2                      (0x004U << RTC_CALR_CALM_Pos)     /*!< 0x00000004 */
5359 #define RTC_CALR_CALM_3                      (0x008U << RTC_CALR_CALM_Pos)     /*!< 0x00000008 */
5360 #define RTC_CALR_CALM_4                      (0x010U << RTC_CALR_CALM_Pos)     /*!< 0x00000010 */
5361 #define RTC_CALR_CALM_5                      (0x020U << RTC_CALR_CALM_Pos)     /*!< 0x00000020 */
5362 #define RTC_CALR_CALM_6                      (0x040U << RTC_CALR_CALM_Pos)     /*!< 0x00000040 */
5363 #define RTC_CALR_CALM_7                      (0x080U << RTC_CALR_CALM_Pos)     /*!< 0x00000080 */
5364 #define RTC_CALR_CALM_8                      (0x100U << RTC_CALR_CALM_Pos)     /*!< 0x00000100 */
5365 
5366 /********************  Bits definition for RTC_TAFCR register  ****************/
5367 #define RTC_TAFCR_ALARMOUTTYPE_Pos           (18U)
5368 #define RTC_TAFCR_ALARMOUTTYPE_Msk           (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos) /*!< 0x00040000 */
5369 #define RTC_TAFCR_ALARMOUTTYPE               RTC_TAFCR_ALARMOUTTYPE_Msk
5370 #define RTC_TAFCR_TAMPPUDIS_Pos              (15U)
5371 #define RTC_TAFCR_TAMPPUDIS_Msk              (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
5372 #define RTC_TAFCR_TAMPPUDIS                  RTC_TAFCR_TAMPPUDIS_Msk
5373 #define RTC_TAFCR_TAMPPRCH_Pos               (13U)
5374 #define RTC_TAFCR_TAMPPRCH_Msk               (0x3U << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00006000 */
5375 #define RTC_TAFCR_TAMPPRCH                   RTC_TAFCR_TAMPPRCH_Msk
5376 #define RTC_TAFCR_TAMPPRCH_0                 (0x1U << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00002000 */
5377 #define RTC_TAFCR_TAMPPRCH_1                 (0x2U << RTC_TAFCR_TAMPPRCH_Pos)  /*!< 0x00004000 */
5378 #define RTC_TAFCR_TAMPFLT_Pos                (11U)
5379 #define RTC_TAFCR_TAMPFLT_Msk                (0x3U << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001800 */
5380 #define RTC_TAFCR_TAMPFLT                    RTC_TAFCR_TAMPFLT_Msk
5381 #define RTC_TAFCR_TAMPFLT_0                  (0x1U << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00000800 */
5382 #define RTC_TAFCR_TAMPFLT_1                  (0x2U << RTC_TAFCR_TAMPFLT_Pos)   /*!< 0x00001000 */
5383 #define RTC_TAFCR_TAMPFREQ_Pos               (8U)
5384 #define RTC_TAFCR_TAMPFREQ_Msk               (0x7U << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000700 */
5385 #define RTC_TAFCR_TAMPFREQ                   RTC_TAFCR_TAMPFREQ_Msk
5386 #define RTC_TAFCR_TAMPFREQ_0                 (0x1U << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000100 */
5387 #define RTC_TAFCR_TAMPFREQ_1                 (0x2U << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000200 */
5388 #define RTC_TAFCR_TAMPFREQ_2                 (0x4U << RTC_TAFCR_TAMPFREQ_Pos)  /*!< 0x00000400 */
5389 #define RTC_TAFCR_TAMPTS_Pos                 (7U)
5390 #define RTC_TAFCR_TAMPTS_Msk                 (0x1U << RTC_TAFCR_TAMPTS_Pos)    /*!< 0x00000080 */
5391 #define RTC_TAFCR_TAMPTS                     RTC_TAFCR_TAMPTS_Msk
5392 #define RTC_TAFCR_TAMP3TRG_Pos               (6U)
5393 #define RTC_TAFCR_TAMP3TRG_Msk               (0x1U << RTC_TAFCR_TAMP3TRG_Pos)  /*!< 0x00000040 */
5394 #define RTC_TAFCR_TAMP3TRG                   RTC_TAFCR_TAMP3TRG_Msk
5395 #define RTC_TAFCR_TAMP3E_Pos                 (5U)
5396 #define RTC_TAFCR_TAMP3E_Msk                 (0x1U << RTC_TAFCR_TAMP3E_Pos)    /*!< 0x00000020 */
5397 #define RTC_TAFCR_TAMP3E                     RTC_TAFCR_TAMP3E_Msk
5398 #define RTC_TAFCR_TAMP2TRG_Pos               (4U)
5399 #define RTC_TAFCR_TAMP2TRG_Msk               (0x1U << RTC_TAFCR_TAMP2TRG_Pos)  /*!< 0x00000010 */
5400 #define RTC_TAFCR_TAMP2TRG                   RTC_TAFCR_TAMP2TRG_Msk
5401 #define RTC_TAFCR_TAMP2E_Pos                 (3U)
5402 #define RTC_TAFCR_TAMP2E_Msk                 (0x1U << RTC_TAFCR_TAMP2E_Pos)    /*!< 0x00000008 */
5403 #define RTC_TAFCR_TAMP2E                     RTC_TAFCR_TAMP2E_Msk
5404 #define RTC_TAFCR_TAMPIE_Pos                 (2U)
5405 #define RTC_TAFCR_TAMPIE_Msk                 (0x1U << RTC_TAFCR_TAMPIE_Pos)    /*!< 0x00000004 */
5406 #define RTC_TAFCR_TAMPIE                     RTC_TAFCR_TAMPIE_Msk
5407 #define RTC_TAFCR_TAMP1TRG_Pos               (1U)
5408 #define RTC_TAFCR_TAMP1TRG_Msk               (0x1U << RTC_TAFCR_TAMP1TRG_Pos)  /*!< 0x00000002 */
5409 #define RTC_TAFCR_TAMP1TRG                   RTC_TAFCR_TAMP1TRG_Msk
5410 #define RTC_TAFCR_TAMP1E_Pos                 (0U)
5411 #define RTC_TAFCR_TAMP1E_Msk                 (0x1U << RTC_TAFCR_TAMP1E_Pos)    /*!< 0x00000001 */
5412 #define RTC_TAFCR_TAMP1E                     RTC_TAFCR_TAMP1E_Msk
5413 
5414 /********************  Bits definition for RTC_ALRMASSR register  *************/
5415 #define RTC_ALRMASSR_MASKSS_Pos              (24U)
5416 #define RTC_ALRMASSR_MASKSS_Msk              (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
5417 #define RTC_ALRMASSR_MASKSS                  RTC_ALRMASSR_MASKSS_Msk
5418 #define RTC_ALRMASSR_MASKSS_0                (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
5419 #define RTC_ALRMASSR_MASKSS_1                (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
5420 #define RTC_ALRMASSR_MASKSS_2                (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
5421 #define RTC_ALRMASSR_MASKSS_3                (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
5422 #define RTC_ALRMASSR_SS_Pos                  (0U)
5423 #define RTC_ALRMASSR_SS_Msk                  (0x7FFFU << RTC_ALRMASSR_SS_Pos)  /*!< 0x00007FFF */
5424 #define RTC_ALRMASSR_SS                      RTC_ALRMASSR_SS_Msk
5425 
5426 /********************  Bits definition for RTC_ALRMBSSR register  *************/
5427 #define RTC_ALRMBSSR_MASKSS_Pos              (24U)
5428 #define RTC_ALRMBSSR_MASKSS_Msk              (0xFU << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
5429 #define RTC_ALRMBSSR_MASKSS                  RTC_ALRMBSSR_MASKSS_Msk
5430 #define RTC_ALRMBSSR_MASKSS_0                (0x1U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
5431 #define RTC_ALRMBSSR_MASKSS_1                (0x2U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
5432 #define RTC_ALRMBSSR_MASKSS_2                (0x4U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
5433 #define RTC_ALRMBSSR_MASKSS_3                (0x8U << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
5434 #define RTC_ALRMBSSR_SS_Pos                  (0U)
5435 #define RTC_ALRMBSSR_SS_Msk                  (0x7FFFU << RTC_ALRMBSSR_SS_Pos)  /*!< 0x00007FFF */
5436 #define RTC_ALRMBSSR_SS                      RTC_ALRMBSSR_SS_Msk
5437 
5438 /********************  Bits definition for RTC_BKP0R register  ****************/
5439 #define RTC_BKP0R_Pos                        (0U)
5440 #define RTC_BKP0R_Msk                        (0xFFFFFFFFU << RTC_BKP0R_Pos)    /*!< 0xFFFFFFFF */
5441 #define RTC_BKP0R                            RTC_BKP0R_Msk
5442 
5443 /********************  Bits definition for RTC_BKP1R register  ****************/
5444 #define RTC_BKP1R_Pos                        (0U)
5445 #define RTC_BKP1R_Msk                        (0xFFFFFFFFU << RTC_BKP1R_Pos)    /*!< 0xFFFFFFFF */
5446 #define RTC_BKP1R                            RTC_BKP1R_Msk
5447 
5448 /********************  Bits definition for RTC_BKP2R register  ****************/
5449 #define RTC_BKP2R_Pos                        (0U)
5450 #define RTC_BKP2R_Msk                        (0xFFFFFFFFU << RTC_BKP2R_Pos)    /*!< 0xFFFFFFFF */
5451 #define RTC_BKP2R                            RTC_BKP2R_Msk
5452 
5453 /********************  Bits definition for RTC_BKP3R register  ****************/
5454 #define RTC_BKP3R_Pos                        (0U)
5455 #define RTC_BKP3R_Msk                        (0xFFFFFFFFU << RTC_BKP3R_Pos)    /*!< 0xFFFFFFFF */
5456 #define RTC_BKP3R                            RTC_BKP3R_Msk
5457 
5458 /********************  Bits definition for RTC_BKP4R register  ****************/
5459 #define RTC_BKP4R_Pos                        (0U)
5460 #define RTC_BKP4R_Msk                        (0xFFFFFFFFU << RTC_BKP4R_Pos)    /*!< 0xFFFFFFFF */
5461 #define RTC_BKP4R                            RTC_BKP4R_Msk
5462 
5463 /********************  Bits definition for RTC_BKP5R register  ****************/
5464 #define RTC_BKP5R_Pos                        (0U)
5465 #define RTC_BKP5R_Msk                        (0xFFFFFFFFU << RTC_BKP5R_Pos)    /*!< 0xFFFFFFFF */
5466 #define RTC_BKP5R                            RTC_BKP5R_Msk
5467 
5468 /********************  Bits definition for RTC_BKP6R register  ****************/
5469 #define RTC_BKP6R_Pos                        (0U)
5470 #define RTC_BKP6R_Msk                        (0xFFFFFFFFU << RTC_BKP6R_Pos)    /*!< 0xFFFFFFFF */
5471 #define RTC_BKP6R                            RTC_BKP6R_Msk
5472 
5473 /********************  Bits definition for RTC_BKP7R register  ****************/
5474 #define RTC_BKP7R_Pos                        (0U)
5475 #define RTC_BKP7R_Msk                        (0xFFFFFFFFU << RTC_BKP7R_Pos)    /*!< 0xFFFFFFFF */
5476 #define RTC_BKP7R                            RTC_BKP7R_Msk
5477 
5478 /********************  Bits definition for RTC_BKP8R register  ****************/
5479 #define RTC_BKP8R_Pos                        (0U)
5480 #define RTC_BKP8R_Msk                        (0xFFFFFFFFU << RTC_BKP8R_Pos)    /*!< 0xFFFFFFFF */
5481 #define RTC_BKP8R                            RTC_BKP8R_Msk
5482 
5483 /********************  Bits definition for RTC_BKP9R register  ****************/
5484 #define RTC_BKP9R_Pos                        (0U)
5485 #define RTC_BKP9R_Msk                        (0xFFFFFFFFU << RTC_BKP9R_Pos)    /*!< 0xFFFFFFFF */
5486 #define RTC_BKP9R                            RTC_BKP9R_Msk
5487 
5488 /********************  Bits definition for RTC_BKP10R register  ***************/
5489 #define RTC_BKP10R_Pos                       (0U)
5490 #define RTC_BKP10R_Msk                       (0xFFFFFFFFU << RTC_BKP10R_Pos)   /*!< 0xFFFFFFFF */
5491 #define RTC_BKP10R                           RTC_BKP10R_Msk
5492 
5493 /********************  Bits definition for RTC_BKP11R register  ***************/
5494 #define RTC_BKP11R_Pos                       (0U)
5495 #define RTC_BKP11R_Msk                       (0xFFFFFFFFU << RTC_BKP11R_Pos)   /*!< 0xFFFFFFFF */
5496 #define RTC_BKP11R                           RTC_BKP11R_Msk
5497 
5498 /********************  Bits definition for RTC_BKP12R register  ***************/
5499 #define RTC_BKP12R_Pos                       (0U)
5500 #define RTC_BKP12R_Msk                       (0xFFFFFFFFU << RTC_BKP12R_Pos)   /*!< 0xFFFFFFFF */
5501 #define RTC_BKP12R                           RTC_BKP12R_Msk
5502 
5503 /********************  Bits definition for RTC_BKP13R register  ***************/
5504 #define RTC_BKP13R_Pos                       (0U)
5505 #define RTC_BKP13R_Msk                       (0xFFFFFFFFU << RTC_BKP13R_Pos)   /*!< 0xFFFFFFFF */
5506 #define RTC_BKP13R                           RTC_BKP13R_Msk
5507 
5508 /********************  Bits definition for RTC_BKP14R register  ***************/
5509 #define RTC_BKP14R_Pos                       (0U)
5510 #define RTC_BKP14R_Msk                       (0xFFFFFFFFU << RTC_BKP14R_Pos)   /*!< 0xFFFFFFFF */
5511 #define RTC_BKP14R                           RTC_BKP14R_Msk
5512 
5513 /********************  Bits definition for RTC_BKP15R register  ***************/
5514 #define RTC_BKP15R_Pos                       (0U)
5515 #define RTC_BKP15R_Msk                       (0xFFFFFFFFU << RTC_BKP15R_Pos)   /*!< 0xFFFFFFFF */
5516 #define RTC_BKP15R                           RTC_BKP15R_Msk
5517 
5518 /********************  Bits definition for RTC_BKP16R register  ***************/
5519 #define RTC_BKP16R_Pos                       (0U)
5520 #define RTC_BKP16R_Msk                       (0xFFFFFFFFU << RTC_BKP16R_Pos)   /*!< 0xFFFFFFFF */
5521 #define RTC_BKP16R                           RTC_BKP16R_Msk
5522 
5523 /********************  Bits definition for RTC_BKP17R register  ***************/
5524 #define RTC_BKP17R_Pos                       (0U)
5525 #define RTC_BKP17R_Msk                       (0xFFFFFFFFU << RTC_BKP17R_Pos)   /*!< 0xFFFFFFFF */
5526 #define RTC_BKP17R                           RTC_BKP17R_Msk
5527 
5528 /********************  Bits definition for RTC_BKP18R register  ***************/
5529 #define RTC_BKP18R_Pos                       (0U)
5530 #define RTC_BKP18R_Msk                       (0xFFFFFFFFU << RTC_BKP18R_Pos)   /*!< 0xFFFFFFFF */
5531 #define RTC_BKP18R                           RTC_BKP18R_Msk
5532 
5533 /********************  Bits definition for RTC_BKP19R register  ***************/
5534 #define RTC_BKP19R_Pos                       (0U)
5535 #define RTC_BKP19R_Msk                       (0xFFFFFFFFU << RTC_BKP19R_Pos)   /*!< 0xFFFFFFFF */
5536 #define RTC_BKP19R                           RTC_BKP19R_Msk
5537 
5538 /********************  Bits definition for RTC_BKP20R register  ***************/
5539 #define RTC_BKP20R_Pos                       (0U)
5540 #define RTC_BKP20R_Msk                       (0xFFFFFFFFU << RTC_BKP20R_Pos)   /*!< 0xFFFFFFFF */
5541 #define RTC_BKP20R                           RTC_BKP20R_Msk
5542 
5543 /********************  Bits definition for RTC_BKP21R register  ***************/
5544 #define RTC_BKP21R_Pos                       (0U)
5545 #define RTC_BKP21R_Msk                       (0xFFFFFFFFU << RTC_BKP21R_Pos)   /*!< 0xFFFFFFFF */
5546 #define RTC_BKP21R                           RTC_BKP21R_Msk
5547 
5548 /********************  Bits definition for RTC_BKP22R register  ***************/
5549 #define RTC_BKP22R_Pos                       (0U)
5550 #define RTC_BKP22R_Msk                       (0xFFFFFFFFU << RTC_BKP22R_Pos)   /*!< 0xFFFFFFFF */
5551 #define RTC_BKP22R                           RTC_BKP22R_Msk
5552 
5553 /********************  Bits definition for RTC_BKP23R register  ***************/
5554 #define RTC_BKP23R_Pos                       (0U)
5555 #define RTC_BKP23R_Msk                       (0xFFFFFFFFU << RTC_BKP23R_Pos)   /*!< 0xFFFFFFFF */
5556 #define RTC_BKP23R                           RTC_BKP23R_Msk
5557 
5558 /********************  Bits definition for RTC_BKP24R register  ***************/
5559 #define RTC_BKP24R_Pos                       (0U)
5560 #define RTC_BKP24R_Msk                       (0xFFFFFFFFU << RTC_BKP24R_Pos)   /*!< 0xFFFFFFFF */
5561 #define RTC_BKP24R                           RTC_BKP24R_Msk
5562 
5563 /********************  Bits definition for RTC_BKP25R register  ***************/
5564 #define RTC_BKP25R_Pos                       (0U)
5565 #define RTC_BKP25R_Msk                       (0xFFFFFFFFU << RTC_BKP25R_Pos)   /*!< 0xFFFFFFFF */
5566 #define RTC_BKP25R                           RTC_BKP25R_Msk
5567 
5568 /********************  Bits definition for RTC_BKP26R register  ***************/
5569 #define RTC_BKP26R_Pos                       (0U)
5570 #define RTC_BKP26R_Msk                       (0xFFFFFFFFU << RTC_BKP26R_Pos)   /*!< 0xFFFFFFFF */
5571 #define RTC_BKP26R                           RTC_BKP26R_Msk
5572 
5573 /********************  Bits definition for RTC_BKP27R register  ***************/
5574 #define RTC_BKP27R_Pos                       (0U)
5575 #define RTC_BKP27R_Msk                       (0xFFFFFFFFU << RTC_BKP27R_Pos)   /*!< 0xFFFFFFFF */
5576 #define RTC_BKP27R                           RTC_BKP27R_Msk
5577 
5578 /********************  Bits definition for RTC_BKP28R register  ***************/
5579 #define RTC_BKP28R_Pos                       (0U)
5580 #define RTC_BKP28R_Msk                       (0xFFFFFFFFU << RTC_BKP28R_Pos)   /*!< 0xFFFFFFFF */
5581 #define RTC_BKP28R                           RTC_BKP28R_Msk
5582 
5583 /********************  Bits definition for RTC_BKP29R register  ***************/
5584 #define RTC_BKP29R_Pos                       (0U)
5585 #define RTC_BKP29R_Msk                       (0xFFFFFFFFU << RTC_BKP29R_Pos)   /*!< 0xFFFFFFFF */
5586 #define RTC_BKP29R                           RTC_BKP29R_Msk
5587 
5588 /********************  Bits definition for RTC_BKP30R register  ***************/
5589 #define RTC_BKP30R_Pos                       (0U)
5590 #define RTC_BKP30R_Msk                       (0xFFFFFFFFU << RTC_BKP30R_Pos)   /*!< 0xFFFFFFFF */
5591 #define RTC_BKP30R                           RTC_BKP30R_Msk
5592 
5593 /********************  Bits definition for RTC_BKP31R register  ***************/
5594 #define RTC_BKP31R_Pos                       (0U)
5595 #define RTC_BKP31R_Msk                       (0xFFFFFFFFU << RTC_BKP31R_Pos)   /*!< 0xFFFFFFFF */
5596 #define RTC_BKP31R                           RTC_BKP31R_Msk
5597 
5598 /******************** Number of backup registers ******************************/
5599 #define RTC_BKP_NUMBER 32
5600 
5601 /******************************************************************************/
5602 /*                                                                            */
5603 /*                     Serial Peripheral Interface (SPI)                      */
5604 /*                                                                            */
5605 /******************************************************************************/
5606 
5607 /*
5608  * @brief Specific device feature definitions (not present on all devices in the STM32F3 serie)
5609  */
5610 #define SPI_I2S_SUPPORT
5611 
5612 /*******************  Bit definition for SPI_CR1 register  ********************/
5613 #define SPI_CR1_CPHA_Pos                    (0U)
5614 #define SPI_CR1_CPHA_Msk                    (0x1U << SPI_CR1_CPHA_Pos)         /*!< 0x00000001 */
5615 #define SPI_CR1_CPHA                        SPI_CR1_CPHA_Msk                   /*!< Clock Phase */
5616 #define SPI_CR1_CPOL_Pos                    (1U)
5617 #define SPI_CR1_CPOL_Msk                    (0x1U << SPI_CR1_CPOL_Pos)         /*!< 0x00000002 */
5618 #define SPI_CR1_CPOL                        SPI_CR1_CPOL_Msk                   /*!< Clock Polarity */
5619 #define SPI_CR1_MSTR_Pos                    (2U)
5620 #define SPI_CR1_MSTR_Msk                    (0x1U << SPI_CR1_MSTR_Pos)         /*!< 0x00000004 */
5621 #define SPI_CR1_MSTR                        SPI_CR1_MSTR_Msk                   /*!< Master Selection */
5622 
5623 #define SPI_CR1_BR_Pos                      (3U)
5624 #define SPI_CR1_BR_Msk                      (0x7U << SPI_CR1_BR_Pos)           /*!< 0x00000038 */
5625 #define SPI_CR1_BR                          SPI_CR1_BR_Msk                     /*!< BR[2:0] bits (Baud Rate Control) */
5626 #define SPI_CR1_BR_0                        (0x1U << SPI_CR1_BR_Pos)           /*!< 0x00000008 */
5627 #define SPI_CR1_BR_1                        (0x2U << SPI_CR1_BR_Pos)           /*!< 0x00000010 */
5628 #define SPI_CR1_BR_2                        (0x4U << SPI_CR1_BR_Pos)           /*!< 0x00000020 */
5629 
5630 #define SPI_CR1_SPE_Pos                     (6U)
5631 #define SPI_CR1_SPE_Msk                     (0x1U << SPI_CR1_SPE_Pos)          /*!< 0x00000040 */
5632 #define SPI_CR1_SPE                         SPI_CR1_SPE_Msk                    /*!< SPI Enable */
5633 #define SPI_CR1_LSBFIRST_Pos                (7U)
5634 #define SPI_CR1_LSBFIRST_Msk                (0x1U << SPI_CR1_LSBFIRST_Pos)     /*!< 0x00000080 */
5635 #define SPI_CR1_LSBFIRST                    SPI_CR1_LSBFIRST_Msk               /*!< Frame Format */
5636 #define SPI_CR1_SSI_Pos                     (8U)
5637 #define SPI_CR1_SSI_Msk                     (0x1U << SPI_CR1_SSI_Pos)          /*!< 0x00000100 */
5638 #define SPI_CR1_SSI                         SPI_CR1_SSI_Msk                    /*!< Internal slave select */
5639 #define SPI_CR1_SSM_Pos                     (9U)
5640 #define SPI_CR1_SSM_Msk                     (0x1U << SPI_CR1_SSM_Pos)          /*!< 0x00000200 */
5641 #define SPI_CR1_SSM                         SPI_CR1_SSM_Msk                    /*!< Software slave management */
5642 #define SPI_CR1_RXONLY_Pos                  (10U)
5643 #define SPI_CR1_RXONLY_Msk                  (0x1U << SPI_CR1_RXONLY_Pos)       /*!< 0x00000400 */
5644 #define SPI_CR1_RXONLY                      SPI_CR1_RXONLY_Msk                 /*!< Receive only */
5645 #define SPI_CR1_DFF_Pos                     (11U)
5646 #define SPI_CR1_DFF_Msk                     (0x1U << SPI_CR1_DFF_Pos)          /*!< 0x00000800 */
5647 #define SPI_CR1_DFF                         SPI_CR1_DFF_Msk                    /*!< Data Frame Format */
5648 #define SPI_CR1_CRCNEXT_Pos                 (12U)
5649 #define SPI_CR1_CRCNEXT_Msk                 (0x1U << SPI_CR1_CRCNEXT_Pos)      /*!< 0x00001000 */
5650 #define SPI_CR1_CRCNEXT                     SPI_CR1_CRCNEXT_Msk                /*!< Transmit CRC next */
5651 #define SPI_CR1_CRCEN_Pos                   (13U)
5652 #define SPI_CR1_CRCEN_Msk                   (0x1U << SPI_CR1_CRCEN_Pos)        /*!< 0x00002000 */
5653 #define SPI_CR1_CRCEN                       SPI_CR1_CRCEN_Msk                  /*!< Hardware CRC calculation enable */
5654 #define SPI_CR1_BIDIOE_Pos                  (14U)
5655 #define SPI_CR1_BIDIOE_Msk                  (0x1U << SPI_CR1_BIDIOE_Pos)       /*!< 0x00004000 */
5656 #define SPI_CR1_BIDIOE                      SPI_CR1_BIDIOE_Msk                 /*!< Output enable in bidirectional mode */
5657 #define SPI_CR1_BIDIMODE_Pos                (15U)
5658 #define SPI_CR1_BIDIMODE_Msk                (0x1U << SPI_CR1_BIDIMODE_Pos)     /*!< 0x00008000 */
5659 #define SPI_CR1_BIDIMODE                    SPI_CR1_BIDIMODE_Msk               /*!< Bidirectional data mode enable */
5660 
5661 /*******************  Bit definition for SPI_CR2 register  ********************/
5662 #define SPI_CR2_RXDMAEN_Pos                 (0U)
5663 #define SPI_CR2_RXDMAEN_Msk                 (0x1U << SPI_CR2_RXDMAEN_Pos)      /*!< 0x00000001 */
5664 #define SPI_CR2_RXDMAEN                     SPI_CR2_RXDMAEN_Msk                /*!< Rx Buffer DMA Enable */
5665 #define SPI_CR2_TXDMAEN_Pos                 (1U)
5666 #define SPI_CR2_TXDMAEN_Msk                 (0x1U << SPI_CR2_TXDMAEN_Pos)      /*!< 0x00000002 */
5667 #define SPI_CR2_TXDMAEN                     SPI_CR2_TXDMAEN_Msk                /*!< Tx Buffer DMA Enable */
5668 #define SPI_CR2_SSOE_Pos                    (2U)
5669 #define SPI_CR2_SSOE_Msk                    (0x1U << SPI_CR2_SSOE_Pos)         /*!< 0x00000004 */
5670 #define SPI_CR2_SSOE                        SPI_CR2_SSOE_Msk                   /*!< SS Output Enable */
5671 #define SPI_CR2_FRF_Pos                     (4U)
5672 #define SPI_CR2_FRF_Msk                     (0x1U << SPI_CR2_FRF_Pos)          /*!< 0x00000010 */
5673 #define SPI_CR2_FRF                         SPI_CR2_FRF_Msk                    /*!< Frame format */
5674 #define SPI_CR2_ERRIE_Pos                   (5U)
5675 #define SPI_CR2_ERRIE_Msk                   (0x1U << SPI_CR2_ERRIE_Pos)        /*!< 0x00000020 */
5676 #define SPI_CR2_ERRIE                       SPI_CR2_ERRIE_Msk                  /*!< Error Interrupt Enable */
5677 #define SPI_CR2_RXNEIE_Pos                  (6U)
5678 #define SPI_CR2_RXNEIE_Msk                  (0x1U << SPI_CR2_RXNEIE_Pos)       /*!< 0x00000040 */
5679 #define SPI_CR2_RXNEIE                      SPI_CR2_RXNEIE_Msk                 /*!< RX buffer Not Empty Interrupt Enable */
5680 #define SPI_CR2_TXEIE_Pos                   (7U)
5681 #define SPI_CR2_TXEIE_Msk                   (0x1U << SPI_CR2_TXEIE_Pos)        /*!< 0x00000080 */
5682 #define SPI_CR2_TXEIE                       SPI_CR2_TXEIE_Msk                  /*!< Tx buffer Empty Interrupt Enable */
5683 
5684 /********************  Bit definition for SPI_SR register  ********************/
5685 #define SPI_SR_RXNE_Pos                     (0U)
5686 #define SPI_SR_RXNE_Msk                     (0x1U << SPI_SR_RXNE_Pos)          /*!< 0x00000001 */
5687 #define SPI_SR_RXNE                         SPI_SR_RXNE_Msk                    /*!< Receive buffer Not Empty */
5688 #define SPI_SR_TXE_Pos                      (1U)
5689 #define SPI_SR_TXE_Msk                      (0x1U << SPI_SR_TXE_Pos)           /*!< 0x00000002 */
5690 #define SPI_SR_TXE                          SPI_SR_TXE_Msk                     /*!< Transmit buffer Empty */
5691 #define SPI_SR_CHSIDE_Pos                   (2U)
5692 #define SPI_SR_CHSIDE_Msk                   (0x1U << SPI_SR_CHSIDE_Pos)        /*!< 0x00000004 */
5693 #define SPI_SR_CHSIDE                       SPI_SR_CHSIDE_Msk                  /*!< Channel side */
5694 #define SPI_SR_UDR_Pos                      (3U)
5695 #define SPI_SR_UDR_Msk                      (0x1U << SPI_SR_UDR_Pos)           /*!< 0x00000008 */
5696 #define SPI_SR_UDR                          SPI_SR_UDR_Msk                     /*!< Underrun flag */
5697 #define SPI_SR_CRCERR_Pos                   (4U)
5698 #define SPI_SR_CRCERR_Msk                   (0x1U << SPI_SR_CRCERR_Pos)        /*!< 0x00000010 */
5699 #define SPI_SR_CRCERR                       SPI_SR_CRCERR_Msk                  /*!< CRC Error flag */
5700 #define SPI_SR_MODF_Pos                     (5U)
5701 #define SPI_SR_MODF_Msk                     (0x1U << SPI_SR_MODF_Pos)          /*!< 0x00000020 */
5702 #define SPI_SR_MODF                         SPI_SR_MODF_Msk                    /*!< Mode fault */
5703 #define SPI_SR_OVR_Pos                      (6U)
5704 #define SPI_SR_OVR_Msk                      (0x1U << SPI_SR_OVR_Pos)           /*!< 0x00000040 */
5705 #define SPI_SR_OVR                          SPI_SR_OVR_Msk                     /*!< Overrun flag */
5706 #define SPI_SR_BSY_Pos                      (7U)
5707 #define SPI_SR_BSY_Msk                      (0x1U << SPI_SR_BSY_Pos)           /*!< 0x00000080 */
5708 #define SPI_SR_BSY                          SPI_SR_BSY_Msk                     /*!< Busy flag */
5709 #define SPI_SR_FRE_Pos                      (8U)
5710 #define SPI_SR_FRE_Msk                      (0x1U << SPI_SR_FRE_Pos)           /*!< 0x00000100 */
5711 #define SPI_SR_FRE                          SPI_SR_FRE_Msk                     /*!<Frame format error flag  */
5712 
5713 /********************  Bit definition for SPI_DR register  ********************/
5714 #define SPI_DR_DR_Pos                       (0U)
5715 #define SPI_DR_DR_Msk                       (0xFFFFU << SPI_DR_DR_Pos)         /*!< 0x0000FFFF */
5716 #define SPI_DR_DR                           SPI_DR_DR_Msk                      /*!< Data Register */
5717 
5718 /*******************  Bit definition for SPI_CRCPR register  ******************/
5719 #define SPI_CRCPR_CRCPOLY_Pos               (0U)
5720 #define SPI_CRCPR_CRCPOLY_Msk               (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */
5721 #define SPI_CRCPR_CRCPOLY                   SPI_CRCPR_CRCPOLY_Msk              /*!< CRC polynomial register */
5722 
5723 /******************  Bit definition for SPI_RXCRCR register  ******************/
5724 #define SPI_RXCRCR_RXCRC_Pos                (0U)
5725 #define SPI_RXCRCR_RXCRC_Msk                (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)  /*!< 0x0000FFFF */
5726 #define SPI_RXCRCR_RXCRC                    SPI_RXCRCR_RXCRC_Msk               /*!< Rx CRC Register */
5727 
5728 /******************  Bit definition for SPI_TXCRCR register  ******************/
5729 #define SPI_TXCRCR_TXCRC_Pos                (0U)
5730 #define SPI_TXCRCR_TXCRC_Msk                (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)  /*!< 0x0000FFFF */
5731 #define SPI_TXCRCR_TXCRC                    SPI_TXCRCR_TXCRC_Msk               /*!< Tx CRC Register */
5732 
5733 /******************  Bit definition for SPI_I2SCFGR register  *****************/
5734 #define SPI_I2SCFGR_CHLEN_Pos               (0U)
5735 #define SPI_I2SCFGR_CHLEN_Msk               (0x1U << SPI_I2SCFGR_CHLEN_Pos)    /*!< 0x00000001 */
5736 #define SPI_I2SCFGR_CHLEN                   SPI_I2SCFGR_CHLEN_Msk              /*!<Channel length (number of bits per audio channel) */
5737 
5738 #define SPI_I2SCFGR_DATLEN_Pos              (1U)
5739 #define SPI_I2SCFGR_DATLEN_Msk              (0x3U << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000006 */
5740 #define SPI_I2SCFGR_DATLEN                  SPI_I2SCFGR_DATLEN_Msk             /*!<DATLEN[1:0] bits (Data length to be transferred) */
5741 #define SPI_I2SCFGR_DATLEN_0                (0x1U << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000002 */
5742 #define SPI_I2SCFGR_DATLEN_1                (0x2U << SPI_I2SCFGR_DATLEN_Pos)   /*!< 0x00000004 */
5743 
5744 #define SPI_I2SCFGR_CKPOL_Pos               (3U)
5745 #define SPI_I2SCFGR_CKPOL_Msk               (0x1U << SPI_I2SCFGR_CKPOL_Pos)    /*!< 0x00000008 */
5746 #define SPI_I2SCFGR_CKPOL                   SPI_I2SCFGR_CKPOL_Msk              /*!<steady state clock polarity */
5747 
5748 #define SPI_I2SCFGR_I2SSTD_Pos              (4U)
5749 #define SPI_I2SCFGR_I2SSTD_Msk              (0x3U << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000030 */
5750 #define SPI_I2SCFGR_I2SSTD                  SPI_I2SCFGR_I2SSTD_Msk             /*!<I2SSTD[1:0] bits (I2S standard selection) */
5751 #define SPI_I2SCFGR_I2SSTD_0                (0x1U << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000010 */
5752 #define SPI_I2SCFGR_I2SSTD_1                (0x2U << SPI_I2SCFGR_I2SSTD_Pos)   /*!< 0x00000020 */
5753 
5754 #define SPI_I2SCFGR_PCMSYNC_Pos             (7U)
5755 #define SPI_I2SCFGR_PCMSYNC_Msk             (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)  /*!< 0x00000080 */
5756 #define SPI_I2SCFGR_PCMSYNC                 SPI_I2SCFGR_PCMSYNC_Msk            /*!<PCM frame synchronization */
5757 
5758 #define SPI_I2SCFGR_I2SCFG_Pos              (8U)
5759 #define SPI_I2SCFGR_I2SCFG_Msk              (0x3U << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000300 */
5760 #define SPI_I2SCFGR_I2SCFG                  SPI_I2SCFGR_I2SCFG_Msk             /*!<I2SCFG[1:0] bits (I2S configuration mode) */
5761 #define SPI_I2SCFGR_I2SCFG_0                (0x1U << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000100 */
5762 #define SPI_I2SCFGR_I2SCFG_1                (0x2U << SPI_I2SCFGR_I2SCFG_Pos)   /*!< 0x00000200 */
5763 
5764 #define SPI_I2SCFGR_I2SE_Pos                (10U)
5765 #define SPI_I2SCFGR_I2SE_Msk                (0x1U << SPI_I2SCFGR_I2SE_Pos)     /*!< 0x00000400 */
5766 #define SPI_I2SCFGR_I2SE                    SPI_I2SCFGR_I2SE_Msk               /*!<I2S Enable */
5767 #define SPI_I2SCFGR_I2SMOD_Pos              (11U)
5768 #define SPI_I2SCFGR_I2SMOD_Msk              (0x1U << SPI_I2SCFGR_I2SMOD_Pos)   /*!< 0x00000800 */
5769 #define SPI_I2SCFGR_I2SMOD                  SPI_I2SCFGR_I2SMOD_Msk             /*!<I2S mode selection */
5770 
5771 /******************  Bit definition for SPI_I2SPR register  *******************/
5772 #define SPI_I2SPR_I2SDIV_Pos                (0U)
5773 #define SPI_I2SPR_I2SDIV_Msk                (0xFFU << SPI_I2SPR_I2SDIV_Pos)    /*!< 0x000000FF */
5774 #define SPI_I2SPR_I2SDIV                    SPI_I2SPR_I2SDIV_Msk               /*!<I2S Linear prescaler */
5775 #define SPI_I2SPR_ODD_Pos                   (8U)
5776 #define SPI_I2SPR_ODD_Msk                   (0x1U << SPI_I2SPR_ODD_Pos)        /*!< 0x00000100 */
5777 #define SPI_I2SPR_ODD                       SPI_I2SPR_ODD_Msk                  /*!<Odd factor for the prescaler */
5778 #define SPI_I2SPR_MCKOE_Pos                 (9U)
5779 #define SPI_I2SPR_MCKOE_Msk                 (0x1U << SPI_I2SPR_MCKOE_Pos)      /*!< 0x00000200 */
5780 #define SPI_I2SPR_MCKOE                     SPI_I2SPR_MCKOE_Msk                /*!<Master Clock Output Enable */
5781 
5782 /******************************************************************************/
5783 /*                                                                            */
5784 /*                       System Configuration (SYSCFG)                        */
5785 /*                                                                            */
5786 /******************************************************************************/
5787 /*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
5788 #define SYSCFG_MEMRMP_MEM_MODE_Pos      (0U)
5789 #define SYSCFG_MEMRMP_MEM_MODE_Msk      (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000003 */
5790 #define SYSCFG_MEMRMP_MEM_MODE          SYSCFG_MEMRMP_MEM_MODE_Msk             /*!< SYSCFG_Memory Remap Config */
5791 #define SYSCFG_MEMRMP_MEM_MODE_0        (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000001 */
5792 #define SYSCFG_MEMRMP_MEM_MODE_1        (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)   /*!< 0x00000002 */
5793 #define SYSCFG_MEMRMP_BOOT_MODE_Pos     (8U)
5794 #define SYSCFG_MEMRMP_BOOT_MODE_Msk     (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000300 */
5795 #define SYSCFG_MEMRMP_BOOT_MODE         SYSCFG_MEMRMP_BOOT_MODE_Msk            /*!< Boot mode Config */
5796 #define SYSCFG_MEMRMP_BOOT_MODE_0       (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000100 */
5797 #define SYSCFG_MEMRMP_BOOT_MODE_1       (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos)  /*!< 0x00000200 */
5798 
5799 /*****************  Bit definition for SYSCFG_PMC register  *******************/
5800 #define SYSCFG_PMC_USB_PU_Pos           (0U)
5801 #define SYSCFG_PMC_USB_PU_Msk           (0x1U << SYSCFG_PMC_USB_PU_Pos)        /*!< 0x00000001 */
5802 #define SYSCFG_PMC_USB_PU               SYSCFG_PMC_USB_PU_Msk                  /*!< SYSCFG PMC */
5803 #define SYSCFG_PMC_LCD_CAPA_Pos         (1U)
5804 #define SYSCFG_PMC_LCD_CAPA_Msk         (0x1FU << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x0000003E */
5805 #define SYSCFG_PMC_LCD_CAPA             SYSCFG_PMC_LCD_CAPA_Msk                /*!< LCD_CAPA decoupling capacitance connection */
5806 #define SYSCFG_PMC_LCD_CAPA_0           (0x01U << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000002 */
5807 #define SYSCFG_PMC_LCD_CAPA_1           (0x02U << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000004 */
5808 #define SYSCFG_PMC_LCD_CAPA_2           (0x04U << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000008 */
5809 #define SYSCFG_PMC_LCD_CAPA_3           (0x08U << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000010 */
5810 #define SYSCFG_PMC_LCD_CAPA_4           (0x10U << SYSCFG_PMC_LCD_CAPA_Pos)     /*!< 0x00000020 */
5811 
5812 /*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
5813 #define SYSCFG_EXTICR1_EXTI0_Pos        (0U)
5814 #define SYSCFG_EXTICR1_EXTI0_Msk        (0xFU << SYSCFG_EXTICR1_EXTI0_Pos)     /*!< 0x0000000F */
5815 #define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!< EXTI 0 configuration */
5816 #define SYSCFG_EXTICR1_EXTI1_Pos        (4U)
5817 #define SYSCFG_EXTICR1_EXTI1_Msk        (0xFU << SYSCFG_EXTICR1_EXTI1_Pos)     /*!< 0x000000F0 */
5818 #define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!< EXTI 1 configuration */
5819 #define SYSCFG_EXTICR1_EXTI2_Pos        (8U)
5820 #define SYSCFG_EXTICR1_EXTI2_Msk        (0xFU << SYSCFG_EXTICR1_EXTI2_Pos)     /*!< 0x00000F00 */
5821 #define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!< EXTI 2 configuration */
5822 #define SYSCFG_EXTICR1_EXTI3_Pos        (12U)
5823 #define SYSCFG_EXTICR1_EXTI3_Msk        (0xFU << SYSCFG_EXTICR1_EXTI3_Pos)     /*!< 0x0000F000 */
5824 #define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!< EXTI 3 configuration */
5825 
5826 /**
5827   * @brief  EXTI0 configuration
5828   */
5829 #define SYSCFG_EXTICR1_EXTI0_PA         (0x00000000U)                          /*!< PA[0] pin */
5830 #define SYSCFG_EXTICR1_EXTI0_PB         (0x00000001U)                          /*!< PB[0] pin */
5831 #define SYSCFG_EXTICR1_EXTI0_PC         (0x00000002U)                          /*!< PC[0] pin */
5832 #define SYSCFG_EXTICR1_EXTI0_PD         (0x00000003U)                          /*!< PD[0] pin */
5833 #define SYSCFG_EXTICR1_EXTI0_PE         (0x00000004U)                          /*!< PE[0] pin */
5834 #define SYSCFG_EXTICR1_EXTI0_PH         (0x00000005U)                          /*!< PH[0] pin */
5835 #define SYSCFG_EXTICR1_EXTI0_PF         (0x00000006U)                          /*!< PF[0] pin */
5836 #define SYSCFG_EXTICR1_EXTI0_PG         (0x00000007U)                          /*!< PG[0] pin */
5837 
5838 /**
5839   * @brief  EXTI1 configuration
5840   */
5841 #define SYSCFG_EXTICR1_EXTI1_PA         (0x00000000U)                          /*!< PA[1] pin */
5842 #define SYSCFG_EXTICR1_EXTI1_PB         (0x00000010U)                          /*!< PB[1] pin */
5843 #define SYSCFG_EXTICR1_EXTI1_PC         (0x00000020U)                          /*!< PC[1] pin */
5844 #define SYSCFG_EXTICR1_EXTI1_PD         (0x00000030U)                          /*!< PD[1] pin */
5845 #define SYSCFG_EXTICR1_EXTI1_PE         (0x00000040U)                          /*!< PE[1] pin */
5846 #define SYSCFG_EXTICR1_EXTI1_PH         (0x00000050U)                          /*!< PH[1] pin */
5847 #define SYSCFG_EXTICR1_EXTI1_PF         (0x00000060U)                          /*!< PF[1] pin */
5848 #define SYSCFG_EXTICR1_EXTI1_PG         (0x00000070U)                          /*!< PG[1] pin */
5849 
5850 /**
5851   * @brief  EXTI2 configuration
5852   */
5853 #define SYSCFG_EXTICR1_EXTI2_PA         (0x00000000U)                          /*!< PA[2] pin */
5854 #define SYSCFG_EXTICR1_EXTI2_PB         (0x00000100U)                          /*!< PB[2] pin */
5855 #define SYSCFG_EXTICR1_EXTI2_PC         (0x00000200U)                          /*!< PC[2] pin */
5856 #define SYSCFG_EXTICR1_EXTI2_PD         (0x00000300U)                          /*!< PD[2] pin */
5857 #define SYSCFG_EXTICR1_EXTI2_PE         (0x00000400U)                          /*!< PE[2] pin */
5858 #define SYSCFG_EXTICR1_EXTI2_PH         (0x00000500U)                          /*!< PH[2] pin */
5859 #define SYSCFG_EXTICR1_EXTI2_PF         (0x00000600U)                          /*!< PF[2] pin */
5860 #define SYSCFG_EXTICR1_EXTI2_PG         (0x00000700U)                          /*!< PG[2] pin */
5861 
5862 /**
5863   * @brief  EXTI3 configuration
5864   */
5865 #define SYSCFG_EXTICR1_EXTI3_PA         (0x00000000U)                          /*!< PA[3] pin */
5866 #define SYSCFG_EXTICR1_EXTI3_PB         (0x00001000U)                          /*!< PB[3] pin */
5867 #define SYSCFG_EXTICR1_EXTI3_PC         (0x00002000U)                          /*!< PC[3] pin */
5868 #define SYSCFG_EXTICR1_EXTI3_PD         (0x00003000U)                          /*!< PD[3] pin */
5869 #define SYSCFG_EXTICR1_EXTI3_PE         (0x00004000U)                          /*!< PE[3] pin */
5870 #define SYSCFG_EXTICR1_EXTI3_PF         (0x00003000U)                          /*!< PF[3] pin */
5871 #define SYSCFG_EXTICR1_EXTI3_PG         (0x00004000U)                          /*!< PG[3] pin */
5872 
5873 /*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
5874 #define SYSCFG_EXTICR2_EXTI4_Pos        (0U)
5875 #define SYSCFG_EXTICR2_EXTI4_Msk        (0xFU << SYSCFG_EXTICR2_EXTI4_Pos)     /*!< 0x0000000F */
5876 #define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!< EXTI 4 configuration */
5877 #define SYSCFG_EXTICR2_EXTI5_Pos        (4U)
5878 #define SYSCFG_EXTICR2_EXTI5_Msk        (0xFU << SYSCFG_EXTICR2_EXTI5_Pos)     /*!< 0x000000F0 */
5879 #define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!< EXTI 5 configuration */
5880 #define SYSCFG_EXTICR2_EXTI6_Pos        (8U)
5881 #define SYSCFG_EXTICR2_EXTI6_Msk        (0xFU << SYSCFG_EXTICR2_EXTI6_Pos)     /*!< 0x00000F00 */
5882 #define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!< EXTI 6 configuration */
5883 #define SYSCFG_EXTICR2_EXTI7_Pos        (12U)
5884 #define SYSCFG_EXTICR2_EXTI7_Msk        (0xFU << SYSCFG_EXTICR2_EXTI7_Pos)     /*!< 0x0000F000 */
5885 #define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!< EXTI 7 configuration */
5886 
5887 /**
5888   * @brief  EXTI4 configuration
5889   */
5890 #define SYSCFG_EXTICR2_EXTI4_PA         (0x00000000U)                          /*!< PA[4] pin */
5891 #define SYSCFG_EXTICR2_EXTI4_PB         (0x00000001U)                          /*!< PB[4] pin */
5892 #define SYSCFG_EXTICR2_EXTI4_PC         (0x00000002U)                          /*!< PC[4] pin */
5893 #define SYSCFG_EXTICR2_EXTI4_PD         (0x00000003U)                          /*!< PD[4] pin */
5894 #define SYSCFG_EXTICR2_EXTI4_PE         (0x00000004U)                          /*!< PE[4] pin */
5895 #define SYSCFG_EXTICR2_EXTI4_PF         (0x00000006U)                          /*!< PF[4] pin */
5896 #define SYSCFG_EXTICR2_EXTI4_PG         (0x00000007U)                          /*!< PG[4] pin */
5897 
5898 /**
5899   * @brief  EXTI5 configuration
5900   */
5901 #define SYSCFG_EXTICR2_EXTI5_PA         (0x00000000U)                          /*!< PA[5] pin */
5902 #define SYSCFG_EXTICR2_EXTI5_PB         (0x00000010U)                          /*!< PB[5] pin */
5903 #define SYSCFG_EXTICR2_EXTI5_PC         (0x00000020U)                          /*!< PC[5] pin */
5904 #define SYSCFG_EXTICR2_EXTI5_PD         (0x00000030U)                          /*!< PD[5] pin */
5905 #define SYSCFG_EXTICR2_EXTI5_PE         (0x00000040U)                          /*!< PE[5] pin */
5906 #define SYSCFG_EXTICR2_EXTI5_PF         (0x00000060U)                          /*!< PF[5] pin */
5907 #define SYSCFG_EXTICR2_EXTI5_PG         (0x00000070U)                          /*!< PG[5] pin */
5908 
5909 /**
5910   * @brief  EXTI6 configuration
5911   */
5912 #define SYSCFG_EXTICR2_EXTI6_PA         (0x00000000U)                          /*!< PA[6] pin */
5913 #define SYSCFG_EXTICR2_EXTI6_PB         (0x00000100U)                          /*!< PB[6] pin */
5914 #define SYSCFG_EXTICR2_EXTI6_PC         (0x00000200U)                          /*!< PC[6] pin */
5915 #define SYSCFG_EXTICR2_EXTI6_PD         (0x00000300U)                          /*!< PD[6] pin */
5916 #define SYSCFG_EXTICR2_EXTI6_PE         (0x00000400U)                          /*!< PE[6] pin */
5917 #define SYSCFG_EXTICR2_EXTI6_PF         (0x00000600U)                          /*!< PF[6] pin */
5918 #define SYSCFG_EXTICR2_EXTI6_PG         (0x00000700U)                          /*!< PG[6] pin */
5919 
5920 /**
5921   * @brief  EXTI7 configuration
5922   */
5923 #define SYSCFG_EXTICR2_EXTI7_PA         (0x00000000U)                          /*!< PA[7] pin */
5924 #define SYSCFG_EXTICR2_EXTI7_PB         (0x00001000U)                          /*!< PB[7] pin */
5925 #define SYSCFG_EXTICR2_EXTI7_PC         (0x00002000U)                          /*!< PC[7] pin */
5926 #define SYSCFG_EXTICR2_EXTI7_PD         (0x00003000U)                          /*!< PD[7] pin */
5927 #define SYSCFG_EXTICR2_EXTI7_PE         (0x00004000U)                          /*!< PE[7] pin */
5928 #define SYSCFG_EXTICR2_EXTI7_PF         (0x00006000U)                          /*!< PF[7] pin */
5929 #define SYSCFG_EXTICR2_EXTI7_PG         (0x00007000U)                          /*!< PG[7] pin */
5930 
5931 /*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
5932 #define SYSCFG_EXTICR3_EXTI8_Pos        (0U)
5933 #define SYSCFG_EXTICR3_EXTI8_Msk        (0xFU << SYSCFG_EXTICR3_EXTI8_Pos)     /*!< 0x0000000F */
5934 #define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!< EXTI 8 configuration */
5935 #define SYSCFG_EXTICR3_EXTI9_Pos        (4U)
5936 #define SYSCFG_EXTICR3_EXTI9_Msk        (0xFU << SYSCFG_EXTICR3_EXTI9_Pos)     /*!< 0x000000F0 */
5937 #define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!< EXTI 9 configuration */
5938 #define SYSCFG_EXTICR3_EXTI10_Pos       (8U)
5939 #define SYSCFG_EXTICR3_EXTI10_Msk       (0xFU << SYSCFG_EXTICR3_EXTI10_Pos)    /*!< 0x00000F00 */
5940 #define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!< EXTI 10 configuration */
5941 #define SYSCFG_EXTICR3_EXTI11_Pos       (12U)
5942 #define SYSCFG_EXTICR3_EXTI11_Msk       (0xFU << SYSCFG_EXTICR3_EXTI11_Pos)    /*!< 0x0000F000 */
5943 #define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!< EXTI 11 configuration */
5944 
5945 /**
5946   * @brief  EXTI8 configuration
5947   */
5948 #define SYSCFG_EXTICR3_EXTI8_PA         (0x00000000U)                          /*!< PA[8] pin */
5949 #define SYSCFG_EXTICR3_EXTI8_PB         (0x00000001U)                          /*!< PB[8] pin */
5950 #define SYSCFG_EXTICR3_EXTI8_PC         (0x00000002U)                          /*!< PC[8] pin */
5951 #define SYSCFG_EXTICR3_EXTI8_PD         (0x00000003U)                          /*!< PD[8] pin */
5952 #define SYSCFG_EXTICR3_EXTI8_PE         (0x00000004U)                          /*!< PE[8] pin */
5953 #define SYSCFG_EXTICR3_EXTI8_PF         (0x00000006U)                          /*!< PF[8] pin */
5954 #define SYSCFG_EXTICR3_EXTI8_PG         (0x00000007U)                          /*!< PG[8] pin */
5955 
5956 /**
5957   * @brief  EXTI9 configuration
5958   */
5959 #define SYSCFG_EXTICR3_EXTI9_PA         (0x00000000U)                          /*!< PA[9] pin */
5960 #define SYSCFG_EXTICR3_EXTI9_PB         (0x00000010U)                          /*!< PB[9] pin */
5961 #define SYSCFG_EXTICR3_EXTI9_PC         (0x00000020U)                          /*!< PC[9] pin */
5962 #define SYSCFG_EXTICR3_EXTI9_PD         (0x00000030U)                          /*!< PD[9] pin */
5963 #define SYSCFG_EXTICR3_EXTI9_PE         (0x00000040U)                          /*!< PE[9] pin */
5964 #define SYSCFG_EXTICR3_EXTI9_PF         (0x00000060U)                          /*!< PF[9] pin */
5965 #define SYSCFG_EXTICR3_EXTI9_PG         (0x00000070U)                          /*!< PG[9] pin */
5966 
5967 /**
5968   * @brief  EXTI10 configuration
5969   */
5970 #define SYSCFG_EXTICR3_EXTI10_PA        (0x00000000U)                          /*!< PA[10] pin */
5971 #define SYSCFG_EXTICR3_EXTI10_PB        (0x00000100U)                          /*!< PB[10] pin */
5972 #define SYSCFG_EXTICR3_EXTI10_PC        (0x00000200U)                          /*!< PC[10] pin */
5973 #define SYSCFG_EXTICR3_EXTI10_PD        (0x00000300U)                          /*!< PD[10] pin */
5974 #define SYSCFG_EXTICR3_EXTI10_PE        (0x00000400U)                          /*!< PE[10] pin */
5975 #define SYSCFG_EXTICR3_EXTI10_PF        (0x00000600U)                          /*!< PF[10] pin */
5976 #define SYSCFG_EXTICR3_EXTI10_PG        (0x00000700U)                          /*!< PG[10] pin */
5977 
5978 /**
5979   * @brief  EXTI11 configuration
5980   */
5981 #define SYSCFG_EXTICR3_EXTI11_PA        (0x00000000U)                          /*!< PA[11] pin */
5982 #define SYSCFG_EXTICR3_EXTI11_PB        (0x00001000U)                          /*!< PB[11] pin */
5983 #define SYSCFG_EXTICR3_EXTI11_PC        (0x00002000U)                          /*!< PC[11] pin */
5984 #define SYSCFG_EXTICR3_EXTI11_PD        (0x00003000U)                          /*!< PD[11] pin */
5985 #define SYSCFG_EXTICR3_EXTI11_PE        (0x00004000U)                          /*!< PE[11] pin */
5986 #define SYSCFG_EXTICR3_EXTI11_PF        (0x00006000U)                          /*!< PF[11] pin */
5987 #define SYSCFG_EXTICR3_EXTI11_PG        (0x00007000U)                          /*!< PG[11] pin */
5988 
5989 /*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
5990 #define SYSCFG_EXTICR4_EXTI12_Pos       (0U)
5991 #define SYSCFG_EXTICR4_EXTI12_Msk       (0xFU << SYSCFG_EXTICR4_EXTI12_Pos)    /*!< 0x0000000F */
5992 #define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!< EXTI 12 configuration */
5993 #define SYSCFG_EXTICR4_EXTI13_Pos       (4U)
5994 #define SYSCFG_EXTICR4_EXTI13_Msk       (0xFU << SYSCFG_EXTICR4_EXTI13_Pos)    /*!< 0x000000F0 */
5995 #define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!< EXTI 13 configuration */
5996 #define SYSCFG_EXTICR4_EXTI14_Pos       (8U)
5997 #define SYSCFG_EXTICR4_EXTI14_Msk       (0xFU << SYSCFG_EXTICR4_EXTI14_Pos)    /*!< 0x00000F00 */
5998 #define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!< EXTI 14 configuration */
5999 #define SYSCFG_EXTICR4_EXTI15_Pos       (12U)
6000 #define SYSCFG_EXTICR4_EXTI15_Msk       (0xFU << SYSCFG_EXTICR4_EXTI15_Pos)    /*!< 0x0000F000 */
6001 #define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!< EXTI 15 configuration */
6002 
6003 /**
6004   * @brief  EXTI12 configuration
6005   */
6006 #define SYSCFG_EXTICR4_EXTI12_PA        (0x00000000U)                          /*!< PA[12] pin */
6007 #define SYSCFG_EXTICR4_EXTI12_PB        (0x00000001U)                          /*!< PB[12] pin */
6008 #define SYSCFG_EXTICR4_EXTI12_PC        (0x00000002U)                          /*!< PC[12] pin */
6009 #define SYSCFG_EXTICR4_EXTI12_PD        (0x00000003U)                          /*!< PD[12] pin */
6010 #define SYSCFG_EXTICR4_EXTI12_PE        (0x00000004U)                          /*!< PE[12] pin */
6011 #define SYSCFG_EXTICR4_EXTI12_PF        (0x00000006U)                          /*!< PF[12] pin */
6012 #define SYSCFG_EXTICR4_EXTI12_PG        (0x00000007U)                          /*!< PG[12] pin */
6013 
6014 /**
6015   * @brief  EXTI13 configuration
6016   */
6017 #define SYSCFG_EXTICR4_EXTI13_PA        (0x00000000U)                          /*!< PA[13] pin */
6018 #define SYSCFG_EXTICR4_EXTI13_PB        (0x00000010U)                          /*!< PB[13] pin */
6019 #define SYSCFG_EXTICR4_EXTI13_PC        (0x00000020U)                          /*!< PC[13] pin */
6020 #define SYSCFG_EXTICR4_EXTI13_PD        (0x00000030U)                          /*!< PD[13] pin */
6021 #define SYSCFG_EXTICR4_EXTI13_PE        (0x00000040U)                          /*!< PE[13] pin */
6022 #define SYSCFG_EXTICR4_EXTI13_PF        (0x00000060U)                          /*!< PF[13] pin */
6023 #define SYSCFG_EXTICR4_EXTI13_PG        (0x00000070U)                          /*!< PG[13] pin */
6024 
6025 /**
6026   * @brief  EXTI14 configuration
6027   */
6028 #define SYSCFG_EXTICR4_EXTI14_PA        (0x00000000U)                          /*!< PA[14] pin */
6029 #define SYSCFG_EXTICR4_EXTI14_PB        (0x00000100U)                          /*!< PB[14] pin */
6030 #define SYSCFG_EXTICR4_EXTI14_PC        (0x00000200U)                          /*!< PC[14] pin */
6031 #define SYSCFG_EXTICR4_EXTI14_PD        (0x00000300U)                          /*!< PD[14] pin */
6032 #define SYSCFG_EXTICR4_EXTI14_PE        (0x00000400U)                          /*!< PE[14] pin */
6033 #define SYSCFG_EXTICR4_EXTI14_PF        (0x00000600U)                          /*!< PF[14] pin */
6034 #define SYSCFG_EXTICR4_EXTI14_PG        (0x00000700U)                          /*!< PG[14] pin */
6035 
6036 /**
6037   * @brief  EXTI15 configuration
6038   */
6039 #define SYSCFG_EXTICR4_EXTI15_PA        (0x00000000U)                          /*!< PA[15] pin */
6040 #define SYSCFG_EXTICR4_EXTI15_PB        (0x00001000U)                          /*!< PB[15] pin */
6041 #define SYSCFG_EXTICR4_EXTI15_PC        (0x00002000U)                          /*!< PC[15] pin */
6042 #define SYSCFG_EXTICR4_EXTI15_PD        (0x00003000U)                          /*!< PD[15] pin */
6043 #define SYSCFG_EXTICR4_EXTI15_PE        (0x00004000U)                          /*!< PE[15] pin */
6044 #define SYSCFG_EXTICR4_EXTI15_PF        (0x00006000U)                          /*!< PF[15] pin */
6045 #define SYSCFG_EXTICR4_EXTI15_PG        (0x00007000U)                          /*!< PG[15] pin */
6046 
6047 /******************************************************************************/
6048 /*                                                                            */
6049 /*                       Routing Interface (RI)                               */
6050 /*                                                                            */
6051 /******************************************************************************/
6052 
6053 /********************  Bit definition for RI_ICR register  ********************/
6054 #define RI_ICR_IC1OS_Pos                (0U)
6055 #define RI_ICR_IC1OS_Msk                (0xFU << RI_ICR_IC1OS_Pos)             /*!< 0x0000000F */
6056 #define RI_ICR_IC1OS                    RI_ICR_IC1OS_Msk                       /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
6057 #define RI_ICR_IC1OS_0                  (0x1U << RI_ICR_IC1OS_Pos)             /*!< 0x00000001 */
6058 #define RI_ICR_IC1OS_1                  (0x2U << RI_ICR_IC1OS_Pos)             /*!< 0x00000002 */
6059 #define RI_ICR_IC1OS_2                  (0x4U << RI_ICR_IC1OS_Pos)             /*!< 0x00000004 */
6060 #define RI_ICR_IC1OS_3                  (0x8U << RI_ICR_IC1OS_Pos)             /*!< 0x00000008 */
6061 
6062 #define RI_ICR_IC2OS_Pos                (4U)
6063 #define RI_ICR_IC2OS_Msk                (0xFU << RI_ICR_IC2OS_Pos)             /*!< 0x000000F0 */
6064 #define RI_ICR_IC2OS                    RI_ICR_IC2OS_Msk                       /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
6065 #define RI_ICR_IC2OS_0                  (0x1U << RI_ICR_IC2OS_Pos)             /*!< 0x00000010 */
6066 #define RI_ICR_IC2OS_1                  (0x2U << RI_ICR_IC2OS_Pos)             /*!< 0x00000020 */
6067 #define RI_ICR_IC2OS_2                  (0x4U << RI_ICR_IC2OS_Pos)             /*!< 0x00000040 */
6068 #define RI_ICR_IC2OS_3                  (0x8U << RI_ICR_IC2OS_Pos)             /*!< 0x00000080 */
6069 
6070 #define RI_ICR_IC3OS_Pos                (8U)
6071 #define RI_ICR_IC3OS_Msk                (0xFU << RI_ICR_IC3OS_Pos)             /*!< 0x00000F00 */
6072 #define RI_ICR_IC3OS                    RI_ICR_IC3OS_Msk                       /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
6073 #define RI_ICR_IC3OS_0                  (0x1U << RI_ICR_IC3OS_Pos)             /*!< 0x00000100 */
6074 #define RI_ICR_IC3OS_1                  (0x2U << RI_ICR_IC3OS_Pos)             /*!< 0x00000200 */
6075 #define RI_ICR_IC3OS_2                  (0x4U << RI_ICR_IC3OS_Pos)             /*!< 0x00000400 */
6076 #define RI_ICR_IC3OS_3                  (0x8U << RI_ICR_IC3OS_Pos)             /*!< 0x00000800 */
6077 
6078 #define RI_ICR_IC4OS_Pos                (12U)
6079 #define RI_ICR_IC4OS_Msk                (0xFU << RI_ICR_IC4OS_Pos)             /*!< 0x0000F000 */
6080 #define RI_ICR_IC4OS                    RI_ICR_IC4OS_Msk                       /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
6081 #define RI_ICR_IC4OS_0                  (0x1U << RI_ICR_IC4OS_Pos)             /*!< 0x00001000 */
6082 #define RI_ICR_IC4OS_1                  (0x2U << RI_ICR_IC4OS_Pos)             /*!< 0x00002000 */
6083 #define RI_ICR_IC4OS_2                  (0x4U << RI_ICR_IC4OS_Pos)             /*!< 0x00004000 */
6084 #define RI_ICR_IC4OS_3                  (0x8U << RI_ICR_IC4OS_Pos)             /*!< 0x00008000 */
6085 
6086 #define RI_ICR_TIM_Pos                  (16U)
6087 #define RI_ICR_TIM_Msk                  (0x3U << RI_ICR_TIM_Pos)               /*!< 0x00030000 */
6088 #define RI_ICR_TIM                      RI_ICR_TIM_Msk                         /*!< TIM[3:0] bits (Timers select bits) */
6089 #define RI_ICR_TIM_0                    (0x1U << RI_ICR_TIM_Pos)               /*!< 0x00010000 */
6090 #define RI_ICR_TIM_1                    (0x2U << RI_ICR_TIM_Pos)               /*!< 0x00020000 */
6091 
6092 #define RI_ICR_IC1_Pos                  (18U)
6093 #define RI_ICR_IC1_Msk                  (0x1U << RI_ICR_IC1_Pos)               /*!< 0x00040000 */
6094 #define RI_ICR_IC1                      RI_ICR_IC1_Msk                         /*!< Input capture 1 */
6095 #define RI_ICR_IC2_Pos                  (19U)
6096 #define RI_ICR_IC2_Msk                  (0x1U << RI_ICR_IC2_Pos)               /*!< 0x00080000 */
6097 #define RI_ICR_IC2                      RI_ICR_IC2_Msk                         /*!< Input capture 2 */
6098 #define RI_ICR_IC3_Pos                  (20U)
6099 #define RI_ICR_IC3_Msk                  (0x1U << RI_ICR_IC3_Pos)               /*!< 0x00100000 */
6100 #define RI_ICR_IC3                      RI_ICR_IC3_Msk                         /*!< Input capture 3 */
6101 #define RI_ICR_IC4_Pos                  (21U)
6102 #define RI_ICR_IC4_Msk                  (0x1U << RI_ICR_IC4_Pos)               /*!< 0x00200000 */
6103 #define RI_ICR_IC4                      RI_ICR_IC4_Msk                         /*!< Input capture 4 */
6104 
6105 /********************  Bit definition for RI_ASCR1 register  ********************/
6106 #define RI_ASCR1_CH_Pos                 (0U)
6107 #define RI_ASCR1_CH_Msk                 (0x7BFDFFFFU << RI_ASCR1_CH_Pos)       /*!< 0x7BFDFFFF */
6108 #define RI_ASCR1_CH                     RI_ASCR1_CH_Msk                        /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
6109 #define RI_ASCR1_CH_0                   (0x00000001U)                          /*!< Bit 0 */
6110 #define RI_ASCR1_CH_1                   (0x00000002U)                          /*!< Bit 1 */
6111 #define RI_ASCR1_CH_2                   (0x00000004U)                          /*!< Bit 2 */
6112 #define RI_ASCR1_CH_3                   (0x00000008U)                          /*!< Bit 3 */
6113 #define RI_ASCR1_CH_4                   (0x00000010U)                          /*!< Bit 4 */
6114 #define RI_ASCR1_CH_5                   (0x00000020U)                          /*!< Bit 5 */
6115 #define RI_ASCR1_CH_6                   (0x00000040U)                          /*!< Bit 6 */
6116 #define RI_ASCR1_CH_7                   (0x00000080U)                          /*!< Bit 7 */
6117 #define RI_ASCR1_CH_8                   (0x00000100U)                          /*!< Bit 8 */
6118 #define RI_ASCR1_CH_9                   (0x00000200U)                          /*!< Bit 9 */
6119 #define RI_ASCR1_CH_10                  (0x00000400U)                          /*!< Bit 10 */
6120 #define RI_ASCR1_CH_11                  (0x00000800U)                          /*!< Bit 11 */
6121 #define RI_ASCR1_CH_12                  (0x00001000U)                          /*!< Bit 12 */
6122 #define RI_ASCR1_CH_13                  (0x00002000U)                          /*!< Bit 13 */
6123 #define RI_ASCR1_CH_14                  (0x00004000U)                          /*!< Bit 14 */
6124 #define RI_ASCR1_CH_15                  (0x00008000U)                          /*!< Bit 15 */
6125 #define RI_ASCR1_CH_31                  (0x00010000U)                          /*!< Bit 16 */
6126 #define RI_ASCR1_CH_18                  (0x00040000U)                          /*!< Bit 18 */
6127 #define RI_ASCR1_CH_19                  (0x00080000U)                          /*!< Bit 19 */
6128 #define RI_ASCR1_CH_20                  (0x00100000U)                          /*!< Bit 20 */
6129 #define RI_ASCR1_CH_21                  (0x00200000U)                          /*!< Bit 21 */
6130 #define RI_ASCR1_CH_22                  (0x00400000U)                          /*!< Bit 22 */
6131 #define RI_ASCR1_CH_23                  (0x00800000U)                          /*!< Bit 23 */
6132 #define RI_ASCR1_CH_24                  (0x01000000U)                          /*!< Bit 24 */
6133 #define RI_ASCR1_CH_25                  (0x02000000U)                          /*!< Bit 25 */
6134 #define RI_ASCR1_VCOMP_Pos              (26U)
6135 #define RI_ASCR1_VCOMP_Msk              (0x1U << RI_ASCR1_VCOMP_Pos)           /*!< 0x04000000 */
6136 #define RI_ASCR1_VCOMP                  RI_ASCR1_VCOMP_Msk                     /*!< ADC analog switch selection for internal node to COMP1 */
6137 #define RI_ASCR1_CH_27                  (0x08000000U)                          /*!< Bit 27 */
6138 #define RI_ASCR1_CH_28                  (0x10000000U)                          /*!< Bit 28 */
6139 #define RI_ASCR1_CH_29                  (0x20000000U)                          /*!< Bit 29 */
6140 #define RI_ASCR1_CH_30                  (0x40000000U)                          /*!< Bit 30 */
6141 #define RI_ASCR1_SCM_Pos                (31U)
6142 #define RI_ASCR1_SCM_Msk                (0x1U << RI_ASCR1_SCM_Pos)             /*!< 0x80000000 */
6143 #define RI_ASCR1_SCM                    RI_ASCR1_SCM_Msk                       /*!< I/O Switch control mode */
6144 
6145 /********************  Bit definition for RI_ASCR2 register  ********************/
6146 #define RI_ASCR2_GR10_1                 (0x00000001U)                          /*!< GR10-1 selection bit */
6147 #define RI_ASCR2_GR10_2                 (0x00000002U)                          /*!< GR10-2 selection bit */
6148 #define RI_ASCR2_GR10_3                 (0x00000004U)                          /*!< GR10-3 selection bit */
6149 #define RI_ASCR2_GR10_4                 (0x00000008U)                          /*!< GR10-4 selection bit */
6150 #define RI_ASCR2_GR6_Pos                (4U)
6151 #define RI_ASCR2_GR6_Msk                (0x1800003U << RI_ASCR2_GR6_Pos)       /*!< 0x18000030 */
6152 #define RI_ASCR2_GR6                    RI_ASCR2_GR6_Msk                       /*!< GR6 selection bits */
6153 #define RI_ASCR2_GR6_1                  (0x0000001U << RI_ASCR2_GR6_Pos)       /*!< 0x00000010 */
6154 #define RI_ASCR2_GR6_2                  (0x0000002U << RI_ASCR2_GR6_Pos)       /*!< 0x00000020 */
6155 #define RI_ASCR2_GR6_3                  (0x0800000U << RI_ASCR2_GR6_Pos)       /*!< 0x08000000 */
6156 #define RI_ASCR2_GR6_4                  (0x1000000U << RI_ASCR2_GR6_Pos)       /*!< 0x10000000 */
6157 #define RI_ASCR2_GR5_1                  (0x00000040U)                          /*!< GR5-1 selection bit */
6158 #define RI_ASCR2_GR5_2                  (0x00000080U)                          /*!< GR5-2 selection bit */
6159 #define RI_ASCR2_GR5_3                  (0x00000100U)                          /*!< GR5-3 selection bit */
6160 #define RI_ASCR2_GR4_1                  (0x00000200U)                          /*!< GR4-1 selection bit */
6161 #define RI_ASCR2_GR4_2                  (0x00000400U)                          /*!< GR4-2 selection bit */
6162 #define RI_ASCR2_GR4_3                  (0x00000800U)                          /*!< GR4-3 selection bit */
6163 #define RI_ASCR2_GR4_4                  (0x00008000U)                          /*!< GR4-4 selection bit */
6164 #define RI_ASCR2_CH0b_Pos               (16U)
6165 #define RI_ASCR2_CH0b_Msk               (0x1U << RI_ASCR2_CH0b_Pos)            /*!< 0x00010000 */
6166 #define RI_ASCR2_CH0b                   RI_ASCR2_CH0b_Msk                      /*!< CH0b selection bit */
6167 
6168 /********************  Bit definition for RI_HYSCR1 register  ********************/
6169 #define RI_HYSCR1_PA_Pos                (0U)
6170 #define RI_HYSCR1_PA_Msk                (0xFFFFU << RI_HYSCR1_PA_Pos)          /*!< 0x0000FFFF */
6171 #define RI_HYSCR1_PA                    RI_HYSCR1_PA_Msk                       /*!< PA[15:0] Port A Hysteresis selection */
6172 #define RI_HYSCR1_PA_0                  (0x0001U << RI_HYSCR1_PA_Pos)          /*!< 0x00000001 */
6173 #define RI_HYSCR1_PA_1                  (0x0002U << RI_HYSCR1_PA_Pos)          /*!< 0x00000002 */
6174 #define RI_HYSCR1_PA_2                  (0x0004U << RI_HYSCR1_PA_Pos)          /*!< 0x00000004 */
6175 #define RI_HYSCR1_PA_3                  (0x0008U << RI_HYSCR1_PA_Pos)          /*!< 0x00000008 */
6176 #define RI_HYSCR1_PA_4                  (0x0010U << RI_HYSCR1_PA_Pos)          /*!< 0x00000010 */
6177 #define RI_HYSCR1_PA_5                  (0x0020U << RI_HYSCR1_PA_Pos)          /*!< 0x00000020 */
6178 #define RI_HYSCR1_PA_6                  (0x0040U << RI_HYSCR1_PA_Pos)          /*!< 0x00000040 */
6179 #define RI_HYSCR1_PA_7                  (0x0080U << RI_HYSCR1_PA_Pos)          /*!< 0x00000080 */
6180 #define RI_HYSCR1_PA_8                  (0x0100U << RI_HYSCR1_PA_Pos)          /*!< 0x00000100 */
6181 #define RI_HYSCR1_PA_9                  (0x0200U << RI_HYSCR1_PA_Pos)          /*!< 0x00000200 */
6182 #define RI_HYSCR1_PA_10                 (0x0400U << RI_HYSCR1_PA_Pos)          /*!< 0x00000400 */
6183 #define RI_HYSCR1_PA_11                 (0x0800U << RI_HYSCR1_PA_Pos)          /*!< 0x00000800 */
6184 #define RI_HYSCR1_PA_12                 (0x1000U << RI_HYSCR1_PA_Pos)          /*!< 0x00001000 */
6185 #define RI_HYSCR1_PA_13                 (0x2000U << RI_HYSCR1_PA_Pos)          /*!< 0x00002000 */
6186 #define RI_HYSCR1_PA_14                 (0x4000U << RI_HYSCR1_PA_Pos)          /*!< 0x00004000 */
6187 #define RI_HYSCR1_PA_15                 (0x8000U << RI_HYSCR1_PA_Pos)          /*!< 0x00008000 */
6188 
6189 #define RI_HYSCR1_PB_Pos                (16U)
6190 #define RI_HYSCR1_PB_Msk                (0xFFFFU << RI_HYSCR1_PB_Pos)          /*!< 0xFFFF0000 */
6191 #define RI_HYSCR1_PB                    RI_HYSCR1_PB_Msk                       /*!< PB[15:0] Port B Hysteresis selection */
6192 #define RI_HYSCR1_PB_0                  (0x0001U << RI_HYSCR1_PB_Pos)          /*!< 0x00010000 */
6193 #define RI_HYSCR1_PB_1                  (0x0002U << RI_HYSCR1_PB_Pos)          /*!< 0x00020000 */
6194 #define RI_HYSCR1_PB_2                  (0x0004U << RI_HYSCR1_PB_Pos)          /*!< 0x00040000 */
6195 #define RI_HYSCR1_PB_3                  (0x0008U << RI_HYSCR1_PB_Pos)          /*!< 0x00080000 */
6196 #define RI_HYSCR1_PB_4                  (0x0010U << RI_HYSCR1_PB_Pos)          /*!< 0x00100000 */
6197 #define RI_HYSCR1_PB_5                  (0x0020U << RI_HYSCR1_PB_Pos)          /*!< 0x00200000 */
6198 #define RI_HYSCR1_PB_6                  (0x0040U << RI_HYSCR1_PB_Pos)          /*!< 0x00400000 */
6199 #define RI_HYSCR1_PB_7                  (0x0080U << RI_HYSCR1_PB_Pos)          /*!< 0x00800000 */
6200 #define RI_HYSCR1_PB_8                  (0x0100U << RI_HYSCR1_PB_Pos)          /*!< 0x01000000 */
6201 #define RI_HYSCR1_PB_9                  (0x0200U << RI_HYSCR1_PB_Pos)          /*!< 0x02000000 */
6202 #define RI_HYSCR1_PB_10                 (0x0400U << RI_HYSCR1_PB_Pos)          /*!< 0x04000000 */
6203 #define RI_HYSCR1_PB_11                 (0x0800U << RI_HYSCR1_PB_Pos)          /*!< 0x08000000 */
6204 #define RI_HYSCR1_PB_12                 (0x1000U << RI_HYSCR1_PB_Pos)          /*!< 0x10000000 */
6205 #define RI_HYSCR1_PB_13                 (0x2000U << RI_HYSCR1_PB_Pos)          /*!< 0x20000000 */
6206 #define RI_HYSCR1_PB_14                 (0x4000U << RI_HYSCR1_PB_Pos)          /*!< 0x40000000 */
6207 #define RI_HYSCR1_PB_15                 (0x8000U << RI_HYSCR1_PB_Pos)          /*!< 0x80000000 */
6208 
6209 /********************  Bit definition for RI_HYSCR2 register  ********************/
6210 #define RI_HYSCR2_PC_Pos                (0U)
6211 #define RI_HYSCR2_PC_Msk                (0xFFFFU << RI_HYSCR2_PC_Pos)          /*!< 0x0000FFFF */
6212 #define RI_HYSCR2_PC                    RI_HYSCR2_PC_Msk                       /*!< PC[15:0] Port C Hysteresis selection */
6213 #define RI_HYSCR2_PC_0                  (0x0001U << RI_HYSCR2_PC_Pos)          /*!< 0x00000001 */
6214 #define RI_HYSCR2_PC_1                  (0x0002U << RI_HYSCR2_PC_Pos)          /*!< 0x00000002 */
6215 #define RI_HYSCR2_PC_2                  (0x0004U << RI_HYSCR2_PC_Pos)          /*!< 0x00000004 */
6216 #define RI_HYSCR2_PC_3                  (0x0008U << RI_HYSCR2_PC_Pos)          /*!< 0x00000008 */
6217 #define RI_HYSCR2_PC_4                  (0x0010U << RI_HYSCR2_PC_Pos)          /*!< 0x00000010 */
6218 #define RI_HYSCR2_PC_5                  (0x0020U << RI_HYSCR2_PC_Pos)          /*!< 0x00000020 */
6219 #define RI_HYSCR2_PC_6                  (0x0040U << RI_HYSCR2_PC_Pos)          /*!< 0x00000040 */
6220 #define RI_HYSCR2_PC_7                  (0x0080U << RI_HYSCR2_PC_Pos)          /*!< 0x00000080 */
6221 #define RI_HYSCR2_PC_8                  (0x0100U << RI_HYSCR2_PC_Pos)          /*!< 0x00000100 */
6222 #define RI_HYSCR2_PC_9                  (0x0200U << RI_HYSCR2_PC_Pos)          /*!< 0x00000200 */
6223 #define RI_HYSCR2_PC_10                 (0x0400U << RI_HYSCR2_PC_Pos)          /*!< 0x00000400 */
6224 #define RI_HYSCR2_PC_11                 (0x0800U << RI_HYSCR2_PC_Pos)          /*!< 0x00000800 */
6225 #define RI_HYSCR2_PC_12                 (0x1000U << RI_HYSCR2_PC_Pos)          /*!< 0x00001000 */
6226 #define RI_HYSCR2_PC_13                 (0x2000U << RI_HYSCR2_PC_Pos)          /*!< 0x00002000 */
6227 #define RI_HYSCR2_PC_14                 (0x4000U << RI_HYSCR2_PC_Pos)          /*!< 0x00004000 */
6228 #define RI_HYSCR2_PC_15                 (0x8000U << RI_HYSCR2_PC_Pos)          /*!< 0x00008000 */
6229 
6230 #define RI_HYSCR2_PD_Pos                (16U)
6231 #define RI_HYSCR2_PD_Msk                (0xFFFFU << RI_HYSCR2_PD_Pos)          /*!< 0xFFFF0000 */
6232 #define RI_HYSCR2_PD                    RI_HYSCR2_PD_Msk                       /*!< PD[15:0] Port D Hysteresis selection */
6233 #define RI_HYSCR2_PD_0                  (0x0001U << RI_HYSCR2_PD_Pos)          /*!< 0x00010000 */
6234 #define RI_HYSCR2_PD_1                  (0x0002U << RI_HYSCR2_PD_Pos)          /*!< 0x00020000 */
6235 #define RI_HYSCR2_PD_2                  (0x0004U << RI_HYSCR2_PD_Pos)          /*!< 0x00040000 */
6236 #define RI_HYSCR2_PD_3                  (0x0008U << RI_HYSCR2_PD_Pos)          /*!< 0x00080000 */
6237 #define RI_HYSCR2_PD_4                  (0x0010U << RI_HYSCR2_PD_Pos)          /*!< 0x00100000 */
6238 #define RI_HYSCR2_PD_5                  (0x0020U << RI_HYSCR2_PD_Pos)          /*!< 0x00200000 */
6239 #define RI_HYSCR2_PD_6                  (0x0040U << RI_HYSCR2_PD_Pos)          /*!< 0x00400000 */
6240 #define RI_HYSCR2_PD_7                  (0x0080U << RI_HYSCR2_PD_Pos)          /*!< 0x00800000 */
6241 #define RI_HYSCR2_PD_8                  (0x0100U << RI_HYSCR2_PD_Pos)          /*!< 0x01000000 */
6242 #define RI_HYSCR2_PD_9                  (0x0200U << RI_HYSCR2_PD_Pos)          /*!< 0x02000000 */
6243 #define RI_HYSCR2_PD_10                 (0x0400U << RI_HYSCR2_PD_Pos)          /*!< 0x04000000 */
6244 #define RI_HYSCR2_PD_11                 (0x0800U << RI_HYSCR2_PD_Pos)          /*!< 0x08000000 */
6245 #define RI_HYSCR2_PD_12                 (0x1000U << RI_HYSCR2_PD_Pos)          /*!< 0x10000000 */
6246 #define RI_HYSCR2_PD_13                 (0x2000U << RI_HYSCR2_PD_Pos)          /*!< 0x20000000 */
6247 #define RI_HYSCR2_PD_14                 (0x4000U << RI_HYSCR2_PD_Pos)          /*!< 0x40000000 */
6248 #define RI_HYSCR2_PD_15                 (0x8000U << RI_HYSCR2_PD_Pos)          /*!< 0x80000000 */
6249 
6250 /********************  Bit definition for RI_HYSCR3 register  ********************/
6251 #define RI_HYSCR3_PE_Pos                (0U)
6252 #define RI_HYSCR3_PE_Msk                (0xFFFFU << RI_HYSCR3_PE_Pos)          /*!< 0x0000FFFF */
6253 #define RI_HYSCR3_PE                    RI_HYSCR3_PE_Msk                       /*!< PE[15:0] Port E Hysteresis selection */
6254 #define RI_HYSCR3_PE_0                  (0x0001U << RI_HYSCR3_PE_Pos)          /*!< 0x00000001 */
6255 #define RI_HYSCR3_PE_1                  (0x0002U << RI_HYSCR3_PE_Pos)          /*!< 0x00000002 */
6256 #define RI_HYSCR3_PE_2                  (0x0004U << RI_HYSCR3_PE_Pos)          /*!< 0x00000004 */
6257 #define RI_HYSCR3_PE_3                  (0x0008U << RI_HYSCR3_PE_Pos)          /*!< 0x00000008 */
6258 #define RI_HYSCR3_PE_4                  (0x0010U << RI_HYSCR3_PE_Pos)          /*!< 0x00000010 */
6259 #define RI_HYSCR3_PE_5                  (0x0020U << RI_HYSCR3_PE_Pos)          /*!< 0x00000020 */
6260 #define RI_HYSCR3_PE_6                  (0x0040U << RI_HYSCR3_PE_Pos)          /*!< 0x00000040 */
6261 #define RI_HYSCR3_PE_7                  (0x0080U << RI_HYSCR3_PE_Pos)          /*!< 0x00000080 */
6262 #define RI_HYSCR3_PE_8                  (0x0100U << RI_HYSCR3_PE_Pos)          /*!< 0x00000100 */
6263 #define RI_HYSCR3_PE_9                  (0x0200U << RI_HYSCR3_PE_Pos)          /*!< 0x00000200 */
6264 #define RI_HYSCR3_PE_10                 (0x0400U << RI_HYSCR3_PE_Pos)          /*!< 0x00000400 */
6265 #define RI_HYSCR3_PE_11                 (0x0800U << RI_HYSCR3_PE_Pos)          /*!< 0x00000800 */
6266 #define RI_HYSCR3_PE_12                 (0x1000U << RI_HYSCR3_PE_Pos)          /*!< 0x00001000 */
6267 #define RI_HYSCR3_PE_13                 (0x2000U << RI_HYSCR3_PE_Pos)          /*!< 0x00002000 */
6268 #define RI_HYSCR3_PE_14                 (0x4000U << RI_HYSCR3_PE_Pos)          /*!< 0x00004000 */
6269 #define RI_HYSCR3_PE_15                 (0x8000U << RI_HYSCR3_PE_Pos)          /*!< 0x00008000 */
6270 
6271 /********************  Bit definition for RI_ASMR1 register  ********************/
6272 #define RI_ASMR1_PA_Pos                 (0U)
6273 #define RI_ASMR1_PA_Msk                 (0xFFFFU << RI_ASMR1_PA_Pos)           /*!< 0x0000FFFF */
6274 #define RI_ASMR1_PA                     RI_ASMR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
6275 #define RI_ASMR1_PA_0                   (0x0001U << RI_ASMR1_PA_Pos)           /*!< 0x00000001 */
6276 #define RI_ASMR1_PA_1                   (0x0002U << RI_ASMR1_PA_Pos)           /*!< 0x00000002 */
6277 #define RI_ASMR1_PA_2                   (0x0004U << RI_ASMR1_PA_Pos)           /*!< 0x00000004 */
6278 #define RI_ASMR1_PA_3                   (0x0008U << RI_ASMR1_PA_Pos)           /*!< 0x00000008 */
6279 #define RI_ASMR1_PA_4                   (0x0010U << RI_ASMR1_PA_Pos)           /*!< 0x00000010 */
6280 #define RI_ASMR1_PA_5                   (0x0020U << RI_ASMR1_PA_Pos)           /*!< 0x00000020 */
6281 #define RI_ASMR1_PA_6                   (0x0040U << RI_ASMR1_PA_Pos)           /*!< 0x00000040 */
6282 #define RI_ASMR1_PA_7                   (0x0080U << RI_ASMR1_PA_Pos)           /*!< 0x00000080 */
6283 #define RI_ASMR1_PA_8                   (0x0100U << RI_ASMR1_PA_Pos)           /*!< 0x00000100 */
6284 #define RI_ASMR1_PA_9                   (0x0200U << RI_ASMR1_PA_Pos)           /*!< 0x00000200 */
6285 #define RI_ASMR1_PA_10                  (0x0400U << RI_ASMR1_PA_Pos)           /*!< 0x00000400 */
6286 #define RI_ASMR1_PA_11                  (0x0800U << RI_ASMR1_PA_Pos)           /*!< 0x00000800 */
6287 #define RI_ASMR1_PA_12                  (0x1000U << RI_ASMR1_PA_Pos)           /*!< 0x00001000 */
6288 #define RI_ASMR1_PA_13                  (0x2000U << RI_ASMR1_PA_Pos)           /*!< 0x00002000 */
6289 #define RI_ASMR1_PA_14                  (0x4000U << RI_ASMR1_PA_Pos)           /*!< 0x00004000 */
6290 #define RI_ASMR1_PA_15                  (0x8000U << RI_ASMR1_PA_Pos)           /*!< 0x00008000 */
6291 
6292 /********************  Bit definition for RI_CMR1 register  ********************/
6293 #define RI_CMR1_PA_Pos                  (0U)
6294 #define RI_CMR1_PA_Msk                  (0xFFFFU << RI_CMR1_PA_Pos)            /*!< 0x0000FFFF */
6295 #define RI_CMR1_PA                      RI_CMR1_PA_Msk                         /*!< PA[15:0] Port A selection*/
6296 #define RI_CMR1_PA_0                    (0x0001U << RI_CMR1_PA_Pos)            /*!< 0x00000001 */
6297 #define RI_CMR1_PA_1                    (0x0002U << RI_CMR1_PA_Pos)            /*!< 0x00000002 */
6298 #define RI_CMR1_PA_2                    (0x0004U << RI_CMR1_PA_Pos)            /*!< 0x00000004 */
6299 #define RI_CMR1_PA_3                    (0x0008U << RI_CMR1_PA_Pos)            /*!< 0x00000008 */
6300 #define RI_CMR1_PA_4                    (0x0010U << RI_CMR1_PA_Pos)            /*!< 0x00000010 */
6301 #define RI_CMR1_PA_5                    (0x0020U << RI_CMR1_PA_Pos)            /*!< 0x00000020 */
6302 #define RI_CMR1_PA_6                    (0x0040U << RI_CMR1_PA_Pos)            /*!< 0x00000040 */
6303 #define RI_CMR1_PA_7                    (0x0080U << RI_CMR1_PA_Pos)            /*!< 0x00000080 */
6304 #define RI_CMR1_PA_8                    (0x0100U << RI_CMR1_PA_Pos)            /*!< 0x00000100 */
6305 #define RI_CMR1_PA_9                    (0x0200U << RI_CMR1_PA_Pos)            /*!< 0x00000200 */
6306 #define RI_CMR1_PA_10                   (0x0400U << RI_CMR1_PA_Pos)            /*!< 0x00000400 */
6307 #define RI_CMR1_PA_11                   (0x0800U << RI_CMR1_PA_Pos)            /*!< 0x00000800 */
6308 #define RI_CMR1_PA_12                   (0x1000U << RI_CMR1_PA_Pos)            /*!< 0x00001000 */
6309 #define RI_CMR1_PA_13                   (0x2000U << RI_CMR1_PA_Pos)            /*!< 0x00002000 */
6310 #define RI_CMR1_PA_14                   (0x4000U << RI_CMR1_PA_Pos)            /*!< 0x00004000 */
6311 #define RI_CMR1_PA_15                   (0x8000U << RI_CMR1_PA_Pos)            /*!< 0x00008000 */
6312 
6313 /********************  Bit definition for RI_CICR1 register  ********************/
6314 #define RI_CICR1_PA_Pos                 (0U)
6315 #define RI_CICR1_PA_Msk                 (0xFFFFU << RI_CICR1_PA_Pos)           /*!< 0x0000FFFF */
6316 #define RI_CICR1_PA                     RI_CICR1_PA_Msk                        /*!< PA[15:0] Port A selection*/
6317 #define RI_CICR1_PA_0                   (0x0001U << RI_CICR1_PA_Pos)           /*!< 0x00000001 */
6318 #define RI_CICR1_PA_1                   (0x0002U << RI_CICR1_PA_Pos)           /*!< 0x00000002 */
6319 #define RI_CICR1_PA_2                   (0x0004U << RI_CICR1_PA_Pos)           /*!< 0x00000004 */
6320 #define RI_CICR1_PA_3                   (0x0008U << RI_CICR1_PA_Pos)           /*!< 0x00000008 */
6321 #define RI_CICR1_PA_4                   (0x0010U << RI_CICR1_PA_Pos)           /*!< 0x00000010 */
6322 #define RI_CICR1_PA_5                   (0x0020U << RI_CICR1_PA_Pos)           /*!< 0x00000020 */
6323 #define RI_CICR1_PA_6                   (0x0040U << RI_CICR1_PA_Pos)           /*!< 0x00000040 */
6324 #define RI_CICR1_PA_7                   (0x0080U << RI_CICR1_PA_Pos)           /*!< 0x00000080 */
6325 #define RI_CICR1_PA_8                   (0x0100U << RI_CICR1_PA_Pos)           /*!< 0x00000100 */
6326 #define RI_CICR1_PA_9                   (0x0200U << RI_CICR1_PA_Pos)           /*!< 0x00000200 */
6327 #define RI_CICR1_PA_10                  (0x0400U << RI_CICR1_PA_Pos)           /*!< 0x00000400 */
6328 #define RI_CICR1_PA_11                  (0x0800U << RI_CICR1_PA_Pos)           /*!< 0x00000800 */
6329 #define RI_CICR1_PA_12                  (0x1000U << RI_CICR1_PA_Pos)           /*!< 0x00001000 */
6330 #define RI_CICR1_PA_13                  (0x2000U << RI_CICR1_PA_Pos)           /*!< 0x00002000 */
6331 #define RI_CICR1_PA_14                  (0x4000U << RI_CICR1_PA_Pos)           /*!< 0x00004000 */
6332 #define RI_CICR1_PA_15                  (0x8000U << RI_CICR1_PA_Pos)           /*!< 0x00008000 */
6333 
6334 /********************  Bit definition for RI_ASMR2 register  ********************/
6335 #define RI_ASMR2_PB_Pos                 (0U)
6336 #define RI_ASMR2_PB_Msk                 (0xFFFFU << RI_ASMR2_PB_Pos)           /*!< 0x0000FFFF */
6337 #define RI_ASMR2_PB                     RI_ASMR2_PB_Msk                        /*!< PB[15:0] Port B selection */
6338 #define RI_ASMR2_PB_0                   (0x0001U << RI_ASMR2_PB_Pos)           /*!< 0x00000001 */
6339 #define RI_ASMR2_PB_1                   (0x0002U << RI_ASMR2_PB_Pos)           /*!< 0x00000002 */
6340 #define RI_ASMR2_PB_2                   (0x0004U << RI_ASMR2_PB_Pos)           /*!< 0x00000004 */
6341 #define RI_ASMR2_PB_3                   (0x0008U << RI_ASMR2_PB_Pos)           /*!< 0x00000008 */
6342 #define RI_ASMR2_PB_4                   (0x0010U << RI_ASMR2_PB_Pos)           /*!< 0x00000010 */
6343 #define RI_ASMR2_PB_5                   (0x0020U << RI_ASMR2_PB_Pos)           /*!< 0x00000020 */
6344 #define RI_ASMR2_PB_6                   (0x0040U << RI_ASMR2_PB_Pos)           /*!< 0x00000040 */
6345 #define RI_ASMR2_PB_7                   (0x0080U << RI_ASMR2_PB_Pos)           /*!< 0x00000080 */
6346 #define RI_ASMR2_PB_8                   (0x0100U << RI_ASMR2_PB_Pos)           /*!< 0x00000100 */
6347 #define RI_ASMR2_PB_9                   (0x0200U << RI_ASMR2_PB_Pos)           /*!< 0x00000200 */
6348 #define RI_ASMR2_PB_10                  (0x0400U << RI_ASMR2_PB_Pos)           /*!< 0x00000400 */
6349 #define RI_ASMR2_PB_11                  (0x0800U << RI_ASMR2_PB_Pos)           /*!< 0x00000800 */
6350 #define RI_ASMR2_PB_12                  (0x1000U << RI_ASMR2_PB_Pos)           /*!< 0x00001000 */
6351 #define RI_ASMR2_PB_13                  (0x2000U << RI_ASMR2_PB_Pos)           /*!< 0x00002000 */
6352 #define RI_ASMR2_PB_14                  (0x4000U << RI_ASMR2_PB_Pos)           /*!< 0x00004000 */
6353 #define RI_ASMR2_PB_15                  (0x8000U << RI_ASMR2_PB_Pos)           /*!< 0x00008000 */
6354 
6355 /********************  Bit definition for RI_CMR2 register  ********************/
6356 #define RI_CMR2_PB_Pos                  (0U)
6357 #define RI_CMR2_PB_Msk                  (0xFFFFU << RI_CMR2_PB_Pos)            /*!< 0x0000FFFF */
6358 #define RI_CMR2_PB                      RI_CMR2_PB_Msk                         /*!< PB[15:0] Port B selection */
6359 #define RI_CMR2_PB_0                    (0x0001U << RI_CMR2_PB_Pos)            /*!< 0x00000001 */
6360 #define RI_CMR2_PB_1                    (0x0002U << RI_CMR2_PB_Pos)            /*!< 0x00000002 */
6361 #define RI_CMR2_PB_2                    (0x0004U << RI_CMR2_PB_Pos)            /*!< 0x00000004 */
6362 #define RI_CMR2_PB_3                    (0x0008U << RI_CMR2_PB_Pos)            /*!< 0x00000008 */
6363 #define RI_CMR2_PB_4                    (0x0010U << RI_CMR2_PB_Pos)            /*!< 0x00000010 */
6364 #define RI_CMR2_PB_5                    (0x0020U << RI_CMR2_PB_Pos)            /*!< 0x00000020 */
6365 #define RI_CMR2_PB_6                    (0x0040U << RI_CMR2_PB_Pos)            /*!< 0x00000040 */
6366 #define RI_CMR2_PB_7                    (0x0080U << RI_CMR2_PB_Pos)            /*!< 0x00000080 */
6367 #define RI_CMR2_PB_8                    (0x0100U << RI_CMR2_PB_Pos)            /*!< 0x00000100 */
6368 #define RI_CMR2_PB_9                    (0x0200U << RI_CMR2_PB_Pos)            /*!< 0x00000200 */
6369 #define RI_CMR2_PB_10                   (0x0400U << RI_CMR2_PB_Pos)            /*!< 0x00000400 */
6370 #define RI_CMR2_PB_11                   (0x0800U << RI_CMR2_PB_Pos)            /*!< 0x00000800 */
6371 #define RI_CMR2_PB_12                   (0x1000U << RI_CMR2_PB_Pos)            /*!< 0x00001000 */
6372 #define RI_CMR2_PB_13                   (0x2000U << RI_CMR2_PB_Pos)            /*!< 0x00002000 */
6373 #define RI_CMR2_PB_14                   (0x4000U << RI_CMR2_PB_Pos)            /*!< 0x00004000 */
6374 #define RI_CMR2_PB_15                   (0x8000U << RI_CMR2_PB_Pos)            /*!< 0x00008000 */
6375 
6376 /********************  Bit definition for RI_CICR2 register  ********************/
6377 #define RI_CICR2_PB_Pos                 (0U)
6378 #define RI_CICR2_PB_Msk                 (0xFFFFU << RI_CICR2_PB_Pos)           /*!< 0x0000FFFF */
6379 #define RI_CICR2_PB                     RI_CICR2_PB_Msk                        /*!< PB[15:0] Port B selection */
6380 #define RI_CICR2_PB_0                   (0x0001U << RI_CICR2_PB_Pos)           /*!< 0x00000001 */
6381 #define RI_CICR2_PB_1                   (0x0002U << RI_CICR2_PB_Pos)           /*!< 0x00000002 */
6382 #define RI_CICR2_PB_2                   (0x0004U << RI_CICR2_PB_Pos)           /*!< 0x00000004 */
6383 #define RI_CICR2_PB_3                   (0x0008U << RI_CICR2_PB_Pos)           /*!< 0x00000008 */
6384 #define RI_CICR2_PB_4                   (0x0010U << RI_CICR2_PB_Pos)           /*!< 0x00000010 */
6385 #define RI_CICR2_PB_5                   (0x0020U << RI_CICR2_PB_Pos)           /*!< 0x00000020 */
6386 #define RI_CICR2_PB_6                   (0x0040U << RI_CICR2_PB_Pos)           /*!< 0x00000040 */
6387 #define RI_CICR2_PB_7                   (0x0080U << RI_CICR2_PB_Pos)           /*!< 0x00000080 */
6388 #define RI_CICR2_PB_8                   (0x0100U << RI_CICR2_PB_Pos)           /*!< 0x00000100 */
6389 #define RI_CICR2_PB_9                   (0x0200U << RI_CICR2_PB_Pos)           /*!< 0x00000200 */
6390 #define RI_CICR2_PB_10                  (0x0400U << RI_CICR2_PB_Pos)           /*!< 0x00000400 */
6391 #define RI_CICR2_PB_11                  (0x0800U << RI_CICR2_PB_Pos)           /*!< 0x00000800 */
6392 #define RI_CICR2_PB_12                  (0x1000U << RI_CICR2_PB_Pos)           /*!< 0x00001000 */
6393 #define RI_CICR2_PB_13                  (0x2000U << RI_CICR2_PB_Pos)           /*!< 0x00002000 */
6394 #define RI_CICR2_PB_14                  (0x4000U << RI_CICR2_PB_Pos)           /*!< 0x00004000 */
6395 #define RI_CICR2_PB_15                  (0x8000U << RI_CICR2_PB_Pos)           /*!< 0x00008000 */
6396 
6397 /********************  Bit definition for RI_ASMR3 register  ********************/
6398 #define RI_ASMR3_PC_Pos                 (0U)
6399 #define RI_ASMR3_PC_Msk                 (0xFFFFU << RI_ASMR3_PC_Pos)           /*!< 0x0000FFFF */
6400 #define RI_ASMR3_PC                     RI_ASMR3_PC_Msk                        /*!< PC[15:0] Port C selection */
6401 #define RI_ASMR3_PC_0                   (0x0001U << RI_ASMR3_PC_Pos)           /*!< 0x00000001 */
6402 #define RI_ASMR3_PC_1                   (0x0002U << RI_ASMR3_PC_Pos)           /*!< 0x00000002 */
6403 #define RI_ASMR3_PC_2                   (0x0004U << RI_ASMR3_PC_Pos)           /*!< 0x00000004 */
6404 #define RI_ASMR3_PC_3                   (0x0008U << RI_ASMR3_PC_Pos)           /*!< 0x00000008 */
6405 #define RI_ASMR3_PC_4                   (0x0010U << RI_ASMR3_PC_Pos)           /*!< 0x00000010 */
6406 #define RI_ASMR3_PC_5                   (0x0020U << RI_ASMR3_PC_Pos)           /*!< 0x00000020 */
6407 #define RI_ASMR3_PC_6                   (0x0040U << RI_ASMR3_PC_Pos)           /*!< 0x00000040 */
6408 #define RI_ASMR3_PC_7                   (0x0080U << RI_ASMR3_PC_Pos)           /*!< 0x00000080 */
6409 #define RI_ASMR3_PC_8                   (0x0100U << RI_ASMR3_PC_Pos)           /*!< 0x00000100 */
6410 #define RI_ASMR3_PC_9                   (0x0200U << RI_ASMR3_PC_Pos)           /*!< 0x00000200 */
6411 #define RI_ASMR3_PC_10                  (0x0400U << RI_ASMR3_PC_Pos)           /*!< 0x00000400 */
6412 #define RI_ASMR3_PC_11                  (0x0800U << RI_ASMR3_PC_Pos)           /*!< 0x00000800 */
6413 #define RI_ASMR3_PC_12                  (0x1000U << RI_ASMR3_PC_Pos)           /*!< 0x00001000 */
6414 #define RI_ASMR3_PC_13                  (0x2000U << RI_ASMR3_PC_Pos)           /*!< 0x00002000 */
6415 #define RI_ASMR3_PC_14                  (0x4000U << RI_ASMR3_PC_Pos)           /*!< 0x00004000 */
6416 #define RI_ASMR3_PC_15                  (0x8000U << RI_ASMR3_PC_Pos)           /*!< 0x00008000 */
6417 
6418 /********************  Bit definition for RI_CMR3 register  ********************/
6419 #define RI_CMR3_PC_Pos                  (0U)
6420 #define RI_CMR3_PC_Msk                  (0xFFFFU << RI_CMR3_PC_Pos)            /*!< 0x0000FFFF */
6421 #define RI_CMR3_PC                      RI_CMR3_PC_Msk                         /*!< PC[15:0] Port C selection */
6422 #define RI_CMR3_PC_0                    (0x0001U << RI_CMR3_PC_Pos)            /*!< 0x00000001 */
6423 #define RI_CMR3_PC_1                    (0x0002U << RI_CMR3_PC_Pos)            /*!< 0x00000002 */
6424 #define RI_CMR3_PC_2                    (0x0004U << RI_CMR3_PC_Pos)            /*!< 0x00000004 */
6425 #define RI_CMR3_PC_3                    (0x0008U << RI_CMR3_PC_Pos)            /*!< 0x00000008 */
6426 #define RI_CMR3_PC_4                    (0x0010U << RI_CMR3_PC_Pos)            /*!< 0x00000010 */
6427 #define RI_CMR3_PC_5                    (0x0020U << RI_CMR3_PC_Pos)            /*!< 0x00000020 */
6428 #define RI_CMR3_PC_6                    (0x0040U << RI_CMR3_PC_Pos)            /*!< 0x00000040 */
6429 #define RI_CMR3_PC_7                    (0x0080U << RI_CMR3_PC_Pos)            /*!< 0x00000080 */
6430 #define RI_CMR3_PC_8                    (0x0100U << RI_CMR3_PC_Pos)            /*!< 0x00000100 */
6431 #define RI_CMR3_PC_9                    (0x0200U << RI_CMR3_PC_Pos)            /*!< 0x00000200 */
6432 #define RI_CMR3_PC_10                   (0x0400U << RI_CMR3_PC_Pos)            /*!< 0x00000400 */
6433 #define RI_CMR3_PC_11                   (0x0800U << RI_CMR3_PC_Pos)            /*!< 0x00000800 */
6434 #define RI_CMR3_PC_12                   (0x1000U << RI_CMR3_PC_Pos)            /*!< 0x00001000 */
6435 #define RI_CMR3_PC_13                   (0x2000U << RI_CMR3_PC_Pos)            /*!< 0x00002000 */
6436 #define RI_CMR3_PC_14                   (0x4000U << RI_CMR3_PC_Pos)            /*!< 0x00004000 */
6437 #define RI_CMR3_PC_15                   (0x8000U << RI_CMR3_PC_Pos)            /*!< 0x00008000 */
6438 
6439 /********************  Bit definition for RI_CICR3 register  ********************/
6440 #define RI_CICR3_PC_Pos                 (0U)
6441 #define RI_CICR3_PC_Msk                 (0xFFFFU << RI_CICR3_PC_Pos)           /*!< 0x0000FFFF */
6442 #define RI_CICR3_PC                     RI_CICR3_PC_Msk                        /*!< PC[15:0] Port C selection */
6443 #define RI_CICR3_PC_0                   (0x0001U << RI_CICR3_PC_Pos)           /*!< 0x00000001 */
6444 #define RI_CICR3_PC_1                   (0x0002U << RI_CICR3_PC_Pos)           /*!< 0x00000002 */
6445 #define RI_CICR3_PC_2                   (0x0004U << RI_CICR3_PC_Pos)           /*!< 0x00000004 */
6446 #define RI_CICR3_PC_3                   (0x0008U << RI_CICR3_PC_Pos)           /*!< 0x00000008 */
6447 #define RI_CICR3_PC_4                   (0x0010U << RI_CICR3_PC_Pos)           /*!< 0x00000010 */
6448 #define RI_CICR3_PC_5                   (0x0020U << RI_CICR3_PC_Pos)           /*!< 0x00000020 */
6449 #define RI_CICR3_PC_6                   (0x0040U << RI_CICR3_PC_Pos)           /*!< 0x00000040 */
6450 #define RI_CICR3_PC_7                   (0x0080U << RI_CICR3_PC_Pos)           /*!< 0x00000080 */
6451 #define RI_CICR3_PC_8                   (0x0100U << RI_CICR3_PC_Pos)           /*!< 0x00000100 */
6452 #define RI_CICR3_PC_9                   (0x0200U << RI_CICR3_PC_Pos)           /*!< 0x00000200 */
6453 #define RI_CICR3_PC_10                  (0x0400U << RI_CICR3_PC_Pos)           /*!< 0x00000400 */
6454 #define RI_CICR3_PC_11                  (0x0800U << RI_CICR3_PC_Pos)           /*!< 0x00000800 */
6455 #define RI_CICR3_PC_12                  (0x1000U << RI_CICR3_PC_Pos)           /*!< 0x00001000 */
6456 #define RI_CICR3_PC_13                  (0x2000U << RI_CICR3_PC_Pos)           /*!< 0x00002000 */
6457 #define RI_CICR3_PC_14                  (0x4000U << RI_CICR3_PC_Pos)           /*!< 0x00004000 */
6458 #define RI_CICR3_PC_15                  (0x8000U << RI_CICR3_PC_Pos)           /*!< 0x00008000 */
6459 
6460 /******************************************************************************/
6461 /*                                                                            */
6462 /*                               Timers (TIM)                                 */
6463 /*                                                                            */
6464 /******************************************************************************/
6465 
6466 /*******************  Bit definition for TIM_CR1 register  ********************/
6467 #define TIM_CR1_CEN_Pos                     (0U)
6468 #define TIM_CR1_CEN_Msk                     (0x1U << TIM_CR1_CEN_Pos)          /*!< 0x00000001 */
6469 #define TIM_CR1_CEN                         TIM_CR1_CEN_Msk                    /*!<Counter enable */
6470 #define TIM_CR1_UDIS_Pos                    (1U)
6471 #define TIM_CR1_UDIS_Msk                    (0x1U << TIM_CR1_UDIS_Pos)         /*!< 0x00000002 */
6472 #define TIM_CR1_UDIS                        TIM_CR1_UDIS_Msk                   /*!<Update disable */
6473 #define TIM_CR1_URS_Pos                     (2U)
6474 #define TIM_CR1_URS_Msk                     (0x1U << TIM_CR1_URS_Pos)          /*!< 0x00000004 */
6475 #define TIM_CR1_URS                         TIM_CR1_URS_Msk                    /*!<Update request source */
6476 #define TIM_CR1_OPM_Pos                     (3U)
6477 #define TIM_CR1_OPM_Msk                     (0x1U << TIM_CR1_OPM_Pos)          /*!< 0x00000008 */
6478 #define TIM_CR1_OPM                         TIM_CR1_OPM_Msk                    /*!<One pulse mode */
6479 #define TIM_CR1_DIR_Pos                     (4U)
6480 #define TIM_CR1_DIR_Msk                     (0x1U << TIM_CR1_DIR_Pos)          /*!< 0x00000010 */
6481 #define TIM_CR1_DIR                         TIM_CR1_DIR_Msk                    /*!<Direction */
6482 
6483 #define TIM_CR1_CMS_Pos                     (5U)
6484 #define TIM_CR1_CMS_Msk                     (0x3U << TIM_CR1_CMS_Pos)          /*!< 0x00000060 */
6485 #define TIM_CR1_CMS                         TIM_CR1_CMS_Msk                    /*!<CMS[1:0] bits (Center-aligned mode selection) */
6486 #define TIM_CR1_CMS_0                       (0x1U << TIM_CR1_CMS_Pos)          /*!< 0x00000020 */
6487 #define TIM_CR1_CMS_1                       (0x2U << TIM_CR1_CMS_Pos)          /*!< 0x00000040 */
6488 
6489 #define TIM_CR1_ARPE_Pos                    (7U)
6490 #define TIM_CR1_ARPE_Msk                    (0x1U << TIM_CR1_ARPE_Pos)         /*!< 0x00000080 */
6491 #define TIM_CR1_ARPE                        TIM_CR1_ARPE_Msk                   /*!<Auto-reload preload enable */
6492 
6493 #define TIM_CR1_CKD_Pos                     (8U)
6494 #define TIM_CR1_CKD_Msk                     (0x3U << TIM_CR1_CKD_Pos)          /*!< 0x00000300 */
6495 #define TIM_CR1_CKD                         TIM_CR1_CKD_Msk                    /*!<CKD[1:0] bits (clock division) */
6496 #define TIM_CR1_CKD_0                       (0x1U << TIM_CR1_CKD_Pos)          /*!< 0x00000100 */
6497 #define TIM_CR1_CKD_1                       (0x2U << TIM_CR1_CKD_Pos)          /*!< 0x00000200 */
6498 
6499 /*******************  Bit definition for TIM_CR2 register  ********************/
6500 #define TIM_CR2_CCDS_Pos                    (3U)
6501 #define TIM_CR2_CCDS_Msk                    (0x1U << TIM_CR2_CCDS_Pos)         /*!< 0x00000008 */
6502 #define TIM_CR2_CCDS                        TIM_CR2_CCDS_Msk                   /*!<Capture/Compare DMA Selection */
6503 
6504 #define TIM_CR2_MMS_Pos                     (4U)
6505 #define TIM_CR2_MMS_Msk                     (0x7U << TIM_CR2_MMS_Pos)          /*!< 0x00000070 */
6506 #define TIM_CR2_MMS                         TIM_CR2_MMS_Msk                    /*!<MMS[2:0] bits (Master Mode Selection) */
6507 #define TIM_CR2_MMS_0                       (0x1U << TIM_CR2_MMS_Pos)          /*!< 0x00000010 */
6508 #define TIM_CR2_MMS_1                       (0x2U << TIM_CR2_MMS_Pos)          /*!< 0x00000020 */
6509 #define TIM_CR2_MMS_2                       (0x4U << TIM_CR2_MMS_Pos)          /*!< 0x00000040 */
6510 
6511 #define TIM_CR2_TI1S_Pos                    (7U)
6512 #define TIM_CR2_TI1S_Msk                    (0x1U << TIM_CR2_TI1S_Pos)         /*!< 0x00000080 */
6513 #define TIM_CR2_TI1S                        TIM_CR2_TI1S_Msk                   /*!<TI1 Selection */
6514 
6515 /*******************  Bit definition for TIM_SMCR register  *******************/
6516 #define TIM_SMCR_SMS_Pos                    (0U)
6517 #define TIM_SMCR_SMS_Msk                    (0x7U << TIM_SMCR_SMS_Pos)         /*!< 0x00000007 */
6518 #define TIM_SMCR_SMS                        TIM_SMCR_SMS_Msk                   /*!<SMS[2:0] bits (Slave mode selection) */
6519 #define TIM_SMCR_SMS_0                      (0x1U << TIM_SMCR_SMS_Pos)         /*!< 0x00000001 */
6520 #define TIM_SMCR_SMS_1                      (0x2U << TIM_SMCR_SMS_Pos)         /*!< 0x00000002 */
6521 #define TIM_SMCR_SMS_2                      (0x4U << TIM_SMCR_SMS_Pos)         /*!< 0x00000004 */
6522 
6523 #define TIM_SMCR_OCCS_Pos                   (3U)
6524 #define TIM_SMCR_OCCS_Msk                   (0x1U << TIM_SMCR_OCCS_Pos)        /*!< 0x00000008 */
6525 #define TIM_SMCR_OCCS                       TIM_SMCR_OCCS_Msk                  /*!< OCREF clear selection */
6526 
6527 #define TIM_SMCR_TS_Pos                     (4U)
6528 #define TIM_SMCR_TS_Msk                     (0x7U << TIM_SMCR_TS_Pos)          /*!< 0x00000070 */
6529 #define TIM_SMCR_TS                         TIM_SMCR_TS_Msk                    /*!<TS[2:0] bits (Trigger selection) */
6530 #define TIM_SMCR_TS_0                       (0x1U << TIM_SMCR_TS_Pos)          /*!< 0x00000010 */
6531 #define TIM_SMCR_TS_1                       (0x2U << TIM_SMCR_TS_Pos)          /*!< 0x00000020 */
6532 #define TIM_SMCR_TS_2                       (0x4U << TIM_SMCR_TS_Pos)          /*!< 0x00000040 */
6533 
6534 #define TIM_SMCR_MSM_Pos                    (7U)
6535 #define TIM_SMCR_MSM_Msk                    (0x1U << TIM_SMCR_MSM_Pos)         /*!< 0x00000080 */
6536 #define TIM_SMCR_MSM                        TIM_SMCR_MSM_Msk                   /*!<Master/slave mode */
6537 
6538 #define TIM_SMCR_ETF_Pos                    (8U)
6539 #define TIM_SMCR_ETF_Msk                    (0xFU << TIM_SMCR_ETF_Pos)         /*!< 0x00000F00 */
6540 #define TIM_SMCR_ETF                        TIM_SMCR_ETF_Msk                   /*!<ETF[3:0] bits (External trigger filter) */
6541 #define TIM_SMCR_ETF_0                      (0x1U << TIM_SMCR_ETF_Pos)         /*!< 0x00000100 */
6542 #define TIM_SMCR_ETF_1                      (0x2U << TIM_SMCR_ETF_Pos)         /*!< 0x00000200 */
6543 #define TIM_SMCR_ETF_2                      (0x4U << TIM_SMCR_ETF_Pos)         /*!< 0x00000400 */
6544 #define TIM_SMCR_ETF_3                      (0x8U << TIM_SMCR_ETF_Pos)         /*!< 0x00000800 */
6545 
6546 #define TIM_SMCR_ETPS_Pos                   (12U)
6547 #define TIM_SMCR_ETPS_Msk                   (0x3U << TIM_SMCR_ETPS_Pos)        /*!< 0x00003000 */
6548 #define TIM_SMCR_ETPS                       TIM_SMCR_ETPS_Msk                  /*!<ETPS[1:0] bits (External trigger prescaler) */
6549 #define TIM_SMCR_ETPS_0                     (0x1U << TIM_SMCR_ETPS_Pos)        /*!< 0x00001000 */
6550 #define TIM_SMCR_ETPS_1                     (0x2U << TIM_SMCR_ETPS_Pos)        /*!< 0x00002000 */
6551 
6552 #define TIM_SMCR_ECE_Pos                    (14U)
6553 #define TIM_SMCR_ECE_Msk                    (0x1U << TIM_SMCR_ECE_Pos)         /*!< 0x00004000 */
6554 #define TIM_SMCR_ECE                        TIM_SMCR_ECE_Msk                   /*!<External clock enable */
6555 #define TIM_SMCR_ETP_Pos                    (15U)
6556 #define TIM_SMCR_ETP_Msk                    (0x1U << TIM_SMCR_ETP_Pos)         /*!< 0x00008000 */
6557 #define TIM_SMCR_ETP                        TIM_SMCR_ETP_Msk                   /*!<External trigger polarity */
6558 
6559 /*******************  Bit definition for TIM_DIER register  *******************/
6560 #define TIM_DIER_UIE_Pos                    (0U)
6561 #define TIM_DIER_UIE_Msk                    (0x1U << TIM_DIER_UIE_Pos)         /*!< 0x00000001 */
6562 #define TIM_DIER_UIE                        TIM_DIER_UIE_Msk                   /*!<Update interrupt enable */
6563 #define TIM_DIER_CC1IE_Pos                  (1U)
6564 #define TIM_DIER_CC1IE_Msk                  (0x1U << TIM_DIER_CC1IE_Pos)       /*!< 0x00000002 */
6565 #define TIM_DIER_CC1IE                      TIM_DIER_CC1IE_Msk                 /*!<Capture/Compare 1 interrupt enable */
6566 #define TIM_DIER_CC2IE_Pos                  (2U)
6567 #define TIM_DIER_CC2IE_Msk                  (0x1U << TIM_DIER_CC2IE_Pos)       /*!< 0x00000004 */
6568 #define TIM_DIER_CC2IE                      TIM_DIER_CC2IE_Msk                 /*!<Capture/Compare 2 interrupt enable */
6569 #define TIM_DIER_CC3IE_Pos                  (3U)
6570 #define TIM_DIER_CC3IE_Msk                  (0x1U << TIM_DIER_CC3IE_Pos)       /*!< 0x00000008 */
6571 #define TIM_DIER_CC3IE                      TIM_DIER_CC3IE_Msk                 /*!<Capture/Compare 3 interrupt enable */
6572 #define TIM_DIER_CC4IE_Pos                  (4U)
6573 #define TIM_DIER_CC4IE_Msk                  (0x1U << TIM_DIER_CC4IE_Pos)       /*!< 0x00000010 */
6574 #define TIM_DIER_CC4IE                      TIM_DIER_CC4IE_Msk                 /*!<Capture/Compare 4 interrupt enable */
6575 #define TIM_DIER_TIE_Pos                    (6U)
6576 #define TIM_DIER_TIE_Msk                    (0x1U << TIM_DIER_TIE_Pos)         /*!< 0x00000040 */
6577 #define TIM_DIER_TIE                        TIM_DIER_TIE_Msk                   /*!<Trigger interrupt enable */
6578 #define TIM_DIER_UDE_Pos                    (8U)
6579 #define TIM_DIER_UDE_Msk                    (0x1U << TIM_DIER_UDE_Pos)         /*!< 0x00000100 */
6580 #define TIM_DIER_UDE                        TIM_DIER_UDE_Msk                   /*!<Update DMA request enable */
6581 #define TIM_DIER_CC1DE_Pos                  (9U)
6582 #define TIM_DIER_CC1DE_Msk                  (0x1U << TIM_DIER_CC1DE_Pos)       /*!< 0x00000200 */
6583 #define TIM_DIER_CC1DE                      TIM_DIER_CC1DE_Msk                 /*!<Capture/Compare 1 DMA request enable */
6584 #define TIM_DIER_CC2DE_Pos                  (10U)
6585 #define TIM_DIER_CC2DE_Msk                  (0x1U << TIM_DIER_CC2DE_Pos)       /*!< 0x00000400 */
6586 #define TIM_DIER_CC2DE                      TIM_DIER_CC2DE_Msk                 /*!<Capture/Compare 2 DMA request enable */
6587 #define TIM_DIER_CC3DE_Pos                  (11U)
6588 #define TIM_DIER_CC3DE_Msk                  (0x1U << TIM_DIER_CC3DE_Pos)       /*!< 0x00000800 */
6589 #define TIM_DIER_CC3DE                      TIM_DIER_CC3DE_Msk                 /*!<Capture/Compare 3 DMA request enable */
6590 #define TIM_DIER_CC4DE_Pos                  (12U)
6591 #define TIM_DIER_CC4DE_Msk                  (0x1U << TIM_DIER_CC4DE_Pos)       /*!< 0x00001000 */
6592 #define TIM_DIER_CC4DE                      TIM_DIER_CC4DE_Msk                 /*!<Capture/Compare 4 DMA request enable */
6593 #define TIM_DIER_COMDE                      ((uint16_t)0x2000U)                /*!<COM DMA request enable */
6594 #define TIM_DIER_TDE_Pos                    (14U)
6595 #define TIM_DIER_TDE_Msk                    (0x1U << TIM_DIER_TDE_Pos)         /*!< 0x00004000 */
6596 #define TIM_DIER_TDE                        TIM_DIER_TDE_Msk                   /*!<Trigger DMA request enable */
6597 
6598 /********************  Bit definition for TIM_SR register  ********************/
6599 #define TIM_SR_UIF_Pos                      (0U)
6600 #define TIM_SR_UIF_Msk                      (0x1U << TIM_SR_UIF_Pos)           /*!< 0x00000001 */
6601 #define TIM_SR_UIF                          TIM_SR_UIF_Msk                     /*!<Update interrupt Flag */
6602 #define TIM_SR_CC1IF_Pos                    (1U)
6603 #define TIM_SR_CC1IF_Msk                    (0x1U << TIM_SR_CC1IF_Pos)         /*!< 0x00000002 */
6604 #define TIM_SR_CC1IF                        TIM_SR_CC1IF_Msk                   /*!<Capture/Compare 1 interrupt Flag */
6605 #define TIM_SR_CC2IF_Pos                    (2U)
6606 #define TIM_SR_CC2IF_Msk                    (0x1U << TIM_SR_CC2IF_Pos)         /*!< 0x00000004 */
6607 #define TIM_SR_CC2IF                        TIM_SR_CC2IF_Msk                   /*!<Capture/Compare 2 interrupt Flag */
6608 #define TIM_SR_CC3IF_Pos                    (3U)
6609 #define TIM_SR_CC3IF_Msk                    (0x1U << TIM_SR_CC3IF_Pos)         /*!< 0x00000008 */
6610 #define TIM_SR_CC3IF                        TIM_SR_CC3IF_Msk                   /*!<Capture/Compare 3 interrupt Flag */
6611 #define TIM_SR_CC4IF_Pos                    (4U)
6612 #define TIM_SR_CC4IF_Msk                    (0x1U << TIM_SR_CC4IF_Pos)         /*!< 0x00000010 */
6613 #define TIM_SR_CC4IF                        TIM_SR_CC4IF_Msk                   /*!<Capture/Compare 4 interrupt Flag */
6614 #define TIM_SR_TIF_Pos                      (6U)
6615 #define TIM_SR_TIF_Msk                      (0x1U << TIM_SR_TIF_Pos)           /*!< 0x00000040 */
6616 #define TIM_SR_TIF                          TIM_SR_TIF_Msk                     /*!<Trigger interrupt Flag */
6617 #define TIM_SR_CC1OF_Pos                    (9U)
6618 #define TIM_SR_CC1OF_Msk                    (0x1U << TIM_SR_CC1OF_Pos)         /*!< 0x00000200 */
6619 #define TIM_SR_CC1OF                        TIM_SR_CC1OF_Msk                   /*!<Capture/Compare 1 Overcapture Flag */
6620 #define TIM_SR_CC2OF_Pos                    (10U)
6621 #define TIM_SR_CC2OF_Msk                    (0x1U << TIM_SR_CC2OF_Pos)         /*!< 0x00000400 */
6622 #define TIM_SR_CC2OF                        TIM_SR_CC2OF_Msk                   /*!<Capture/Compare 2 Overcapture Flag */
6623 #define TIM_SR_CC3OF_Pos                    (11U)
6624 #define TIM_SR_CC3OF_Msk                    (0x1U << TIM_SR_CC3OF_Pos)         /*!< 0x00000800 */
6625 #define TIM_SR_CC3OF                        TIM_SR_CC3OF_Msk                   /*!<Capture/Compare 3 Overcapture Flag */
6626 #define TIM_SR_CC4OF_Pos                    (12U)
6627 #define TIM_SR_CC4OF_Msk                    (0x1U << TIM_SR_CC4OF_Pos)         /*!< 0x00001000 */
6628 #define TIM_SR_CC4OF                        TIM_SR_CC4OF_Msk                   /*!<Capture/Compare 4 Overcapture Flag */
6629 
6630 /*******************  Bit definition for TIM_EGR register  ********************/
6631 #define TIM_EGR_UG_Pos                      (0U)
6632 #define TIM_EGR_UG_Msk                      (0x1U << TIM_EGR_UG_Pos)           /*!< 0x00000001 */
6633 #define TIM_EGR_UG                          TIM_EGR_UG_Msk                     /*!<Update Generation */
6634 #define TIM_EGR_CC1G_Pos                    (1U)
6635 #define TIM_EGR_CC1G_Msk                    (0x1U << TIM_EGR_CC1G_Pos)         /*!< 0x00000002 */
6636 #define TIM_EGR_CC1G                        TIM_EGR_CC1G_Msk                   /*!<Capture/Compare 1 Generation */
6637 #define TIM_EGR_CC2G_Pos                    (2U)
6638 #define TIM_EGR_CC2G_Msk                    (0x1U << TIM_EGR_CC2G_Pos)         /*!< 0x00000004 */
6639 #define TIM_EGR_CC2G                        TIM_EGR_CC2G_Msk                   /*!<Capture/Compare 2 Generation */
6640 #define TIM_EGR_CC3G_Pos                    (3U)
6641 #define TIM_EGR_CC3G_Msk                    (0x1U << TIM_EGR_CC3G_Pos)         /*!< 0x00000008 */
6642 #define TIM_EGR_CC3G                        TIM_EGR_CC3G_Msk                   /*!<Capture/Compare 3 Generation */
6643 #define TIM_EGR_CC4G_Pos                    (4U)
6644 #define TIM_EGR_CC4G_Msk                    (0x1U << TIM_EGR_CC4G_Pos)         /*!< 0x00000010 */
6645 #define TIM_EGR_CC4G                        TIM_EGR_CC4G_Msk                   /*!<Capture/Compare 4 Generation */
6646 #define TIM_EGR_TG_Pos                      (6U)
6647 #define TIM_EGR_TG_Msk                      (0x1U << TIM_EGR_TG_Pos)           /*!< 0x00000040 */
6648 #define TIM_EGR_TG                          TIM_EGR_TG_Msk                     /*!<Trigger Generation */
6649 
6650 /******************  Bit definition for TIM_CCMR1 register  *******************/
6651 #define TIM_CCMR1_CC1S_Pos                  (0U)
6652 #define TIM_CCMR1_CC1S_Msk                  (0x3U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000003 */
6653 #define TIM_CCMR1_CC1S                      TIM_CCMR1_CC1S_Msk                 /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
6654 #define TIM_CCMR1_CC1S_0                    (0x1U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000001 */
6655 #define TIM_CCMR1_CC1S_1                    (0x2U << TIM_CCMR1_CC1S_Pos)       /*!< 0x00000002 */
6656 
6657 #define TIM_CCMR1_OC1FE_Pos                 (2U)
6658 #define TIM_CCMR1_OC1FE_Msk                 (0x1U << TIM_CCMR1_OC1FE_Pos)      /*!< 0x00000004 */
6659 #define TIM_CCMR1_OC1FE                     TIM_CCMR1_OC1FE_Msk                /*!<Output Compare 1 Fast enable */
6660 #define TIM_CCMR1_OC1PE_Pos                 (3U)
6661 #define TIM_CCMR1_OC1PE_Msk                 (0x1U << TIM_CCMR1_OC1PE_Pos)      /*!< 0x00000008 */
6662 #define TIM_CCMR1_OC1PE                     TIM_CCMR1_OC1PE_Msk                /*!<Output Compare 1 Preload enable */
6663 
6664 #define TIM_CCMR1_OC1M_Pos                  (4U)
6665 #define TIM_CCMR1_OC1M_Msk                  (0x7U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000070 */
6666 #define TIM_CCMR1_OC1M                      TIM_CCMR1_OC1M_Msk                 /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
6667 #define TIM_CCMR1_OC1M_0                    (0x1U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000010 */
6668 #define TIM_CCMR1_OC1M_1                    (0x2U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000020 */
6669 #define TIM_CCMR1_OC1M_2                    (0x4U << TIM_CCMR1_OC1M_Pos)       /*!< 0x00000040 */
6670 
6671 #define TIM_CCMR1_OC1CE_Pos                 (7U)
6672 #define TIM_CCMR1_OC1CE_Msk                 (0x1U << TIM_CCMR1_OC1CE_Pos)      /*!< 0x00000080 */
6673 #define TIM_CCMR1_OC1CE                     TIM_CCMR1_OC1CE_Msk                /*!<Output Compare 1Clear Enable */
6674 
6675 #define TIM_CCMR1_CC2S_Pos                  (8U)
6676 #define TIM_CCMR1_CC2S_Msk                  (0x3U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000300 */
6677 #define TIM_CCMR1_CC2S                      TIM_CCMR1_CC2S_Msk                 /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
6678 #define TIM_CCMR1_CC2S_0                    (0x1U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000100 */
6679 #define TIM_CCMR1_CC2S_1                    (0x2U << TIM_CCMR1_CC2S_Pos)       /*!< 0x00000200 */
6680 
6681 #define TIM_CCMR1_OC2FE_Pos                 (10U)
6682 #define TIM_CCMR1_OC2FE_Msk                 (0x1U << TIM_CCMR1_OC2FE_Pos)      /*!< 0x00000400 */
6683 #define TIM_CCMR1_OC2FE                     TIM_CCMR1_OC2FE_Msk                /*!<Output Compare 2 Fast enable */
6684 #define TIM_CCMR1_OC2PE_Pos                 (11U)
6685 #define TIM_CCMR1_OC2PE_Msk                 (0x1U << TIM_CCMR1_OC2PE_Pos)      /*!< 0x00000800 */
6686 #define TIM_CCMR1_OC2PE                     TIM_CCMR1_OC2PE_Msk                /*!<Output Compare 2 Preload enable */
6687 
6688 #define TIM_CCMR1_OC2M_Pos                  (12U)
6689 #define TIM_CCMR1_OC2M_Msk                  (0x7U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00007000 */
6690 #define TIM_CCMR1_OC2M                      TIM_CCMR1_OC2M_Msk                 /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
6691 #define TIM_CCMR1_OC2M_0                    (0x1U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00001000 */
6692 #define TIM_CCMR1_OC2M_1                    (0x2U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00002000 */
6693 #define TIM_CCMR1_OC2M_2                    (0x4U << TIM_CCMR1_OC2M_Pos)       /*!< 0x00004000 */
6694 
6695 #define TIM_CCMR1_OC2CE_Pos                 (15U)
6696 #define TIM_CCMR1_OC2CE_Msk                 (0x1U << TIM_CCMR1_OC2CE_Pos)      /*!< 0x00008000 */
6697 #define TIM_CCMR1_OC2CE                     TIM_CCMR1_OC2CE_Msk                /*!<Output Compare 2 Clear Enable */
6698 
6699 /*----------------------------------------------------------------------------*/
6700 
6701 #define TIM_CCMR1_IC1PSC_Pos                (2U)
6702 #define TIM_CCMR1_IC1PSC_Msk                (0x3U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x0000000C */
6703 #define TIM_CCMR1_IC1PSC                    TIM_CCMR1_IC1PSC_Msk               /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
6704 #define TIM_CCMR1_IC1PSC_0                  (0x1U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000004 */
6705 #define TIM_CCMR1_IC1PSC_1                  (0x2U << TIM_CCMR1_IC1PSC_Pos)     /*!< 0x00000008 */
6706 
6707 #define TIM_CCMR1_IC1F_Pos                  (4U)
6708 #define TIM_CCMR1_IC1F_Msk                  (0xFU << TIM_CCMR1_IC1F_Pos)       /*!< 0x000000F0 */
6709 #define TIM_CCMR1_IC1F                      TIM_CCMR1_IC1F_Msk                 /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
6710 #define TIM_CCMR1_IC1F_0                    (0x1U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000010 */
6711 #define TIM_CCMR1_IC1F_1                    (0x2U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000020 */
6712 #define TIM_CCMR1_IC1F_2                    (0x4U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000040 */
6713 #define TIM_CCMR1_IC1F_3                    (0x8U << TIM_CCMR1_IC1F_Pos)       /*!< 0x00000080 */
6714 
6715 #define TIM_CCMR1_IC2PSC_Pos                (10U)
6716 #define TIM_CCMR1_IC2PSC_Msk                (0x3U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000C00 */
6717 #define TIM_CCMR1_IC2PSC                    TIM_CCMR1_IC2PSC_Msk               /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
6718 #define TIM_CCMR1_IC2PSC_0                  (0x1U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000400 */
6719 #define TIM_CCMR1_IC2PSC_1                  (0x2U << TIM_CCMR1_IC2PSC_Pos)     /*!< 0x00000800 */
6720 
6721 #define TIM_CCMR1_IC2F_Pos                  (12U)
6722 #define TIM_CCMR1_IC2F_Msk                  (0xFU << TIM_CCMR1_IC2F_Pos)       /*!< 0x0000F000 */
6723 #define TIM_CCMR1_IC2F                      TIM_CCMR1_IC2F_Msk                 /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
6724 #define TIM_CCMR1_IC2F_0                    (0x1U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00001000 */
6725 #define TIM_CCMR1_IC2F_1                    (0x2U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00002000 */
6726 #define TIM_CCMR1_IC2F_2                    (0x4U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00004000 */
6727 #define TIM_CCMR1_IC2F_3                    (0x8U << TIM_CCMR1_IC2F_Pos)       /*!< 0x00008000 */
6728 
6729 /******************  Bit definition for TIM_CCMR2 register  *******************/
6730 #define TIM_CCMR2_CC3S_Pos                  (0U)
6731 #define TIM_CCMR2_CC3S_Msk                  (0x3U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000003 */
6732 #define TIM_CCMR2_CC3S                      TIM_CCMR2_CC3S_Msk                 /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
6733 #define TIM_CCMR2_CC3S_0                    (0x1U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000001 */
6734 #define TIM_CCMR2_CC3S_1                    (0x2U << TIM_CCMR2_CC3S_Pos)       /*!< 0x00000002 */
6735 
6736 #define TIM_CCMR2_OC3FE_Pos                 (2U)
6737 #define TIM_CCMR2_OC3FE_Msk                 (0x1U << TIM_CCMR2_OC3FE_Pos)      /*!< 0x00000004 */
6738 #define TIM_CCMR2_OC3FE                     TIM_CCMR2_OC3FE_Msk                /*!<Output Compare 3 Fast enable */
6739 #define TIM_CCMR2_OC3PE_Pos                 (3U)
6740 #define TIM_CCMR2_OC3PE_Msk                 (0x1U << TIM_CCMR2_OC3PE_Pos)      /*!< 0x00000008 */
6741 #define TIM_CCMR2_OC3PE                     TIM_CCMR2_OC3PE_Msk                /*!<Output Compare 3 Preload enable */
6742 
6743 #define TIM_CCMR2_OC3M_Pos                  (4U)
6744 #define TIM_CCMR2_OC3M_Msk                  (0x7U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000070 */
6745 #define TIM_CCMR2_OC3M                      TIM_CCMR2_OC3M_Msk                 /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
6746 #define TIM_CCMR2_OC3M_0                    (0x1U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000010 */
6747 #define TIM_CCMR2_OC3M_1                    (0x2U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000020 */
6748 #define TIM_CCMR2_OC3M_2                    (0x4U << TIM_CCMR2_OC3M_Pos)       /*!< 0x00000040 */
6749 
6750 #define TIM_CCMR2_OC3CE_Pos                 (7U)
6751 #define TIM_CCMR2_OC3CE_Msk                 (0x1U << TIM_CCMR2_OC3CE_Pos)      /*!< 0x00000080 */
6752 #define TIM_CCMR2_OC3CE                     TIM_CCMR2_OC3CE_Msk                /*!<Output Compare 3 Clear Enable */
6753 
6754 #define TIM_CCMR2_CC4S_Pos                  (8U)
6755 #define TIM_CCMR2_CC4S_Msk                  (0x3U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000300 */
6756 #define TIM_CCMR2_CC4S                      TIM_CCMR2_CC4S_Msk                 /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
6757 #define TIM_CCMR2_CC4S_0                    (0x1U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000100 */
6758 #define TIM_CCMR2_CC4S_1                    (0x2U << TIM_CCMR2_CC4S_Pos)       /*!< 0x00000200 */
6759 
6760 #define TIM_CCMR2_OC4FE_Pos                 (10U)
6761 #define TIM_CCMR2_OC4FE_Msk                 (0x1U << TIM_CCMR2_OC4FE_Pos)      /*!< 0x00000400 */
6762 #define TIM_CCMR2_OC4FE                     TIM_CCMR2_OC4FE_Msk                /*!<Output Compare 4 Fast enable */
6763 #define TIM_CCMR2_OC4PE_Pos                 (11U)
6764 #define TIM_CCMR2_OC4PE_Msk                 (0x1U << TIM_CCMR2_OC4PE_Pos)      /*!< 0x00000800 */
6765 #define TIM_CCMR2_OC4PE                     TIM_CCMR2_OC4PE_Msk                /*!<Output Compare 4 Preload enable */
6766 
6767 #define TIM_CCMR2_OC4M_Pos                  (12U)
6768 #define TIM_CCMR2_OC4M_Msk                  (0x7U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00007000 */
6769 #define TIM_CCMR2_OC4M                      TIM_CCMR2_OC4M_Msk                 /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
6770 #define TIM_CCMR2_OC4M_0                    (0x1U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00001000 */
6771 #define TIM_CCMR2_OC4M_1                    (0x2U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00002000 */
6772 #define TIM_CCMR2_OC4M_2                    (0x4U << TIM_CCMR2_OC4M_Pos)       /*!< 0x00004000 */
6773 
6774 #define TIM_CCMR2_OC4CE_Pos                 (15U)
6775 #define TIM_CCMR2_OC4CE_Msk                 (0x1U << TIM_CCMR2_OC4CE_Pos)      /*!< 0x00008000 */
6776 #define TIM_CCMR2_OC4CE                     TIM_CCMR2_OC4CE_Msk                /*!<Output Compare 4 Clear Enable */
6777 
6778 /*----------------------------------------------------------------------------*/
6779 
6780 #define TIM_CCMR2_IC3PSC_Pos                (2U)
6781 #define TIM_CCMR2_IC3PSC_Msk                (0x3U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x0000000C */
6782 #define TIM_CCMR2_IC3PSC                    TIM_CCMR2_IC3PSC_Msk               /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
6783 #define TIM_CCMR2_IC3PSC_0                  (0x1U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000004 */
6784 #define TIM_CCMR2_IC3PSC_1                  (0x2U << TIM_CCMR2_IC3PSC_Pos)     /*!< 0x00000008 */
6785 
6786 #define TIM_CCMR2_IC3F_Pos                  (4U)
6787 #define TIM_CCMR2_IC3F_Msk                  (0xFU << TIM_CCMR2_IC3F_Pos)       /*!< 0x000000F0 */
6788 #define TIM_CCMR2_IC3F                      TIM_CCMR2_IC3F_Msk                 /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
6789 #define TIM_CCMR2_IC3F_0                    (0x1U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000010 */
6790 #define TIM_CCMR2_IC3F_1                    (0x2U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000020 */
6791 #define TIM_CCMR2_IC3F_2                    (0x4U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000040 */
6792 #define TIM_CCMR2_IC3F_3                    (0x8U << TIM_CCMR2_IC3F_Pos)       /*!< 0x00000080 */
6793 
6794 #define TIM_CCMR2_IC4PSC_Pos                (10U)
6795 #define TIM_CCMR2_IC4PSC_Msk                (0x3U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000C00 */
6796 #define TIM_CCMR2_IC4PSC                    TIM_CCMR2_IC4PSC_Msk               /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
6797 #define TIM_CCMR2_IC4PSC_0                  (0x1U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000400 */
6798 #define TIM_CCMR2_IC4PSC_1                  (0x2U << TIM_CCMR2_IC4PSC_Pos)     /*!< 0x00000800 */
6799 
6800 #define TIM_CCMR2_IC4F_Pos                  (12U)
6801 #define TIM_CCMR2_IC4F_Msk                  (0xFU << TIM_CCMR2_IC4F_Pos)       /*!< 0x0000F000 */
6802 #define TIM_CCMR2_IC4F                      TIM_CCMR2_IC4F_Msk                 /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
6803 #define TIM_CCMR2_IC4F_0                    (0x1U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00001000 */
6804 #define TIM_CCMR2_IC4F_1                    (0x2U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00002000 */
6805 #define TIM_CCMR2_IC4F_2                    (0x4U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00004000 */
6806 #define TIM_CCMR2_IC4F_3                    (0x8U << TIM_CCMR2_IC4F_Pos)       /*!< 0x00008000 */
6807 
6808 /*******************  Bit definition for TIM_CCER register  *******************/
6809 #define TIM_CCER_CC1E_Pos                   (0U)
6810 #define TIM_CCER_CC1E_Msk                   (0x1U << TIM_CCER_CC1E_Pos)        /*!< 0x00000001 */
6811 #define TIM_CCER_CC1E                       TIM_CCER_CC1E_Msk                  /*!<Capture/Compare 1 output enable */
6812 #define TIM_CCER_CC1P_Pos                   (1U)
6813 #define TIM_CCER_CC1P_Msk                   (0x1U << TIM_CCER_CC1P_Pos)        /*!< 0x00000002 */
6814 #define TIM_CCER_CC1P                       TIM_CCER_CC1P_Msk                  /*!<Capture/Compare 1 output Polarity */
6815 #define TIM_CCER_CC1NP_Pos                  (3U)
6816 #define TIM_CCER_CC1NP_Msk                  (0x1U << TIM_CCER_CC1NP_Pos)       /*!< 0x00000008 */
6817 #define TIM_CCER_CC1NP                      TIM_CCER_CC1NP_Msk                 /*!<Capture/Compare 1 Complementary output Polarity */
6818 #define TIM_CCER_CC2E_Pos                   (4U)
6819 #define TIM_CCER_CC2E_Msk                   (0x1U << TIM_CCER_CC2E_Pos)        /*!< 0x00000010 */
6820 #define TIM_CCER_CC2E                       TIM_CCER_CC2E_Msk                  /*!<Capture/Compare 2 output enable */
6821 #define TIM_CCER_CC2P_Pos                   (5U)
6822 #define TIM_CCER_CC2P_Msk                   (0x1U << TIM_CCER_CC2P_Pos)        /*!< 0x00000020 */
6823 #define TIM_CCER_CC2P                       TIM_CCER_CC2P_Msk                  /*!<Capture/Compare 2 output Polarity */
6824 #define TIM_CCER_CC2NP_Pos                  (7U)
6825 #define TIM_CCER_CC2NP_Msk                  (0x1U << TIM_CCER_CC2NP_Pos)       /*!< 0x00000080 */
6826 #define TIM_CCER_CC2NP                      TIM_CCER_CC2NP_Msk                 /*!<Capture/Compare 2 Complementary output Polarity */
6827 #define TIM_CCER_CC3E_Pos                   (8U)
6828 #define TIM_CCER_CC3E_Msk                   (0x1U << TIM_CCER_CC3E_Pos)        /*!< 0x00000100 */
6829 #define TIM_CCER_CC3E                       TIM_CCER_CC3E_Msk                  /*!<Capture/Compare 3 output enable */
6830 #define TIM_CCER_CC3P_Pos                   (9U)
6831 #define TIM_CCER_CC3P_Msk                   (0x1U << TIM_CCER_CC3P_Pos)        /*!< 0x00000200 */
6832 #define TIM_CCER_CC3P                       TIM_CCER_CC3P_Msk                  /*!<Capture/Compare 3 output Polarity */
6833 #define TIM_CCER_CC3NP_Pos                  (11U)
6834 #define TIM_CCER_CC3NP_Msk                  (0x1U << TIM_CCER_CC3NP_Pos)       /*!< 0x00000800 */
6835 #define TIM_CCER_CC3NP                      TIM_CCER_CC3NP_Msk                 /*!<Capture/Compare 3 Complementary output Polarity */
6836 #define TIM_CCER_CC4E_Pos                   (12U)
6837 #define TIM_CCER_CC4E_Msk                   (0x1U << TIM_CCER_CC4E_Pos)        /*!< 0x00001000 */
6838 #define TIM_CCER_CC4E                       TIM_CCER_CC4E_Msk                  /*!<Capture/Compare 4 output enable */
6839 #define TIM_CCER_CC4P_Pos                   (13U)
6840 #define TIM_CCER_CC4P_Msk                   (0x1U << TIM_CCER_CC4P_Pos)        /*!< 0x00002000 */
6841 #define TIM_CCER_CC4P                       TIM_CCER_CC4P_Msk                  /*!<Capture/Compare 4 output Polarity */
6842 #define TIM_CCER_CC4NP_Pos                  (15U)
6843 #define TIM_CCER_CC4NP_Msk                  (0x1U << TIM_CCER_CC4NP_Pos)       /*!< 0x00008000 */
6844 #define TIM_CCER_CC4NP                      TIM_CCER_CC4NP_Msk                 /*!<Capture/Compare 4 Complementary output Polarity */
6845 
6846 /*******************  Bit definition for TIM_CNT register  ********************/
6847 #define TIM_CNT_CNT_Pos                     (0U)
6848 #define TIM_CNT_CNT_Msk                     (0xFFFFFFFFU << TIM_CNT_CNT_Pos)   /*!< 0xFFFFFFFF */
6849 #define TIM_CNT_CNT                         TIM_CNT_CNT_Msk                    /*!<Counter Value */
6850 
6851 /*******************  Bit definition for TIM_PSC register  ********************/
6852 #define TIM_PSC_PSC_Pos                     (0U)
6853 #define TIM_PSC_PSC_Msk                     (0xFFFFU << TIM_PSC_PSC_Pos)       /*!< 0x0000FFFF */
6854 #define TIM_PSC_PSC                         TIM_PSC_PSC_Msk                    /*!<Prescaler Value */
6855 
6856 /*******************  Bit definition for TIM_ARR register  ********************/
6857 #define TIM_ARR_ARR_Pos                     (0U)
6858 #define TIM_ARR_ARR_Msk                     (0xFFFFFFFFU << TIM_ARR_ARR_Pos)   /*!< 0xFFFFFFFF */
6859 #define TIM_ARR_ARR                         TIM_ARR_ARR_Msk                    /*!<actual auto-reload Value */
6860 
6861 /*******************  Bit definition for TIM_CCR1 register  *******************/
6862 #define TIM_CCR1_CCR1_Pos                   (0U)
6863 #define TIM_CCR1_CCR1_Msk                   (0xFFFFU << TIM_CCR1_CCR1_Pos)     /*!< 0x0000FFFF */
6864 #define TIM_CCR1_CCR1                       TIM_CCR1_CCR1_Msk                  /*!<Capture/Compare 1 Value */
6865 
6866 /*******************  Bit definition for TIM_CCR2 register  *******************/
6867 #define TIM_CCR2_CCR2_Pos                   (0U)
6868 #define TIM_CCR2_CCR2_Msk                   (0xFFFFU << TIM_CCR2_CCR2_Pos)     /*!< 0x0000FFFF */
6869 #define TIM_CCR2_CCR2                       TIM_CCR2_CCR2_Msk                  /*!<Capture/Compare 2 Value */
6870 
6871 /*******************  Bit definition for TIM_CCR3 register  *******************/
6872 #define TIM_CCR3_CCR3_Pos                   (0U)
6873 #define TIM_CCR3_CCR3_Msk                   (0xFFFFU << TIM_CCR3_CCR3_Pos)     /*!< 0x0000FFFF */
6874 #define TIM_CCR3_CCR3                       TIM_CCR3_CCR3_Msk                  /*!<Capture/Compare 3 Value */
6875 
6876 /*******************  Bit definition for TIM_CCR4 register  *******************/
6877 #define TIM_CCR4_CCR4_Pos                   (0U)
6878 #define TIM_CCR4_CCR4_Msk                   (0xFFFFU << TIM_CCR4_CCR4_Pos)     /*!< 0x0000FFFF */
6879 #define TIM_CCR4_CCR4                       TIM_CCR4_CCR4_Msk                  /*!<Capture/Compare 4 Value */
6880 
6881 /*******************  Bit definition for TIM_DCR register  ********************/
6882 #define TIM_DCR_DBA_Pos                     (0U)
6883 #define TIM_DCR_DBA_Msk                     (0x1FU << TIM_DCR_DBA_Pos)         /*!< 0x0000001F */
6884 #define TIM_DCR_DBA                         TIM_DCR_DBA_Msk                    /*!<DBA[4:0] bits (DMA Base Address) */
6885 #define TIM_DCR_DBA_0                       (0x01U << TIM_DCR_DBA_Pos)         /*!< 0x00000001 */
6886 #define TIM_DCR_DBA_1                       (0x02U << TIM_DCR_DBA_Pos)         /*!< 0x00000002 */
6887 #define TIM_DCR_DBA_2                       (0x04U << TIM_DCR_DBA_Pos)         /*!< 0x00000004 */
6888 #define TIM_DCR_DBA_3                       (0x08U << TIM_DCR_DBA_Pos)         /*!< 0x00000008 */
6889 #define TIM_DCR_DBA_4                       (0x10U << TIM_DCR_DBA_Pos)         /*!< 0x00000010 */
6890 
6891 #define TIM_DCR_DBL_Pos                     (8U)
6892 #define TIM_DCR_DBL_Msk                     (0x1FU << TIM_DCR_DBL_Pos)         /*!< 0x00001F00 */
6893 #define TIM_DCR_DBL                         TIM_DCR_DBL_Msk                    /*!<DBL[4:0] bits (DMA Burst Length) */
6894 #define TIM_DCR_DBL_0                       (0x01U << TIM_DCR_DBL_Pos)         /*!< 0x00000100 */
6895 #define TIM_DCR_DBL_1                       (0x02U << TIM_DCR_DBL_Pos)         /*!< 0x00000200 */
6896 #define TIM_DCR_DBL_2                       (0x04U << TIM_DCR_DBL_Pos)         /*!< 0x00000400 */
6897 #define TIM_DCR_DBL_3                       (0x08U << TIM_DCR_DBL_Pos)         /*!< 0x00000800 */
6898 #define TIM_DCR_DBL_4                       (0x10U << TIM_DCR_DBL_Pos)         /*!< 0x00001000 */
6899 
6900 /*******************  Bit definition for TIM_DMAR register  *******************/
6901 #define TIM_DMAR_DMAB_Pos                   (0U)
6902 #define TIM_DMAR_DMAB_Msk                   (0xFFFFU << TIM_DMAR_DMAB_Pos)     /*!< 0x0000FFFF */
6903 #define TIM_DMAR_DMAB                       TIM_DMAR_DMAB_Msk                  /*!<DMA register for burst accesses */
6904 
6905 /*******************  Bit definition for TIM_OR register  *********************/
6906 #define TIM_OR_TI1RMP_Pos                   (0U)
6907 #define TIM_OR_TI1RMP_Msk                   (0x3U << TIM_OR_TI1RMP_Pos)        /*!< 0x00000003 */
6908 #define TIM_OR_TI1RMP                       TIM_OR_TI1RMP_Msk                  /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
6909 #define TIM_OR_TI1RMP_0                     (0x1U << TIM_OR_TI1RMP_Pos)        /*!< 0x00000001 */
6910 #define TIM_OR_TI1RMP_1                     (0x2U << TIM_OR_TI1RMP_Pos)        /*!< 0x00000002 */
6911 
6912 #define TIM_OR_ETR_RMP_Pos                  (2U)
6913 #define TIM_OR_ETR_RMP_Msk                  (0x1U << TIM_OR_ETR_RMP_Pos)       /*!< 0x00000004 */
6914 #define TIM_OR_ETR_RMP                      TIM_OR_ETR_RMP_Msk                 /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
6915 #define TIM_OR_TI1_RMP_RI_Pos               (3U)
6916 #define TIM_OR_TI1_RMP_RI_Msk               (0x1U << TIM_OR_TI1_RMP_RI_Pos)    /*!< 0x00000008 */
6917 #define TIM_OR_TI1_RMP_RI                   TIM_OR_TI1_RMP_RI_Msk              /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
6918 
6919 /*----------------------------------------------------------------------------*/
6920 #define TIM9_OR_ITR1_RMP_Pos                (2U)
6921 #define TIM9_OR_ITR1_RMP_Msk                (0x1U << TIM9_OR_ITR1_RMP_Pos)     /*!< 0x00000004 */
6922 #define TIM9_OR_ITR1_RMP                    TIM9_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
6923 
6924 /*----------------------------------------------------------------------------*/
6925 #define TIM2_OR_ITR1_RMP_Pos                (0U)
6926 #define TIM2_OR_ITR1_RMP_Msk                (0x1U << TIM2_OR_ITR1_RMP_Pos)     /*!< 0x00000001 */
6927 #define TIM2_OR_ITR1_RMP                    TIM2_OR_ITR1_RMP_Msk               /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
6928 
6929 /*----------------------------------------------------------------------------*/
6930 #define TIM3_OR_ITR2_RMP_Pos                (0U)
6931 #define TIM3_OR_ITR2_RMP_Msk                (0x1U << TIM3_OR_ITR2_RMP_Pos)     /*!< 0x00000001 */
6932 #define TIM3_OR_ITR2_RMP                    TIM3_OR_ITR2_RMP_Msk               /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
6933 
6934 /*----------------------------------------------------------------------------*/
6935 
6936 /******************************************************************************/
6937 /*                                                                            */
6938 /*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
6939 /*                                                                            */
6940 /******************************************************************************/
6941 
6942 /*******************  Bit definition for USART_SR register  *******************/
6943 #define USART_SR_PE_Pos                     (0U)
6944 #define USART_SR_PE_Msk                     (0x1U << USART_SR_PE_Pos)          /*!< 0x00000001 */
6945 #define USART_SR_PE                         USART_SR_PE_Msk                    /*!< Parity Error */
6946 #define USART_SR_FE_Pos                     (1U)
6947 #define USART_SR_FE_Msk                     (0x1U << USART_SR_FE_Pos)          /*!< 0x00000002 */
6948 #define USART_SR_FE                         USART_SR_FE_Msk                    /*!< Framing Error */
6949 #define USART_SR_NE_Pos                     (2U)
6950 #define USART_SR_NE_Msk                     (0x1U << USART_SR_NE_Pos)          /*!< 0x00000004 */
6951 #define USART_SR_NE                         USART_SR_NE_Msk                    /*!< Noise Error Flag */
6952 #define USART_SR_ORE_Pos                    (3U)
6953 #define USART_SR_ORE_Msk                    (0x1U << USART_SR_ORE_Pos)         /*!< 0x00000008 */
6954 #define USART_SR_ORE                        USART_SR_ORE_Msk                   /*!< OverRun Error */
6955 #define USART_SR_IDLE_Pos                   (4U)
6956 #define USART_SR_IDLE_Msk                   (0x1U << USART_SR_IDLE_Pos)        /*!< 0x00000010 */
6957 #define USART_SR_IDLE                       USART_SR_IDLE_Msk                  /*!< IDLE line detected */
6958 #define USART_SR_RXNE_Pos                   (5U)
6959 #define USART_SR_RXNE_Msk                   (0x1U << USART_SR_RXNE_Pos)        /*!< 0x00000020 */
6960 #define USART_SR_RXNE                       USART_SR_RXNE_Msk                  /*!< Read Data Register Not Empty */
6961 #define USART_SR_TC_Pos                     (6U)
6962 #define USART_SR_TC_Msk                     (0x1U << USART_SR_TC_Pos)          /*!< 0x00000040 */
6963 #define USART_SR_TC                         USART_SR_TC_Msk                    /*!< Transmission Complete */
6964 #define USART_SR_TXE_Pos                    (7U)
6965 #define USART_SR_TXE_Msk                    (0x1U << USART_SR_TXE_Pos)         /*!< 0x00000080 */
6966 #define USART_SR_TXE                        USART_SR_TXE_Msk                   /*!< Transmit Data Register Empty */
6967 #define USART_SR_LBD_Pos                    (8U)
6968 #define USART_SR_LBD_Msk                    (0x1U << USART_SR_LBD_Pos)         /*!< 0x00000100 */
6969 #define USART_SR_LBD                        USART_SR_LBD_Msk                   /*!< LIN Break Detection Flag */
6970 #define USART_SR_CTS_Pos                    (9U)
6971 #define USART_SR_CTS_Msk                    (0x1U << USART_SR_CTS_Pos)         /*!< 0x00000200 */
6972 #define USART_SR_CTS                        USART_SR_CTS_Msk                   /*!< CTS Flag */
6973 
6974 /*******************  Bit definition for USART_DR register  *******************/
6975 #define USART_DR_DR_Pos                     (0U)
6976 #define USART_DR_DR_Msk                     (0x1FFU << USART_DR_DR_Pos)        /*!< 0x000001FF */
6977 #define USART_DR_DR                         USART_DR_DR_Msk                    /*!< Data value */
6978 
6979 /******************  Bit definition for USART_BRR register  *******************/
6980 #define USART_BRR_DIV_FRACTION_Pos          (0U)
6981 #define USART_BRR_DIV_FRACTION_Msk          (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
6982 #define USART_BRR_DIV_FRACTION              USART_BRR_DIV_FRACTION_Msk         /*!< Fraction of USARTDIV */
6983 #define USART_BRR_DIV_MANTISSA_Pos          (4U)
6984 #define USART_BRR_DIV_MANTISSA_Msk          (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
6985 #define USART_BRR_DIV_MANTISSA              USART_BRR_DIV_MANTISSA_Msk         /*!< Mantissa of USARTDIV */
6986 
6987 /******************  Bit definition for USART_CR1 register  *******************/
6988 #define USART_CR1_SBK_Pos                   (0U)
6989 #define USART_CR1_SBK_Msk                   (0x1U << USART_CR1_SBK_Pos)        /*!< 0x00000001 */
6990 #define USART_CR1_SBK                       USART_CR1_SBK_Msk                  /*!< Send Break */
6991 #define USART_CR1_RWU_Pos                   (1U)
6992 #define USART_CR1_RWU_Msk                   (0x1U << USART_CR1_RWU_Pos)        /*!< 0x00000002 */
6993 #define USART_CR1_RWU                       USART_CR1_RWU_Msk                  /*!< Receiver wakeup */
6994 #define USART_CR1_RE_Pos                    (2U)
6995 #define USART_CR1_RE_Msk                    (0x1U << USART_CR1_RE_Pos)         /*!< 0x00000004 */
6996 #define USART_CR1_RE                        USART_CR1_RE_Msk                   /*!< Receiver Enable */
6997 #define USART_CR1_TE_Pos                    (3U)
6998 #define USART_CR1_TE_Msk                    (0x1U << USART_CR1_TE_Pos)         /*!< 0x00000008 */
6999 #define USART_CR1_TE                        USART_CR1_TE_Msk                   /*!< Transmitter Enable */
7000 #define USART_CR1_IDLEIE_Pos                (4U)
7001 #define USART_CR1_IDLEIE_Msk                (0x1U << USART_CR1_IDLEIE_Pos)     /*!< 0x00000010 */
7002 #define USART_CR1_IDLEIE                    USART_CR1_IDLEIE_Msk               /*!< IDLE Interrupt Enable */
7003 #define USART_CR1_RXNEIE_Pos                (5U)
7004 #define USART_CR1_RXNEIE_Msk                (0x1U << USART_CR1_RXNEIE_Pos)     /*!< 0x00000020 */
7005 #define USART_CR1_RXNEIE                    USART_CR1_RXNEIE_Msk               /*!< RXNE Interrupt Enable */
7006 #define USART_CR1_TCIE_Pos                  (6U)
7007 #define USART_CR1_TCIE_Msk                  (0x1U << USART_CR1_TCIE_Pos)       /*!< 0x00000040 */
7008 #define USART_CR1_TCIE                      USART_CR1_TCIE_Msk                 /*!< Transmission Complete Interrupt Enable */
7009 #define USART_CR1_TXEIE_Pos                 (7U)
7010 #define USART_CR1_TXEIE_Msk                 (0x1U << USART_CR1_TXEIE_Pos)      /*!< 0x00000080 */
7011 #define USART_CR1_TXEIE                     USART_CR1_TXEIE_Msk                /*!< PE Interrupt Enable */
7012 #define USART_CR1_PEIE_Pos                  (8U)
7013 #define USART_CR1_PEIE_Msk                  (0x1U << USART_CR1_PEIE_Pos)       /*!< 0x00000100 */
7014 #define USART_CR1_PEIE                      USART_CR1_PEIE_Msk                 /*!< PE Interrupt Enable */
7015 #define USART_CR1_PS_Pos                    (9U)
7016 #define USART_CR1_PS_Msk                    (0x1U << USART_CR1_PS_Pos)         /*!< 0x00000200 */
7017 #define USART_CR1_PS                        USART_CR1_PS_Msk                   /*!< Parity Selection */
7018 #define USART_CR1_PCE_Pos                   (10U)
7019 #define USART_CR1_PCE_Msk                   (0x1U << USART_CR1_PCE_Pos)        /*!< 0x00000400 */
7020 #define USART_CR1_PCE                       USART_CR1_PCE_Msk                  /*!< Parity Control Enable */
7021 #define USART_CR1_WAKE_Pos                  (11U)
7022 #define USART_CR1_WAKE_Msk                  (0x1U << USART_CR1_WAKE_Pos)       /*!< 0x00000800 */
7023 #define USART_CR1_WAKE                      USART_CR1_WAKE_Msk                 /*!< Wakeup method */
7024 #define USART_CR1_M_Pos                     (12U)
7025 #define USART_CR1_M_Msk                     (0x1U << USART_CR1_M_Pos)          /*!< 0x00001000 */
7026 #define USART_CR1_M                         USART_CR1_M_Msk                    /*!< Word length */
7027 #define USART_CR1_UE_Pos                    (13U)
7028 #define USART_CR1_UE_Msk                    (0x1U << USART_CR1_UE_Pos)         /*!< 0x00002000 */
7029 #define USART_CR1_UE                        USART_CR1_UE_Msk                   /*!< USART Enable */
7030 #define USART_CR1_OVER8_Pos                 (15U)
7031 #define USART_CR1_OVER8_Msk                 (0x1U << USART_CR1_OVER8_Pos)      /*!< 0x00008000 */
7032 #define USART_CR1_OVER8                     USART_CR1_OVER8_Msk                /*!< Oversampling by 8-bit mode */
7033 
7034 /******************  Bit definition for USART_CR2 register  *******************/
7035 #define USART_CR2_ADD_Pos                   (0U)
7036 #define USART_CR2_ADD_Msk                   (0xFU << USART_CR2_ADD_Pos)        /*!< 0x0000000F */
7037 #define USART_CR2_ADD                       USART_CR2_ADD_Msk                  /*!< Address of the USART node */
7038 #define USART_CR2_LBDL_Pos                  (5U)
7039 #define USART_CR2_LBDL_Msk                  (0x1U << USART_CR2_LBDL_Pos)       /*!< 0x00000020 */
7040 #define USART_CR2_LBDL                      USART_CR2_LBDL_Msk                 /*!< LIN Break Detection Length */
7041 #define USART_CR2_LBDIE_Pos                 (6U)
7042 #define USART_CR2_LBDIE_Msk                 (0x1U << USART_CR2_LBDIE_Pos)      /*!< 0x00000040 */
7043 #define USART_CR2_LBDIE                     USART_CR2_LBDIE_Msk                /*!< LIN Break Detection Interrupt Enable */
7044 #define USART_CR2_LBCL_Pos                  (8U)
7045 #define USART_CR2_LBCL_Msk                  (0x1U << USART_CR2_LBCL_Pos)       /*!< 0x00000100 */
7046 #define USART_CR2_LBCL                      USART_CR2_LBCL_Msk                 /*!< Last Bit Clock pulse */
7047 #define USART_CR2_CPHA_Pos                  (9U)
7048 #define USART_CR2_CPHA_Msk                  (0x1U << USART_CR2_CPHA_Pos)       /*!< 0x00000200 */
7049 #define USART_CR2_CPHA                      USART_CR2_CPHA_Msk                 /*!< Clock Phase */
7050 #define USART_CR2_CPOL_Pos                  (10U)
7051 #define USART_CR2_CPOL_Msk                  (0x1U << USART_CR2_CPOL_Pos)       /*!< 0x00000400 */
7052 #define USART_CR2_CPOL                      USART_CR2_CPOL_Msk                 /*!< Clock Polarity */
7053 #define USART_CR2_CLKEN_Pos                 (11U)
7054 #define USART_CR2_CLKEN_Msk                 (0x1U << USART_CR2_CLKEN_Pos)      /*!< 0x00000800 */
7055 #define USART_CR2_CLKEN                     USART_CR2_CLKEN_Msk                /*!< Clock Enable */
7056 
7057 #define USART_CR2_STOP_Pos                  (12U)
7058 #define USART_CR2_STOP_Msk                  (0x3U << USART_CR2_STOP_Pos)       /*!< 0x00003000 */
7059 #define USART_CR2_STOP                      USART_CR2_STOP_Msk                 /*!< STOP[1:0] bits (STOP bits) */
7060 #define USART_CR2_STOP_0                    (0x1U << USART_CR2_STOP_Pos)       /*!< 0x00001000 */
7061 #define USART_CR2_STOP_1                    (0x2U << USART_CR2_STOP_Pos)       /*!< 0x00002000 */
7062 
7063 #define USART_CR2_LINEN_Pos                 (14U)
7064 #define USART_CR2_LINEN_Msk                 (0x1U << USART_CR2_LINEN_Pos)      /*!< 0x00004000 */
7065 #define USART_CR2_LINEN                     USART_CR2_LINEN_Msk                /*!< LIN mode enable */
7066 
7067 /******************  Bit definition for USART_CR3 register  *******************/
7068 #define USART_CR3_EIE_Pos                   (0U)
7069 #define USART_CR3_EIE_Msk                   (0x1U << USART_CR3_EIE_Pos)        /*!< 0x00000001 */
7070 #define USART_CR3_EIE                       USART_CR3_EIE_Msk                  /*!< Error Interrupt Enable */
7071 #define USART_CR3_IREN_Pos                  (1U)
7072 #define USART_CR3_IREN_Msk                  (0x1U << USART_CR3_IREN_Pos)       /*!< 0x00000002 */
7073 #define USART_CR3_IREN                      USART_CR3_IREN_Msk                 /*!< IrDA mode Enable */
7074 #define USART_CR3_IRLP_Pos                  (2U)
7075 #define USART_CR3_IRLP_Msk                  (0x1U << USART_CR3_IRLP_Pos)       /*!< 0x00000004 */
7076 #define USART_CR3_IRLP                      USART_CR3_IRLP_Msk                 /*!< IrDA Low-Power */
7077 #define USART_CR3_HDSEL_Pos                 (3U)
7078 #define USART_CR3_HDSEL_Msk                 (0x1U << USART_CR3_HDSEL_Pos)      /*!< 0x00000008 */
7079 #define USART_CR3_HDSEL                     USART_CR3_HDSEL_Msk                /*!< Half-Duplex Selection */
7080 #define USART_CR3_NACK_Pos                  (4U)
7081 #define USART_CR3_NACK_Msk                  (0x1U << USART_CR3_NACK_Pos)       /*!< 0x00000010 */
7082 #define USART_CR3_NACK                      USART_CR3_NACK_Msk                 /*!< Smartcard NACK enable */
7083 #define USART_CR3_SCEN_Pos                  (5U)
7084 #define USART_CR3_SCEN_Msk                  (0x1U << USART_CR3_SCEN_Pos)       /*!< 0x00000020 */
7085 #define USART_CR3_SCEN                      USART_CR3_SCEN_Msk                 /*!< Smartcard mode enable */
7086 #define USART_CR3_DMAR_Pos                  (6U)
7087 #define USART_CR3_DMAR_Msk                  (0x1U << USART_CR3_DMAR_Pos)       /*!< 0x00000040 */
7088 #define USART_CR3_DMAR                      USART_CR3_DMAR_Msk                 /*!< DMA Enable Receiver */
7089 #define USART_CR3_DMAT_Pos                  (7U)
7090 #define USART_CR3_DMAT_Msk                  (0x1U << USART_CR3_DMAT_Pos)       /*!< 0x00000080 */
7091 #define USART_CR3_DMAT                      USART_CR3_DMAT_Msk                 /*!< DMA Enable Transmitter */
7092 #define USART_CR3_RTSE_Pos                  (8U)
7093 #define USART_CR3_RTSE_Msk                  (0x1U << USART_CR3_RTSE_Pos)       /*!< 0x00000100 */
7094 #define USART_CR3_RTSE                      USART_CR3_RTSE_Msk                 /*!< RTS Enable */
7095 #define USART_CR3_CTSE_Pos                  (9U)
7096 #define USART_CR3_CTSE_Msk                  (0x1U << USART_CR3_CTSE_Pos)       /*!< 0x00000200 */
7097 #define USART_CR3_CTSE                      USART_CR3_CTSE_Msk                 /*!< CTS Enable */
7098 #define USART_CR3_CTSIE_Pos                 (10U)
7099 #define USART_CR3_CTSIE_Msk                 (0x1U << USART_CR3_CTSIE_Pos)      /*!< 0x00000400 */
7100 #define USART_CR3_CTSIE                     USART_CR3_CTSIE_Msk                /*!< CTS Interrupt Enable */
7101 #define USART_CR3_ONEBIT_Pos                (11U)
7102 #define USART_CR3_ONEBIT_Msk                (0x1U << USART_CR3_ONEBIT_Pos)     /*!< 0x00000800 */
7103 #define USART_CR3_ONEBIT                    USART_CR3_ONEBIT_Msk               /*!< One sample bit method enable */
7104 
7105 /******************  Bit definition for USART_GTPR register  ******************/
7106 #define USART_GTPR_PSC_Pos                  (0U)
7107 #define USART_GTPR_PSC_Msk                  (0xFFU << USART_GTPR_PSC_Pos)      /*!< 0x000000FF */
7108 #define USART_GTPR_PSC                      USART_GTPR_PSC_Msk                 /*!< PSC[7:0] bits (Prescaler value) */
7109 #define USART_GTPR_PSC_0                    (0x01U << USART_GTPR_PSC_Pos)      /*!< 0x00000001 */
7110 #define USART_GTPR_PSC_1                    (0x02U << USART_GTPR_PSC_Pos)      /*!< 0x00000002 */
7111 #define USART_GTPR_PSC_2                    (0x04U << USART_GTPR_PSC_Pos)      /*!< 0x00000004 */
7112 #define USART_GTPR_PSC_3                    (0x08U << USART_GTPR_PSC_Pos)      /*!< 0x00000008 */
7113 #define USART_GTPR_PSC_4                    (0x10U << USART_GTPR_PSC_Pos)      /*!< 0x00000010 */
7114 #define USART_GTPR_PSC_5                    (0x20U << USART_GTPR_PSC_Pos)      /*!< 0x00000020 */
7115 #define USART_GTPR_PSC_6                    (0x40U << USART_GTPR_PSC_Pos)      /*!< 0x00000040 */
7116 #define USART_GTPR_PSC_7                    (0x80U << USART_GTPR_PSC_Pos)      /*!< 0x00000080 */
7117 
7118 #define USART_GTPR_GT_Pos                   (8U)
7119 #define USART_GTPR_GT_Msk                   (0xFFU << USART_GTPR_GT_Pos)       /*!< 0x0000FF00 */
7120 #define USART_GTPR_GT                       USART_GTPR_GT_Msk                  /*!< Guard time value */
7121 
7122 /******************************************************************************/
7123 /*                                                                            */
7124 /*                     Universal Serial Bus (USB)                             */
7125 /*                                                                            */
7126 /******************************************************************************/
7127 
7128 /*!<Endpoint-specific registers */
7129 
7130 #define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
7131 #define  USB_EP1R                             (USB_BASE + 0x00000004U)         /*!< endpoint 1 register address */
7132 #define  USB_EP2R                             (USB_BASE + 0x00000008U)         /*!< endpoint 2 register address */
7133 #define  USB_EP3R                             (USB_BASE + 0x0000000CU)         /*!< endpoint 3 register address */
7134 #define  USB_EP4R                             (USB_BASE + 0x00000010U)         /*!< endpoint 4 register address */
7135 #define  USB_EP5R                             (USB_BASE + 0x00000014U)         /*!< endpoint 5 register address */
7136 #define  USB_EP6R                             (USB_BASE + 0x00000018U)         /*!< endpoint 6 register address */
7137 #define  USB_EP7R                             (USB_BASE + 0x0000001CU)         /*!< endpoint 7 register address */
7138 
7139 /* bit positions */
7140 #define USB_EP_CTR_RX_Pos                     (15U)
7141 #define USB_EP_CTR_RX_Msk                     (0x1U << USB_EP_CTR_RX_Pos)      /*!< 0x00008000 */
7142 #define USB_EP_CTR_RX                         USB_EP_CTR_RX_Msk                /*!<  EndPoint Correct TRansfer RX */
7143 #define USB_EP_DTOG_RX_Pos                    (14U)
7144 #define USB_EP_DTOG_RX_Msk                    (0x1U << USB_EP_DTOG_RX_Pos)     /*!< 0x00004000 */
7145 #define USB_EP_DTOG_RX                        USB_EP_DTOG_RX_Msk               /*!<  EndPoint Data TOGGLE RX */
7146 #define USB_EPRX_STAT_Pos                     (12U)
7147 #define USB_EPRX_STAT_Msk                     (0x3U << USB_EPRX_STAT_Pos)      /*!< 0x00003000 */
7148 #define USB_EPRX_STAT                         USB_EPRX_STAT_Msk                /*!<  EndPoint RX STATus bit field */
7149 #define USB_EP_SETUP_Pos                      (11U)
7150 #define USB_EP_SETUP_Msk                      (0x1U << USB_EP_SETUP_Pos)       /*!< 0x00000800 */
7151 #define USB_EP_SETUP                          USB_EP_SETUP_Msk                 /*!<  EndPoint SETUP */
7152 #define USB_EP_T_FIELD_Pos                    (9U)
7153 #define USB_EP_T_FIELD_Msk                    (0x3U << USB_EP_T_FIELD_Pos)     /*!< 0x00000600 */
7154 #define USB_EP_T_FIELD                        USB_EP_T_FIELD_Msk               /*!<  EndPoint TYPE */
7155 #define USB_EP_KIND_Pos                       (8U)
7156 #define USB_EP_KIND_Msk                       (0x1U << USB_EP_KIND_Pos)        /*!< 0x00000100 */
7157 #define USB_EP_KIND                           USB_EP_KIND_Msk                  /*!<  EndPoint KIND */
7158 #define USB_EP_CTR_TX_Pos                     (7U)
7159 #define USB_EP_CTR_TX_Msk                     (0x1U << USB_EP_CTR_TX_Pos)      /*!< 0x00000080 */
7160 #define USB_EP_CTR_TX                         USB_EP_CTR_TX_Msk                /*!<  EndPoint Correct TRansfer TX */
7161 #define USB_EP_DTOG_TX_Pos                    (6U)
7162 #define USB_EP_DTOG_TX_Msk                    (0x1U << USB_EP_DTOG_TX_Pos)     /*!< 0x00000040 */
7163 #define USB_EP_DTOG_TX                        USB_EP_DTOG_TX_Msk               /*!<  EndPoint Data TOGGLE TX */
7164 #define USB_EPTX_STAT_Pos                     (4U)
7165 #define USB_EPTX_STAT_Msk                     (0x3U << USB_EPTX_STAT_Pos)      /*!< 0x00000030 */
7166 #define USB_EPTX_STAT                         USB_EPTX_STAT_Msk                /*!<  EndPoint TX STATus bit field */
7167 #define USB_EPADDR_FIELD_Pos                  (0U)
7168 #define USB_EPADDR_FIELD_Msk                  (0xFU << USB_EPADDR_FIELD_Pos)   /*!< 0x0000000F */
7169 #define USB_EPADDR_FIELD                      USB_EPADDR_FIELD_Msk             /*!<  EndPoint ADDRess FIELD */
7170 
7171 /* EndPoint REGister MASK (no toggle fields) */
7172 #define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
7173                                                                                /*!< EP_TYPE[1:0] EndPoint TYPE */
7174 #define USB_EP_TYPE_MASK_Pos                  (9U)
7175 #define USB_EP_TYPE_MASK_Msk                  (0x3U << USB_EP_TYPE_MASK_Pos)   /*!< 0x00000600 */
7176 #define USB_EP_TYPE_MASK                      USB_EP_TYPE_MASK_Msk             /*!< EndPoint TYPE Mask */
7177 #define USB_EP_BULK                           (0x00000000U)                    /*!< EndPoint BULK */
7178 #define USB_EP_CONTROL                        (0x00000200U)                    /*!< EndPoint CONTROL */
7179 #define USB_EP_ISOCHRONOUS                    (0x00000400U)                    /*!< EndPoint ISOCHRONOUS */
7180 #define USB_EP_INTERRUPT                      (0x00000600U)                    /*!< EndPoint INTERRUPT */
7181 #define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
7182 
7183 #define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
7184                                                                                /*!< STAT_TX[1:0] STATus for TX transfer */
7185 #define USB_EP_TX_DIS                         (0x00000000U)                    /*!< EndPoint TX DISabled */
7186 #define USB_EP_TX_STALL                       (0x00000010U)                    /*!< EndPoint TX STALLed */
7187 #define USB_EP_TX_NAK                         (0x00000020U)                    /*!< EndPoint TX NAKed */
7188 #define USB_EP_TX_VALID                       (0x00000030U)                    /*!< EndPoint TX VALID */
7189 #define USB_EPTX_DTOG1                        (0x00000010U)                    /*!< EndPoint TX Data TOGgle bit1 */
7190 #define USB_EPTX_DTOG2                        (0x00000020U)                    /*!< EndPoint TX Data TOGgle bit2 */
7191 #define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
7192                                                                                /*!< STAT_RX[1:0] STATus for RX transfer */
7193 #define USB_EP_RX_DIS                         (0x00000000U)                    /*!< EndPoint RX DISabled */
7194 #define USB_EP_RX_STALL                       (0x00001000U)                    /*!< EndPoint RX STALLed */
7195 #define USB_EP_RX_NAK                         (0x00002000U)                    /*!< EndPoint RX NAKed */
7196 #define USB_EP_RX_VALID                       (0x00003000U)                    /*!< EndPoint RX VALID */
7197 #define USB_EPRX_DTOG1                        (0x00001000U)                    /*!< EndPoint RX Data TOGgle bit1 */
7198 #define USB_EPRX_DTOG2                        (0x00002000U)                    /*!< EndPoint RX Data TOGgle bit1 */
7199 #define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
7200 
7201 /*******************  Bit definition for USB_EP0R register  *******************/
7202 #define USB_EP0R_EA_Pos                       (0U)
7203 #define USB_EP0R_EA_Msk                       (0xFU << USB_EP0R_EA_Pos)        /*!< 0x0000000F */
7204 #define USB_EP0R_EA                           USB_EP0R_EA_Msk                  /*!<Endpoint Address */
7205 
7206 #define USB_EP0R_STAT_TX_Pos                  (4U)
7207 #define USB_EP0R_STAT_TX_Msk                  (0x3U << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000030 */
7208 #define USB_EP0R_STAT_TX                      USB_EP0R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
7209 #define USB_EP0R_STAT_TX_0                    (0x1U << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000010 */
7210 #define USB_EP0R_STAT_TX_1                    (0x2U << USB_EP0R_STAT_TX_Pos)   /*!< 0x00000020 */
7211 
7212 #define USB_EP0R_DTOG_TX_Pos                  (6U)
7213 #define USB_EP0R_DTOG_TX_Msk                  (0x1U << USB_EP0R_DTOG_TX_Pos)   /*!< 0x00000040 */
7214 #define USB_EP0R_DTOG_TX                      USB_EP0R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
7215 #define USB_EP0R_CTR_TX_Pos                   (7U)
7216 #define USB_EP0R_CTR_TX_Msk                   (0x1U << USB_EP0R_CTR_TX_Pos)    /*!< 0x00000080 */
7217 #define USB_EP0R_CTR_TX                       USB_EP0R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
7218 #define USB_EP0R_EP_KIND_Pos                  (8U)
7219 #define USB_EP0R_EP_KIND_Msk                  (0x1U << USB_EP0R_EP_KIND_Pos)   /*!< 0x00000100 */
7220 #define USB_EP0R_EP_KIND                      USB_EP0R_EP_KIND_Msk             /*!<Endpoint Kind */
7221 
7222 #define USB_EP0R_EP_TYPE_Pos                  (9U)
7223 #define USB_EP0R_EP_TYPE_Msk                  (0x3U << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000600 */
7224 #define USB_EP0R_EP_TYPE                      USB_EP0R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
7225 #define USB_EP0R_EP_TYPE_0                    (0x1U << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000200 */
7226 #define USB_EP0R_EP_TYPE_1                    (0x2U << USB_EP0R_EP_TYPE_Pos)   /*!< 0x00000400 */
7227 
7228 #define USB_EP0R_SETUP_Pos                    (11U)
7229 #define USB_EP0R_SETUP_Msk                    (0x1U << USB_EP0R_SETUP_Pos)     /*!< 0x00000800 */
7230 #define USB_EP0R_SETUP                        USB_EP0R_SETUP_Msk               /*!<Setup transaction completed */
7231 
7232 #define USB_EP0R_STAT_RX_Pos                  (12U)
7233 #define USB_EP0R_STAT_RX_Msk                  (0x3U << USB_EP0R_STAT_RX_Pos)   /*!< 0x00003000 */
7234 #define USB_EP0R_STAT_RX                      USB_EP0R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
7235 #define USB_EP0R_STAT_RX_0                    (0x1U << USB_EP0R_STAT_RX_Pos)   /*!< 0x00001000 */
7236 #define USB_EP0R_STAT_RX_1                    (0x2U << USB_EP0R_STAT_RX_Pos)   /*!< 0x00002000 */
7237 
7238 #define USB_EP0R_DTOG_RX_Pos                  (14U)
7239 #define USB_EP0R_DTOG_RX_Msk                  (0x1U << USB_EP0R_DTOG_RX_Pos)   /*!< 0x00004000 */
7240 #define USB_EP0R_DTOG_RX                      USB_EP0R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
7241 #define USB_EP0R_CTR_RX_Pos                   (15U)
7242 #define USB_EP0R_CTR_RX_Msk                   (0x1U << USB_EP0R_CTR_RX_Pos)    /*!< 0x00008000 */
7243 #define USB_EP0R_CTR_RX                       USB_EP0R_CTR_RX_Msk              /*!<Correct Transfer for reception */
7244 
7245 /*******************  Bit definition for USB_EP1R register  *******************/
7246 #define USB_EP1R_EA_Pos                       (0U)
7247 #define USB_EP1R_EA_Msk                       (0xFU << USB_EP1R_EA_Pos)        /*!< 0x0000000F */
7248 #define USB_EP1R_EA                           USB_EP1R_EA_Msk                  /*!<Endpoint Address */
7249 
7250 #define USB_EP1R_STAT_TX_Pos                  (4U)
7251 #define USB_EP1R_STAT_TX_Msk                  (0x3U << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000030 */
7252 #define USB_EP1R_STAT_TX                      USB_EP1R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
7253 #define USB_EP1R_STAT_TX_0                    (0x1U << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000010 */
7254 #define USB_EP1R_STAT_TX_1                    (0x2U << USB_EP1R_STAT_TX_Pos)   /*!< 0x00000020 */
7255 
7256 #define USB_EP1R_DTOG_TX_Pos                  (6U)
7257 #define USB_EP1R_DTOG_TX_Msk                  (0x1U << USB_EP1R_DTOG_TX_Pos)   /*!< 0x00000040 */
7258 #define USB_EP1R_DTOG_TX                      USB_EP1R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
7259 #define USB_EP1R_CTR_TX_Pos                   (7U)
7260 #define USB_EP1R_CTR_TX_Msk                   (0x1U << USB_EP1R_CTR_TX_Pos)    /*!< 0x00000080 */
7261 #define USB_EP1R_CTR_TX                       USB_EP1R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
7262 #define USB_EP1R_EP_KIND_Pos                  (8U)
7263 #define USB_EP1R_EP_KIND_Msk                  (0x1U << USB_EP1R_EP_KIND_Pos)   /*!< 0x00000100 */
7264 #define USB_EP1R_EP_KIND                      USB_EP1R_EP_KIND_Msk             /*!<Endpoint Kind */
7265 
7266 #define USB_EP1R_EP_TYPE_Pos                  (9U)
7267 #define USB_EP1R_EP_TYPE_Msk                  (0x3U << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000600 */
7268 #define USB_EP1R_EP_TYPE                      USB_EP1R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
7269 #define USB_EP1R_EP_TYPE_0                    (0x1U << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000200 */
7270 #define USB_EP1R_EP_TYPE_1                    (0x2U << USB_EP1R_EP_TYPE_Pos)   /*!< 0x00000400 */
7271 
7272 #define USB_EP1R_SETUP_Pos                    (11U)
7273 #define USB_EP1R_SETUP_Msk                    (0x1U << USB_EP1R_SETUP_Pos)     /*!< 0x00000800 */
7274 #define USB_EP1R_SETUP                        USB_EP1R_SETUP_Msk               /*!<Setup transaction completed */
7275 
7276 #define USB_EP1R_STAT_RX_Pos                  (12U)
7277 #define USB_EP1R_STAT_RX_Msk                  (0x3U << USB_EP1R_STAT_RX_Pos)   /*!< 0x00003000 */
7278 #define USB_EP1R_STAT_RX                      USB_EP1R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
7279 #define USB_EP1R_STAT_RX_0                    (0x1U << USB_EP1R_STAT_RX_Pos)   /*!< 0x00001000 */
7280 #define USB_EP1R_STAT_RX_1                    (0x2U << USB_EP1R_STAT_RX_Pos)   /*!< 0x00002000 */
7281 
7282 #define USB_EP1R_DTOG_RX_Pos                  (14U)
7283 #define USB_EP1R_DTOG_RX_Msk                  (0x1U << USB_EP1R_DTOG_RX_Pos)   /*!< 0x00004000 */
7284 #define USB_EP1R_DTOG_RX                      USB_EP1R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
7285 #define USB_EP1R_CTR_RX_Pos                   (15U)
7286 #define USB_EP1R_CTR_RX_Msk                   (0x1U << USB_EP1R_CTR_RX_Pos)    /*!< 0x00008000 */
7287 #define USB_EP1R_CTR_RX                       USB_EP1R_CTR_RX_Msk              /*!<Correct Transfer for reception */
7288 
7289 /*******************  Bit definition for USB_EP2R register  *******************/
7290 #define USB_EP2R_EA_Pos                       (0U)
7291 #define USB_EP2R_EA_Msk                       (0xFU << USB_EP2R_EA_Pos)        /*!< 0x0000000F */
7292 #define USB_EP2R_EA                           USB_EP2R_EA_Msk                  /*!<Endpoint Address */
7293 
7294 #define USB_EP2R_STAT_TX_Pos                  (4U)
7295 #define USB_EP2R_STAT_TX_Msk                  (0x3U << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000030 */
7296 #define USB_EP2R_STAT_TX                      USB_EP2R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
7297 #define USB_EP2R_STAT_TX_0                    (0x1U << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000010 */
7298 #define USB_EP2R_STAT_TX_1                    (0x2U << USB_EP2R_STAT_TX_Pos)   /*!< 0x00000020 */
7299 
7300 #define USB_EP2R_DTOG_TX_Pos                  (6U)
7301 #define USB_EP2R_DTOG_TX_Msk                  (0x1U << USB_EP2R_DTOG_TX_Pos)   /*!< 0x00000040 */
7302 #define USB_EP2R_DTOG_TX                      USB_EP2R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
7303 #define USB_EP2R_CTR_TX_Pos                   (7U)
7304 #define USB_EP2R_CTR_TX_Msk                   (0x1U << USB_EP2R_CTR_TX_Pos)    /*!< 0x00000080 */
7305 #define USB_EP2R_CTR_TX                       USB_EP2R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
7306 #define USB_EP2R_EP_KIND_Pos                  (8U)
7307 #define USB_EP2R_EP_KIND_Msk                  (0x1U << USB_EP2R_EP_KIND_Pos)   /*!< 0x00000100 */
7308 #define USB_EP2R_EP_KIND                      USB_EP2R_EP_KIND_Msk             /*!<Endpoint Kind */
7309 
7310 #define USB_EP2R_EP_TYPE_Pos                  (9U)
7311 #define USB_EP2R_EP_TYPE_Msk                  (0x3U << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000600 */
7312 #define USB_EP2R_EP_TYPE                      USB_EP2R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
7313 #define USB_EP2R_EP_TYPE_0                    (0x1U << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000200 */
7314 #define USB_EP2R_EP_TYPE_1                    (0x2U << USB_EP2R_EP_TYPE_Pos)   /*!< 0x00000400 */
7315 
7316 #define USB_EP2R_SETUP_Pos                    (11U)
7317 #define USB_EP2R_SETUP_Msk                    (0x1U << USB_EP2R_SETUP_Pos)     /*!< 0x00000800 */
7318 #define USB_EP2R_SETUP                        USB_EP2R_SETUP_Msk               /*!<Setup transaction completed */
7319 
7320 #define USB_EP2R_STAT_RX_Pos                  (12U)
7321 #define USB_EP2R_STAT_RX_Msk                  (0x3U << USB_EP2R_STAT_RX_Pos)   /*!< 0x00003000 */
7322 #define USB_EP2R_STAT_RX                      USB_EP2R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
7323 #define USB_EP2R_STAT_RX_0                    (0x1U << USB_EP2R_STAT_RX_Pos)   /*!< 0x00001000 */
7324 #define USB_EP2R_STAT_RX_1                    (0x2U << USB_EP2R_STAT_RX_Pos)   /*!< 0x00002000 */
7325 
7326 #define USB_EP2R_DTOG_RX_Pos                  (14U)
7327 #define USB_EP2R_DTOG_RX_Msk                  (0x1U << USB_EP2R_DTOG_RX_Pos)   /*!< 0x00004000 */
7328 #define USB_EP2R_DTOG_RX                      USB_EP2R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
7329 #define USB_EP2R_CTR_RX_Pos                   (15U)
7330 #define USB_EP2R_CTR_RX_Msk                   (0x1U << USB_EP2R_CTR_RX_Pos)    /*!< 0x00008000 */
7331 #define USB_EP2R_CTR_RX                       USB_EP2R_CTR_RX_Msk              /*!<Correct Transfer for reception */
7332 
7333 /*******************  Bit definition for USB_EP3R register  *******************/
7334 #define USB_EP3R_EA_Pos                       (0U)
7335 #define USB_EP3R_EA_Msk                       (0xFU << USB_EP3R_EA_Pos)        /*!< 0x0000000F */
7336 #define USB_EP3R_EA                           USB_EP3R_EA_Msk                  /*!<Endpoint Address */
7337 
7338 #define USB_EP3R_STAT_TX_Pos                  (4U)
7339 #define USB_EP3R_STAT_TX_Msk                  (0x3U << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000030 */
7340 #define USB_EP3R_STAT_TX                      USB_EP3R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
7341 #define USB_EP3R_STAT_TX_0                    (0x1U << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000010 */
7342 #define USB_EP3R_STAT_TX_1                    (0x2U << USB_EP3R_STAT_TX_Pos)   /*!< 0x00000020 */
7343 
7344 #define USB_EP3R_DTOG_TX_Pos                  (6U)
7345 #define USB_EP3R_DTOG_TX_Msk                  (0x1U << USB_EP3R_DTOG_TX_Pos)   /*!< 0x00000040 */
7346 #define USB_EP3R_DTOG_TX                      USB_EP3R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
7347 #define USB_EP3R_CTR_TX_Pos                   (7U)
7348 #define USB_EP3R_CTR_TX_Msk                   (0x1U << USB_EP3R_CTR_TX_Pos)    /*!< 0x00000080 */
7349 #define USB_EP3R_CTR_TX                       USB_EP3R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
7350 #define USB_EP3R_EP_KIND_Pos                  (8U)
7351 #define USB_EP3R_EP_KIND_Msk                  (0x1U << USB_EP3R_EP_KIND_Pos)   /*!< 0x00000100 */
7352 #define USB_EP3R_EP_KIND                      USB_EP3R_EP_KIND_Msk             /*!<Endpoint Kind */
7353 
7354 #define USB_EP3R_EP_TYPE_Pos                  (9U)
7355 #define USB_EP3R_EP_TYPE_Msk                  (0x3U << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000600 */
7356 #define USB_EP3R_EP_TYPE                      USB_EP3R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
7357 #define USB_EP3R_EP_TYPE_0                    (0x1U << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000200 */
7358 #define USB_EP3R_EP_TYPE_1                    (0x2U << USB_EP3R_EP_TYPE_Pos)   /*!< 0x00000400 */
7359 
7360 #define USB_EP3R_SETUP_Pos                    (11U)
7361 #define USB_EP3R_SETUP_Msk                    (0x1U << USB_EP3R_SETUP_Pos)     /*!< 0x00000800 */
7362 #define USB_EP3R_SETUP                        USB_EP3R_SETUP_Msk               /*!<Setup transaction completed */
7363 
7364 #define USB_EP3R_STAT_RX_Pos                  (12U)
7365 #define USB_EP3R_STAT_RX_Msk                  (0x3U << USB_EP3R_STAT_RX_Pos)   /*!< 0x00003000 */
7366 #define USB_EP3R_STAT_RX                      USB_EP3R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
7367 #define USB_EP3R_STAT_RX_0                    (0x1U << USB_EP3R_STAT_RX_Pos)   /*!< 0x00001000 */
7368 #define USB_EP3R_STAT_RX_1                    (0x2U << USB_EP3R_STAT_RX_Pos)   /*!< 0x00002000 */
7369 
7370 #define USB_EP3R_DTOG_RX_Pos                  (14U)
7371 #define USB_EP3R_DTOG_RX_Msk                  (0x1U << USB_EP3R_DTOG_RX_Pos)   /*!< 0x00004000 */
7372 #define USB_EP3R_DTOG_RX                      USB_EP3R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
7373 #define USB_EP3R_CTR_RX_Pos                   (15U)
7374 #define USB_EP3R_CTR_RX_Msk                   (0x1U << USB_EP3R_CTR_RX_Pos)    /*!< 0x00008000 */
7375 #define USB_EP3R_CTR_RX                       USB_EP3R_CTR_RX_Msk              /*!<Correct Transfer for reception */
7376 
7377 /*******************  Bit definition for USB_EP4R register  *******************/
7378 #define USB_EP4R_EA_Pos                       (0U)
7379 #define USB_EP4R_EA_Msk                       (0xFU << USB_EP4R_EA_Pos)        /*!< 0x0000000F */
7380 #define USB_EP4R_EA                           USB_EP4R_EA_Msk                  /*!<Endpoint Address */
7381 
7382 #define USB_EP4R_STAT_TX_Pos                  (4U)
7383 #define USB_EP4R_STAT_TX_Msk                  (0x3U << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000030 */
7384 #define USB_EP4R_STAT_TX                      USB_EP4R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
7385 #define USB_EP4R_STAT_TX_0                    (0x1U << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000010 */
7386 #define USB_EP4R_STAT_TX_1                    (0x2U << USB_EP4R_STAT_TX_Pos)   /*!< 0x00000020 */
7387 
7388 #define USB_EP4R_DTOG_TX_Pos                  (6U)
7389 #define USB_EP4R_DTOG_TX_Msk                  (0x1U << USB_EP4R_DTOG_TX_Pos)   /*!< 0x00000040 */
7390 #define USB_EP4R_DTOG_TX                      USB_EP4R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
7391 #define USB_EP4R_CTR_TX_Pos                   (7U)
7392 #define USB_EP4R_CTR_TX_Msk                   (0x1U << USB_EP4R_CTR_TX_Pos)    /*!< 0x00000080 */
7393 #define USB_EP4R_CTR_TX                       USB_EP4R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
7394 #define USB_EP4R_EP_KIND_Pos                  (8U)
7395 #define USB_EP4R_EP_KIND_Msk                  (0x1U << USB_EP4R_EP_KIND_Pos)   /*!< 0x00000100 */
7396 #define USB_EP4R_EP_KIND                      USB_EP4R_EP_KIND_Msk             /*!<Endpoint Kind */
7397 
7398 #define USB_EP4R_EP_TYPE_Pos                  (9U)
7399 #define USB_EP4R_EP_TYPE_Msk                  (0x3U << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000600 */
7400 #define USB_EP4R_EP_TYPE                      USB_EP4R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
7401 #define USB_EP4R_EP_TYPE_0                    (0x1U << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000200 */
7402 #define USB_EP4R_EP_TYPE_1                    (0x2U << USB_EP4R_EP_TYPE_Pos)   /*!< 0x00000400 */
7403 
7404 #define USB_EP4R_SETUP_Pos                    (11U)
7405 #define USB_EP4R_SETUP_Msk                    (0x1U << USB_EP4R_SETUP_Pos)     /*!< 0x00000800 */
7406 #define USB_EP4R_SETUP                        USB_EP4R_SETUP_Msk               /*!<Setup transaction completed */
7407 
7408 #define USB_EP4R_STAT_RX_Pos                  (12U)
7409 #define USB_EP4R_STAT_RX_Msk                  (0x3U << USB_EP4R_STAT_RX_Pos)   /*!< 0x00003000 */
7410 #define USB_EP4R_STAT_RX                      USB_EP4R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
7411 #define USB_EP4R_STAT_RX_0                    (0x1U << USB_EP4R_STAT_RX_Pos)   /*!< 0x00001000 */
7412 #define USB_EP4R_STAT_RX_1                    (0x2U << USB_EP4R_STAT_RX_Pos)   /*!< 0x00002000 */
7413 
7414 #define USB_EP4R_DTOG_RX_Pos                  (14U)
7415 #define USB_EP4R_DTOG_RX_Msk                  (0x1U << USB_EP4R_DTOG_RX_Pos)   /*!< 0x00004000 */
7416 #define USB_EP4R_DTOG_RX                      USB_EP4R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
7417 #define USB_EP4R_CTR_RX_Pos                   (15U)
7418 #define USB_EP4R_CTR_RX_Msk                   (0x1U << USB_EP4R_CTR_RX_Pos)    /*!< 0x00008000 */
7419 #define USB_EP4R_CTR_RX                       USB_EP4R_CTR_RX_Msk              /*!<Correct Transfer for reception */
7420 
7421 /*******************  Bit definition for USB_EP5R register  *******************/
7422 #define USB_EP5R_EA_Pos                       (0U)
7423 #define USB_EP5R_EA_Msk                       (0xFU << USB_EP5R_EA_Pos)        /*!< 0x0000000F */
7424 #define USB_EP5R_EA                           USB_EP5R_EA_Msk                  /*!<Endpoint Address */
7425 
7426 #define USB_EP5R_STAT_TX_Pos                  (4U)
7427 #define USB_EP5R_STAT_TX_Msk                  (0x3U << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000030 */
7428 #define USB_EP5R_STAT_TX                      USB_EP5R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
7429 #define USB_EP5R_STAT_TX_0                    (0x1U << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000010 */
7430 #define USB_EP5R_STAT_TX_1                    (0x2U << USB_EP5R_STAT_TX_Pos)   /*!< 0x00000020 */
7431 
7432 #define USB_EP5R_DTOG_TX_Pos                  (6U)
7433 #define USB_EP5R_DTOG_TX_Msk                  (0x1U << USB_EP5R_DTOG_TX_Pos)   /*!< 0x00000040 */
7434 #define USB_EP5R_DTOG_TX                      USB_EP5R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
7435 #define USB_EP5R_CTR_TX_Pos                   (7U)
7436 #define USB_EP5R_CTR_TX_Msk                   (0x1U << USB_EP5R_CTR_TX_Pos)    /*!< 0x00000080 */
7437 #define USB_EP5R_CTR_TX                       USB_EP5R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
7438 #define USB_EP5R_EP_KIND_Pos                  (8U)
7439 #define USB_EP5R_EP_KIND_Msk                  (0x1U << USB_EP5R_EP_KIND_Pos)   /*!< 0x00000100 */
7440 #define USB_EP5R_EP_KIND                      USB_EP5R_EP_KIND_Msk             /*!<Endpoint Kind */
7441 
7442 #define USB_EP5R_EP_TYPE_Pos                  (9U)
7443 #define USB_EP5R_EP_TYPE_Msk                  (0x3U << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000600 */
7444 #define USB_EP5R_EP_TYPE                      USB_EP5R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
7445 #define USB_EP5R_EP_TYPE_0                    (0x1U << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000200 */
7446 #define USB_EP5R_EP_TYPE_1                    (0x2U << USB_EP5R_EP_TYPE_Pos)   /*!< 0x00000400 */
7447 
7448 #define USB_EP5R_SETUP_Pos                    (11U)
7449 #define USB_EP5R_SETUP_Msk                    (0x1U << USB_EP5R_SETUP_Pos)     /*!< 0x00000800 */
7450 #define USB_EP5R_SETUP                        USB_EP5R_SETUP_Msk               /*!<Setup transaction completed */
7451 
7452 #define USB_EP5R_STAT_RX_Pos                  (12U)
7453 #define USB_EP5R_STAT_RX_Msk                  (0x3U << USB_EP5R_STAT_RX_Pos)   /*!< 0x00003000 */
7454 #define USB_EP5R_STAT_RX                      USB_EP5R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
7455 #define USB_EP5R_STAT_RX_0                    (0x1U << USB_EP5R_STAT_RX_Pos)   /*!< 0x00001000 */
7456 #define USB_EP5R_STAT_RX_1                    (0x2U << USB_EP5R_STAT_RX_Pos)   /*!< 0x00002000 */
7457 
7458 #define USB_EP5R_DTOG_RX_Pos                  (14U)
7459 #define USB_EP5R_DTOG_RX_Msk                  (0x1U << USB_EP5R_DTOG_RX_Pos)   /*!< 0x00004000 */
7460 #define USB_EP5R_DTOG_RX                      USB_EP5R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
7461 #define USB_EP5R_CTR_RX_Pos                   (15U)
7462 #define USB_EP5R_CTR_RX_Msk                   (0x1U << USB_EP5R_CTR_RX_Pos)    /*!< 0x00008000 */
7463 #define USB_EP5R_CTR_RX                       USB_EP5R_CTR_RX_Msk              /*!<Correct Transfer for reception */
7464 
7465 /*******************  Bit definition for USB_EP6R register  *******************/
7466 #define USB_EP6R_EA_Pos                       (0U)
7467 #define USB_EP6R_EA_Msk                       (0xFU << USB_EP6R_EA_Pos)        /*!< 0x0000000F */
7468 #define USB_EP6R_EA                           USB_EP6R_EA_Msk                  /*!<Endpoint Address */
7469 
7470 #define USB_EP6R_STAT_TX_Pos                  (4U)
7471 #define USB_EP6R_STAT_TX_Msk                  (0x3U << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000030 */
7472 #define USB_EP6R_STAT_TX                      USB_EP6R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
7473 #define USB_EP6R_STAT_TX_0                    (0x1U << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000010 */
7474 #define USB_EP6R_STAT_TX_1                    (0x2U << USB_EP6R_STAT_TX_Pos)   /*!< 0x00000020 */
7475 
7476 #define USB_EP6R_DTOG_TX_Pos                  (6U)
7477 #define USB_EP6R_DTOG_TX_Msk                  (0x1U << USB_EP6R_DTOG_TX_Pos)   /*!< 0x00000040 */
7478 #define USB_EP6R_DTOG_TX                      USB_EP6R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
7479 #define USB_EP6R_CTR_TX_Pos                   (7U)
7480 #define USB_EP6R_CTR_TX_Msk                   (0x1U << USB_EP6R_CTR_TX_Pos)    /*!< 0x00000080 */
7481 #define USB_EP6R_CTR_TX                       USB_EP6R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
7482 #define USB_EP6R_EP_KIND_Pos                  (8U)
7483 #define USB_EP6R_EP_KIND_Msk                  (0x1U << USB_EP6R_EP_KIND_Pos)   /*!< 0x00000100 */
7484 #define USB_EP6R_EP_KIND                      USB_EP6R_EP_KIND_Msk             /*!<Endpoint Kind */
7485 
7486 #define USB_EP6R_EP_TYPE_Pos                  (9U)
7487 #define USB_EP6R_EP_TYPE_Msk                  (0x3U << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000600 */
7488 #define USB_EP6R_EP_TYPE                      USB_EP6R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
7489 #define USB_EP6R_EP_TYPE_0                    (0x1U << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000200 */
7490 #define USB_EP6R_EP_TYPE_1                    (0x2U << USB_EP6R_EP_TYPE_Pos)   /*!< 0x00000400 */
7491 
7492 #define USB_EP6R_SETUP_Pos                    (11U)
7493 #define USB_EP6R_SETUP_Msk                    (0x1U << USB_EP6R_SETUP_Pos)     /*!< 0x00000800 */
7494 #define USB_EP6R_SETUP                        USB_EP6R_SETUP_Msk               /*!<Setup transaction completed */
7495 
7496 #define USB_EP6R_STAT_RX_Pos                  (12U)
7497 #define USB_EP6R_STAT_RX_Msk                  (0x3U << USB_EP6R_STAT_RX_Pos)   /*!< 0x00003000 */
7498 #define USB_EP6R_STAT_RX                      USB_EP6R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
7499 #define USB_EP6R_STAT_RX_0                    (0x1U << USB_EP6R_STAT_RX_Pos)   /*!< 0x00001000 */
7500 #define USB_EP6R_STAT_RX_1                    (0x2U << USB_EP6R_STAT_RX_Pos)   /*!< 0x00002000 */
7501 
7502 #define USB_EP6R_DTOG_RX_Pos                  (14U)
7503 #define USB_EP6R_DTOG_RX_Msk                  (0x1U << USB_EP6R_DTOG_RX_Pos)   /*!< 0x00004000 */
7504 #define USB_EP6R_DTOG_RX                      USB_EP6R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
7505 #define USB_EP6R_CTR_RX_Pos                   (15U)
7506 #define USB_EP6R_CTR_RX_Msk                   (0x1U << USB_EP6R_CTR_RX_Pos)    /*!< 0x00008000 */
7507 #define USB_EP6R_CTR_RX                       USB_EP6R_CTR_RX_Msk              /*!<Correct Transfer for reception */
7508 
7509 /*******************  Bit definition for USB_EP7R register  *******************/
7510 #define USB_EP7R_EA_Pos                       (0U)
7511 #define USB_EP7R_EA_Msk                       (0xFU << USB_EP7R_EA_Pos)        /*!< 0x0000000F */
7512 #define USB_EP7R_EA                           USB_EP7R_EA_Msk                  /*!<Endpoint Address */
7513 
7514 #define USB_EP7R_STAT_TX_Pos                  (4U)
7515 #define USB_EP7R_STAT_TX_Msk                  (0x3U << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000030 */
7516 #define USB_EP7R_STAT_TX                      USB_EP7R_STAT_TX_Msk             /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
7517 #define USB_EP7R_STAT_TX_0                    (0x1U << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000010 */
7518 #define USB_EP7R_STAT_TX_1                    (0x2U << USB_EP7R_STAT_TX_Pos)   /*!< 0x00000020 */
7519 
7520 #define USB_EP7R_DTOG_TX_Pos                  (6U)
7521 #define USB_EP7R_DTOG_TX_Msk                  (0x1U << USB_EP7R_DTOG_TX_Pos)   /*!< 0x00000040 */
7522 #define USB_EP7R_DTOG_TX                      USB_EP7R_DTOG_TX_Msk             /*!<Data Toggle, for transmission transfers */
7523 #define USB_EP7R_CTR_TX_Pos                   (7U)
7524 #define USB_EP7R_CTR_TX_Msk                   (0x1U << USB_EP7R_CTR_TX_Pos)    /*!< 0x00000080 */
7525 #define USB_EP7R_CTR_TX                       USB_EP7R_CTR_TX_Msk              /*!<Correct Transfer for transmission */
7526 #define USB_EP7R_EP_KIND_Pos                  (8U)
7527 #define USB_EP7R_EP_KIND_Msk                  (0x1U << USB_EP7R_EP_KIND_Pos)   /*!< 0x00000100 */
7528 #define USB_EP7R_EP_KIND                      USB_EP7R_EP_KIND_Msk             /*!<Endpoint Kind */
7529 
7530 #define USB_EP7R_EP_TYPE_Pos                  (9U)
7531 #define USB_EP7R_EP_TYPE_Msk                  (0x3U << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000600 */
7532 #define USB_EP7R_EP_TYPE                      USB_EP7R_EP_TYPE_Msk             /*!<EP_TYPE[1:0] bits (Endpoint type) */
7533 #define USB_EP7R_EP_TYPE_0                    (0x1U << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000200 */
7534 #define USB_EP7R_EP_TYPE_1                    (0x2U << USB_EP7R_EP_TYPE_Pos)   /*!< 0x00000400 */
7535 
7536 #define USB_EP7R_SETUP_Pos                    (11U)
7537 #define USB_EP7R_SETUP_Msk                    (0x1U << USB_EP7R_SETUP_Pos)     /*!< 0x00000800 */
7538 #define USB_EP7R_SETUP                        USB_EP7R_SETUP_Msk               /*!<Setup transaction completed */
7539 
7540 #define USB_EP7R_STAT_RX_Pos                  (12U)
7541 #define USB_EP7R_STAT_RX_Msk                  (0x3U << USB_EP7R_STAT_RX_Pos)   /*!< 0x00003000 */
7542 #define USB_EP7R_STAT_RX                      USB_EP7R_STAT_RX_Msk             /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
7543 #define USB_EP7R_STAT_RX_0                    (0x1U << USB_EP7R_STAT_RX_Pos)   /*!< 0x00001000 */
7544 #define USB_EP7R_STAT_RX_1                    (0x2U << USB_EP7R_STAT_RX_Pos)   /*!< 0x00002000 */
7545 
7546 #define USB_EP7R_DTOG_RX_Pos                  (14U)
7547 #define USB_EP7R_DTOG_RX_Msk                  (0x1U << USB_EP7R_DTOG_RX_Pos)   /*!< 0x00004000 */
7548 #define USB_EP7R_DTOG_RX                      USB_EP7R_DTOG_RX_Msk             /*!<Data Toggle, for reception transfers */
7549 #define USB_EP7R_CTR_RX_Pos                   (15U)
7550 #define USB_EP7R_CTR_RX_Msk                   (0x1U << USB_EP7R_CTR_RX_Pos)    /*!< 0x00008000 */
7551 #define USB_EP7R_CTR_RX                       USB_EP7R_CTR_RX_Msk              /*!<Correct Transfer for reception */
7552 
7553 /*!<Common registers */
7554 
7555 #define  USB_CNTR                             (USB_BASE + 0x00000040U)          /*!< Control register */
7556 #define  USB_ISTR                             (USB_BASE + 0x00000044U)          /*!< Interrupt status register */
7557 #define  USB_FNR                              (USB_BASE + 0x00000048U)          /*!< Frame number register */
7558 #define  USB_DADDR                            (USB_BASE + 0x0000004CU)          /*!< Device address register */
7559 #define  USB_BTABLE                           (USB_BASE + 0x00000050U)          /*!< Buffer Table address register */
7560 
7561 
7562 
7563 /*******************  Bit definition for USB_CNTR register  *******************/
7564 #define USB_CNTR_FRES_Pos                     (0U)
7565 #define USB_CNTR_FRES_Msk                     (0x1U << USB_CNTR_FRES_Pos)      /*!< 0x00000001 */
7566 #define USB_CNTR_FRES                         USB_CNTR_FRES_Msk                /*!<Force USB Reset */
7567 #define USB_CNTR_PDWN_Pos                     (1U)
7568 #define USB_CNTR_PDWN_Msk                     (0x1U << USB_CNTR_PDWN_Pos)      /*!< 0x00000002 */
7569 #define USB_CNTR_PDWN                         USB_CNTR_PDWN_Msk                /*!<Power down */
7570 #define USB_CNTR_LPMODE_Pos                   (2U)
7571 #define USB_CNTR_LPMODE_Msk                   (0x1U << USB_CNTR_LPMODE_Pos)    /*!< 0x00000004 */
7572 #define USB_CNTR_LPMODE                       USB_CNTR_LPMODE_Msk              /*!<Low-power mode */
7573 #define USB_CNTR_FSUSP_Pos                    (3U)
7574 #define USB_CNTR_FSUSP_Msk                    (0x1U << USB_CNTR_FSUSP_Pos)     /*!< 0x00000008 */
7575 #define USB_CNTR_FSUSP                        USB_CNTR_FSUSP_Msk               /*!<Force suspend */
7576 #define USB_CNTR_RESUME_Pos                   (4U)
7577 #define USB_CNTR_RESUME_Msk                   (0x1U << USB_CNTR_RESUME_Pos)    /*!< 0x00000010 */
7578 #define USB_CNTR_RESUME                       USB_CNTR_RESUME_Msk              /*!<Resume request */
7579 #define USB_CNTR_ESOFM_Pos                    (8U)
7580 #define USB_CNTR_ESOFM_Msk                    (0x1U << USB_CNTR_ESOFM_Pos)     /*!< 0x00000100 */
7581 #define USB_CNTR_ESOFM                        USB_CNTR_ESOFM_Msk               /*!<Expected Start Of Frame Interrupt Mask */
7582 #define USB_CNTR_SOFM_Pos                     (9U)
7583 #define USB_CNTR_SOFM_Msk                     (0x1U << USB_CNTR_SOFM_Pos)      /*!< 0x00000200 */
7584 #define USB_CNTR_SOFM                         USB_CNTR_SOFM_Msk                /*!<Start Of Frame Interrupt Mask */
7585 #define USB_CNTR_RESETM_Pos                   (10U)
7586 #define USB_CNTR_RESETM_Msk                   (0x1U << USB_CNTR_RESETM_Pos)    /*!< 0x00000400 */
7587 #define USB_CNTR_RESETM                       USB_CNTR_RESETM_Msk              /*!<RESET Interrupt Mask */
7588 #define USB_CNTR_SUSPM_Pos                    (11U)
7589 #define USB_CNTR_SUSPM_Msk                    (0x1U << USB_CNTR_SUSPM_Pos)     /*!< 0x00000800 */
7590 #define USB_CNTR_SUSPM                        USB_CNTR_SUSPM_Msk               /*!<Suspend mode Interrupt Mask */
7591 #define USB_CNTR_WKUPM_Pos                    (12U)
7592 #define USB_CNTR_WKUPM_Msk                    (0x1U << USB_CNTR_WKUPM_Pos)     /*!< 0x00001000 */
7593 #define USB_CNTR_WKUPM                        USB_CNTR_WKUPM_Msk               /*!<Wakeup Interrupt Mask */
7594 #define USB_CNTR_ERRM_Pos                     (13U)
7595 #define USB_CNTR_ERRM_Msk                     (0x1U << USB_CNTR_ERRM_Pos)      /*!< 0x00002000 */
7596 #define USB_CNTR_ERRM                         USB_CNTR_ERRM_Msk                /*!<Error Interrupt Mask */
7597 #define USB_CNTR_PMAOVRM_Pos                  (14U)
7598 #define USB_CNTR_PMAOVRM_Msk                  (0x1U << USB_CNTR_PMAOVRM_Pos)   /*!< 0x00004000 */
7599 #define USB_CNTR_PMAOVRM                      USB_CNTR_PMAOVRM_Msk             /*!<Packet Memory Area Over / Underrun Interrupt Mask */
7600 #define USB_CNTR_CTRM_Pos                     (15U)
7601 #define USB_CNTR_CTRM_Msk                     (0x1U << USB_CNTR_CTRM_Pos)      /*!< 0x00008000 */
7602 #define USB_CNTR_CTRM                         USB_CNTR_CTRM_Msk                /*!<Correct Transfer Interrupt Mask */
7603 
7604 /*******************  Bit definition for USB_ISTR register  *******************/
7605 #define USB_ISTR_EP_ID_Pos                    (0U)
7606 #define USB_ISTR_EP_ID_Msk                    (0xFU << USB_ISTR_EP_ID_Pos)     /*!< 0x0000000F */
7607 #define USB_ISTR_EP_ID                        USB_ISTR_EP_ID_Msk               /*!<Endpoint Identifier */
7608 #define USB_ISTR_DIR_Pos                      (4U)
7609 #define USB_ISTR_DIR_Msk                      (0x1U << USB_ISTR_DIR_Pos)       /*!< 0x00000010 */
7610 #define USB_ISTR_DIR                          USB_ISTR_DIR_Msk                 /*!<Direction of transaction */
7611 #define USB_ISTR_ESOF_Pos                     (8U)
7612 #define USB_ISTR_ESOF_Msk                     (0x1U << USB_ISTR_ESOF_Pos)      /*!< 0x00000100 */
7613 #define USB_ISTR_ESOF                         USB_ISTR_ESOF_Msk                /*!<Expected Start Of Frame */
7614 #define USB_ISTR_SOF_Pos                      (9U)
7615 #define USB_ISTR_SOF_Msk                      (0x1U << USB_ISTR_SOF_Pos)       /*!< 0x00000200 */
7616 #define USB_ISTR_SOF                          USB_ISTR_SOF_Msk                 /*!<Start Of Frame */
7617 #define USB_ISTR_RESET_Pos                    (10U)
7618 #define USB_ISTR_RESET_Msk                    (0x1U << USB_ISTR_RESET_Pos)     /*!< 0x00000400 */
7619 #define USB_ISTR_RESET                        USB_ISTR_RESET_Msk               /*!<USB RESET request */
7620 #define USB_ISTR_SUSP_Pos                     (11U)
7621 #define USB_ISTR_SUSP_Msk                     (0x1U << USB_ISTR_SUSP_Pos)      /*!< 0x00000800 */
7622 #define USB_ISTR_SUSP                         USB_ISTR_SUSP_Msk                /*!<Suspend mode request */
7623 #define USB_ISTR_WKUP_Pos                     (12U)
7624 #define USB_ISTR_WKUP_Msk                     (0x1U << USB_ISTR_WKUP_Pos)      /*!< 0x00001000 */
7625 #define USB_ISTR_WKUP                         USB_ISTR_WKUP_Msk                /*!<Wake up */
7626 #define USB_ISTR_ERR_Pos                      (13U)
7627 #define USB_ISTR_ERR_Msk                      (0x1U << USB_ISTR_ERR_Pos)       /*!< 0x00002000 */
7628 #define USB_ISTR_ERR                          USB_ISTR_ERR_Msk                 /*!<Error */
7629 #define USB_ISTR_PMAOVR_Pos                   (14U)
7630 #define USB_ISTR_PMAOVR_Msk                   (0x1U << USB_ISTR_PMAOVR_Pos)    /*!< 0x00004000 */
7631 #define USB_ISTR_PMAOVR                       USB_ISTR_PMAOVR_Msk              /*!<Packet Memory Area Over / Underrun */
7632 #define USB_ISTR_CTR_Pos                      (15U)
7633 #define USB_ISTR_CTR_Msk                      (0x1U << USB_ISTR_CTR_Pos)       /*!< 0x00008000 */
7634 #define USB_ISTR_CTR                          USB_ISTR_CTR_Msk                 /*!<Correct Transfer */
7635 
7636 #define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
7637 #define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
7638 #define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
7639 #define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
7640 #define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
7641 #define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
7642 #define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
7643 #define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
7644 
7645 
7646 /*******************  Bit definition for USB_FNR register  ********************/
7647 #define USB_FNR_FN_Pos                        (0U)
7648 #define USB_FNR_FN_Msk                        (0x7FFU << USB_FNR_FN_Pos)       /*!< 0x000007FF */
7649 #define USB_FNR_FN                            USB_FNR_FN_Msk                   /*!<Frame Number */
7650 #define USB_FNR_LSOF_Pos                      (11U)
7651 #define USB_FNR_LSOF_Msk                      (0x3U << USB_FNR_LSOF_Pos)       /*!< 0x00001800 */
7652 #define USB_FNR_LSOF                          USB_FNR_LSOF_Msk                 /*!<Lost SOF */
7653 #define USB_FNR_LCK_Pos                       (13U)
7654 #define USB_FNR_LCK_Msk                       (0x1U << USB_FNR_LCK_Pos)        /*!< 0x00002000 */
7655 #define USB_FNR_LCK                           USB_FNR_LCK_Msk                  /*!<Locked */
7656 #define USB_FNR_RXDM_Pos                      (14U)
7657 #define USB_FNR_RXDM_Msk                      (0x1U << USB_FNR_RXDM_Pos)       /*!< 0x00004000 */
7658 #define USB_FNR_RXDM                          USB_FNR_RXDM_Msk                 /*!<Receive Data - Line Status */
7659 #define USB_FNR_RXDP_Pos                      (15U)
7660 #define USB_FNR_RXDP_Msk                      (0x1U << USB_FNR_RXDP_Pos)       /*!< 0x00008000 */
7661 #define USB_FNR_RXDP                          USB_FNR_RXDP_Msk                 /*!<Receive Data + Line Status */
7662 
7663 /******************  Bit definition for USB_DADDR register  *******************/
7664 #define USB_DADDR_ADD_Pos                     (0U)
7665 #define USB_DADDR_ADD_Msk                     (0x7FU << USB_DADDR_ADD_Pos)     /*!< 0x0000007F */
7666 #define USB_DADDR_ADD                         USB_DADDR_ADD_Msk                /*!<ADD[6:0] bits (Device Address) */
7667 #define USB_DADDR_ADD0_Pos                    (0U)
7668 #define USB_DADDR_ADD0_Msk                    (0x1U << USB_DADDR_ADD0_Pos)     /*!< 0x00000001 */
7669 #define USB_DADDR_ADD0                        USB_DADDR_ADD0_Msk               /*!<Bit 0 */
7670 #define USB_DADDR_ADD1_Pos                    (1U)
7671 #define USB_DADDR_ADD1_Msk                    (0x1U << USB_DADDR_ADD1_Pos)     /*!< 0x00000002 */
7672 #define USB_DADDR_ADD1                        USB_DADDR_ADD1_Msk               /*!<Bit 1 */
7673 #define USB_DADDR_ADD2_Pos                    (2U)
7674 #define USB_DADDR_ADD2_Msk                    (0x1U << USB_DADDR_ADD2_Pos)     /*!< 0x00000004 */
7675 #define USB_DADDR_ADD2                        USB_DADDR_ADD2_Msk               /*!<Bit 2 */
7676 #define USB_DADDR_ADD3_Pos                    (3U)
7677 #define USB_DADDR_ADD3_Msk                    (0x1U << USB_DADDR_ADD3_Pos)     /*!< 0x00000008 */
7678 #define USB_DADDR_ADD3                        USB_DADDR_ADD3_Msk               /*!<Bit 3 */
7679 #define USB_DADDR_ADD4_Pos                    (4U)
7680 #define USB_DADDR_ADD4_Msk                    (0x1U << USB_DADDR_ADD4_Pos)     /*!< 0x00000010 */
7681 #define USB_DADDR_ADD4                        USB_DADDR_ADD4_Msk               /*!<Bit 4 */
7682 #define USB_DADDR_ADD5_Pos                    (5U)
7683 #define USB_DADDR_ADD5_Msk                    (0x1U << USB_DADDR_ADD5_Pos)     /*!< 0x00000020 */
7684 #define USB_DADDR_ADD5                        USB_DADDR_ADD5_Msk               /*!<Bit 5 */
7685 #define USB_DADDR_ADD6_Pos                    (6U)
7686 #define USB_DADDR_ADD6_Msk                    (0x1U << USB_DADDR_ADD6_Pos)     /*!< 0x00000040 */
7687 #define USB_DADDR_ADD6                        USB_DADDR_ADD6_Msk               /*!<Bit 6 */
7688 
7689 #define USB_DADDR_EF_Pos                      (7U)
7690 #define USB_DADDR_EF_Msk                      (0x1U << USB_DADDR_EF_Pos)       /*!< 0x00000080 */
7691 #define USB_DADDR_EF                          USB_DADDR_EF_Msk                 /*!<Enable Function */
7692 
7693 /******************  Bit definition for USB_BTABLE register  ******************/
7694 #define USB_BTABLE_BTABLE_Pos                 (3U)
7695 #define USB_BTABLE_BTABLE_Msk                 (0x1FFFU << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */
7696 #define USB_BTABLE_BTABLE                     USB_BTABLE_BTABLE_Msk            /*!<Buffer Table */
7697 
7698 /*!< Buffer descriptor table */
7699 /*****************  Bit definition for USB_ADDR0_TX register  *****************/
7700 #define USB_ADDR0_TX_ADDR0_TX_Pos             (1U)
7701 #define USB_ADDR0_TX_ADDR0_TX_Msk             (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */
7702 #define USB_ADDR0_TX_ADDR0_TX                 USB_ADDR0_TX_ADDR0_TX_Msk        /*!< Transmission Buffer Address 0 */
7703 
7704 /*****************  Bit definition for USB_ADDR1_TX register  *****************/
7705 #define USB_ADDR1_TX_ADDR1_TX_Pos             (1U)
7706 #define USB_ADDR1_TX_ADDR1_TX_Msk             (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */
7707 #define USB_ADDR1_TX_ADDR1_TX                 USB_ADDR1_TX_ADDR1_TX_Msk        /*!< Transmission Buffer Address 1 */
7708 
7709 /*****************  Bit definition for USB_ADDR2_TX register  *****************/
7710 #define USB_ADDR2_TX_ADDR2_TX_Pos             (1U)
7711 #define USB_ADDR2_TX_ADDR2_TX_Msk             (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */
7712 #define USB_ADDR2_TX_ADDR2_TX                 USB_ADDR2_TX_ADDR2_TX_Msk        /*!< Transmission Buffer Address 2 */
7713 
7714 /*****************  Bit definition for USB_ADDR3_TX register  *****************/
7715 #define USB_ADDR3_TX_ADDR3_TX_Pos             (1U)
7716 #define USB_ADDR3_TX_ADDR3_TX_Msk             (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */
7717 #define USB_ADDR3_TX_ADDR3_TX                 USB_ADDR3_TX_ADDR3_TX_Msk        /*!< Transmission Buffer Address 3 */
7718 
7719 /*****************  Bit definition for USB_ADDR4_TX register  *****************/
7720 #define USB_ADDR4_TX_ADDR4_TX_Pos             (1U)
7721 #define USB_ADDR4_TX_ADDR4_TX_Msk             (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */
7722 #define USB_ADDR4_TX_ADDR4_TX                 USB_ADDR4_TX_ADDR4_TX_Msk        /*!< Transmission Buffer Address 4 */
7723 
7724 /*****************  Bit definition for USB_ADDR5_TX register  *****************/
7725 #define USB_ADDR5_TX_ADDR5_TX_Pos             (1U)
7726 #define USB_ADDR5_TX_ADDR5_TX_Msk             (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */
7727 #define USB_ADDR5_TX_ADDR5_TX                 USB_ADDR5_TX_ADDR5_TX_Msk        /*!< Transmission Buffer Address 5 */
7728 
7729 /*****************  Bit definition for USB_ADDR6_TX register  *****************/
7730 #define USB_ADDR6_TX_ADDR6_TX_Pos             (1U)
7731 #define USB_ADDR6_TX_ADDR6_TX_Msk             (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */
7732 #define USB_ADDR6_TX_ADDR6_TX                 USB_ADDR6_TX_ADDR6_TX_Msk        /*!< Transmission Buffer Address 6 */
7733 
7734 /*****************  Bit definition for USB_ADDR7_TX register  *****************/
7735 #define USB_ADDR7_TX_ADDR7_TX_Pos             (1U)
7736 #define USB_ADDR7_TX_ADDR7_TX_Msk             (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */
7737 #define USB_ADDR7_TX_ADDR7_TX                 USB_ADDR7_TX_ADDR7_TX_Msk        /*!< Transmission Buffer Address 7 */
7738 
7739 /*----------------------------------------------------------------------------*/
7740 
7741 /*****************  Bit definition for USB_COUNT0_TX register  ****************/
7742 #define USB_COUNT0_TX_COUNT0_TX_Pos           (0U)
7743 #define USB_COUNT0_TX_COUNT0_TX_Msk           (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */
7744 #define USB_COUNT0_TX_COUNT0_TX               USB_COUNT0_TX_COUNT0_TX_Msk      /*!< Transmission Byte Count 0 */
7745 
7746 /*****************  Bit definition for USB_COUNT1_TX register  ****************/
7747 #define USB_COUNT1_TX_COUNT1_TX_Pos           (0U)
7748 #define USB_COUNT1_TX_COUNT1_TX_Msk           (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */
7749 #define USB_COUNT1_TX_COUNT1_TX               USB_COUNT1_TX_COUNT1_TX_Msk      /*!< Transmission Byte Count 1 */
7750 
7751 /*****************  Bit definition for USB_COUNT2_TX register  ****************/
7752 #define USB_COUNT2_TX_COUNT2_TX_Pos           (0U)
7753 #define USB_COUNT2_TX_COUNT2_TX_Msk           (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */
7754 #define USB_COUNT2_TX_COUNT2_TX               USB_COUNT2_TX_COUNT2_TX_Msk      /*!< Transmission Byte Count 2 */
7755 
7756 /*****************  Bit definition for USB_COUNT3_TX register  ****************/
7757 #define USB_COUNT3_TX_COUNT3_TX_Pos           (0U)
7758 #define USB_COUNT3_TX_COUNT3_TX_Msk           (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */
7759 #define USB_COUNT3_TX_COUNT3_TX               USB_COUNT3_TX_COUNT3_TX_Msk      /*!< Transmission Byte Count 3 */
7760 
7761 /*****************  Bit definition for USB_COUNT4_TX register  ****************/
7762 #define USB_COUNT4_TX_COUNT4_TX_Pos           (0U)
7763 #define USB_COUNT4_TX_COUNT4_TX_Msk           (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */
7764 #define USB_COUNT4_TX_COUNT4_TX               USB_COUNT4_TX_COUNT4_TX_Msk      /*!< Transmission Byte Count 4 */
7765 
7766 /*****************  Bit definition for USB_COUNT5_TX register  ****************/
7767 #define USB_COUNT5_TX_COUNT5_TX_Pos           (0U)
7768 #define USB_COUNT5_TX_COUNT5_TX_Msk           (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */
7769 #define USB_COUNT5_TX_COUNT5_TX               USB_COUNT5_TX_COUNT5_TX_Msk      /*!< Transmission Byte Count 5 */
7770 
7771 /*****************  Bit definition for USB_COUNT6_TX register  ****************/
7772 #define USB_COUNT6_TX_COUNT6_TX_Pos           (0U)
7773 #define USB_COUNT6_TX_COUNT6_TX_Msk           (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */
7774 #define USB_COUNT6_TX_COUNT6_TX               USB_COUNT6_TX_COUNT6_TX_Msk      /*!< Transmission Byte Count 6 */
7775 
7776 /*****************  Bit definition for USB_COUNT7_TX register  ****************/
7777 #define USB_COUNT7_TX_COUNT7_TX_Pos           (0U)
7778 #define USB_COUNT7_TX_COUNT7_TX_Msk           (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */
7779 #define USB_COUNT7_TX_COUNT7_TX               USB_COUNT7_TX_COUNT7_TX_Msk      /*!< Transmission Byte Count 7 */
7780 
7781 /*----------------------------------------------------------------------------*/
7782 
7783 /****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
7784 #define USB_COUNT0_TX_0_COUNT0_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 0 (low) */
7785 
7786 /****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
7787 #define USB_COUNT0_TX_1_COUNT0_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 0 (high) */
7788 
7789 /****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
7790 #define USB_COUNT1_TX_0_COUNT1_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 1 (low) */
7791 
7792 /****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
7793 #define USB_COUNT1_TX_1_COUNT1_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 1 (high) */
7794 
7795 /****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
7796 #define USB_COUNT2_TX_0_COUNT2_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 2 (low) */
7797 
7798 /****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
7799 #define USB_COUNT2_TX_1_COUNT2_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 2 (high) */
7800 
7801 /****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
7802 #define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint32_t)0x00000000U03FF)        /*!< Transmission Byte Count 3 (low) */
7803 
7804 /****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
7805 #define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint32_t)0x000003FFU0000)        /*!< Transmission Byte Count 3 (high) */
7806 
7807 /****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
7808 #define USB_COUNT4_TX_0_COUNT4_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 4 (low) */
7809 
7810 /****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
7811 #define USB_COUNT4_TX_1_COUNT4_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 4 (high) */
7812 
7813 /****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
7814 #define USB_COUNT5_TX_0_COUNT5_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 5 (low) */
7815 
7816 /****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
7817 #define USB_COUNT5_TX_1_COUNT5_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 5 (high) */
7818 
7819 /****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
7820 #define USB_COUNT6_TX_0_COUNT6_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 6 (low) */
7821 
7822 /****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
7823 #define USB_COUNT6_TX_1_COUNT6_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 6 (high) */
7824 
7825 /****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
7826 #define USB_COUNT7_TX_0_COUNT7_TX_0           (0x000003FFU)                    /*!< Transmission Byte Count 7 (low) */
7827 
7828 /****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
7829 #define USB_COUNT7_TX_1_COUNT7_TX_1           (0x03FF0000U)                    /*!< Transmission Byte Count 7 (high) */
7830 
7831 /*----------------------------------------------------------------------------*/
7832 
7833 /*****************  Bit definition for USB_ADDR0_RX register  *****************/
7834 #define USB_ADDR0_RX_ADDR0_RX_Pos             (1U)
7835 #define USB_ADDR0_RX_ADDR0_RX_Msk             (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */
7836 #define USB_ADDR0_RX_ADDR0_RX                 USB_ADDR0_RX_ADDR0_RX_Msk        /*!< Reception Buffer Address 0 */
7837 
7838 /*****************  Bit definition for USB_ADDR1_RX register  *****************/
7839 #define USB_ADDR1_RX_ADDR1_RX_Pos             (1U)
7840 #define USB_ADDR1_RX_ADDR1_RX_Msk             (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */
7841 #define USB_ADDR1_RX_ADDR1_RX                 USB_ADDR1_RX_ADDR1_RX_Msk        /*!< Reception Buffer Address 1 */
7842 
7843 /*****************  Bit definition for USB_ADDR2_RX register  *****************/
7844 #define USB_ADDR2_RX_ADDR2_RX_Pos             (1U)
7845 #define USB_ADDR2_RX_ADDR2_RX_Msk             (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */
7846 #define USB_ADDR2_RX_ADDR2_RX                 USB_ADDR2_RX_ADDR2_RX_Msk        /*!< Reception Buffer Address 2 */
7847 
7848 /*****************  Bit definition for USB_ADDR3_RX register  *****************/
7849 #define USB_ADDR3_RX_ADDR3_RX_Pos             (1U)
7850 #define USB_ADDR3_RX_ADDR3_RX_Msk             (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */
7851 #define USB_ADDR3_RX_ADDR3_RX                 USB_ADDR3_RX_ADDR3_RX_Msk        /*!< Reception Buffer Address 3 */
7852 
7853 /*****************  Bit definition for USB_ADDR4_RX register  *****************/
7854 #define USB_ADDR4_RX_ADDR4_RX_Pos             (1U)
7855 #define USB_ADDR4_RX_ADDR4_RX_Msk             (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */
7856 #define USB_ADDR4_RX_ADDR4_RX                 USB_ADDR4_RX_ADDR4_RX_Msk        /*!< Reception Buffer Address 4 */
7857 
7858 /*****************  Bit definition for USB_ADDR5_RX register  *****************/
7859 #define USB_ADDR5_RX_ADDR5_RX_Pos             (1U)
7860 #define USB_ADDR5_RX_ADDR5_RX_Msk             (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */
7861 #define USB_ADDR5_RX_ADDR5_RX                 USB_ADDR5_RX_ADDR5_RX_Msk        /*!< Reception Buffer Address 5 */
7862 
7863 /*****************  Bit definition for USB_ADDR6_RX register  *****************/
7864 #define USB_ADDR6_RX_ADDR6_RX_Pos             (1U)
7865 #define USB_ADDR6_RX_ADDR6_RX_Msk             (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */
7866 #define USB_ADDR6_RX_ADDR6_RX                 USB_ADDR6_RX_ADDR6_RX_Msk        /*!< Reception Buffer Address 6 */
7867 
7868 /*****************  Bit definition for USB_ADDR7_RX register  *****************/
7869 #define USB_ADDR7_RX_ADDR7_RX_Pos             (1U)
7870 #define USB_ADDR7_RX_ADDR7_RX_Msk             (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */
7871 #define USB_ADDR7_RX_ADDR7_RX                 USB_ADDR7_RX_ADDR7_RX_Msk        /*!< Reception Buffer Address 7 */
7872 
7873 /*----------------------------------------------------------------------------*/
7874 
7875 /*****************  Bit definition for USB_COUNT0_RX register  ****************/
7876 #define USB_COUNT0_RX_COUNT0_RX_Pos           (0U)
7877 #define USB_COUNT0_RX_COUNT0_RX_Msk           (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */
7878 #define USB_COUNT0_RX_COUNT0_RX               USB_COUNT0_RX_COUNT0_RX_Msk      /*!< Reception Byte Count */
7879 
7880 #define USB_COUNT0_RX_NUM_BLOCK_Pos           (10U)
7881 #define USB_COUNT0_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
7882 #define USB_COUNT0_RX_NUM_BLOCK               USB_COUNT0_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
7883 #define USB_COUNT0_RX_NUM_BLOCK_0             (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
7884 #define USB_COUNT0_RX_NUM_BLOCK_1             (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
7885 #define USB_COUNT0_RX_NUM_BLOCK_2             (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
7886 #define USB_COUNT0_RX_NUM_BLOCK_3             (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
7887 #define USB_COUNT0_RX_NUM_BLOCK_4             (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
7888 
7889 #define USB_COUNT0_RX_BLSIZE_Pos              (15U)
7890 #define USB_COUNT0_RX_BLSIZE_Msk              (0x1U << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */
7891 #define USB_COUNT0_RX_BLSIZE                  USB_COUNT0_RX_BLSIZE_Msk         /*!< BLock SIZE */
7892 
7893 /*****************  Bit definition for USB_COUNT1_RX register  ****************/
7894 #define USB_COUNT1_RX_COUNT1_RX_Pos           (0U)
7895 #define USB_COUNT1_RX_COUNT1_RX_Msk           (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */
7896 #define USB_COUNT1_RX_COUNT1_RX               USB_COUNT1_RX_COUNT1_RX_Msk      /*!< Reception Byte Count */
7897 
7898 #define USB_COUNT1_RX_NUM_BLOCK_Pos           (10U)
7899 #define USB_COUNT1_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
7900 #define USB_COUNT1_RX_NUM_BLOCK               USB_COUNT1_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
7901 #define USB_COUNT1_RX_NUM_BLOCK_0             (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
7902 #define USB_COUNT1_RX_NUM_BLOCK_1             (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
7903 #define USB_COUNT1_RX_NUM_BLOCK_2             (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
7904 #define USB_COUNT1_RX_NUM_BLOCK_3             (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
7905 #define USB_COUNT1_RX_NUM_BLOCK_4             (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
7906 
7907 #define USB_COUNT1_RX_BLSIZE_Pos              (15U)
7908 #define USB_COUNT1_RX_BLSIZE_Msk              (0x1U << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */
7909 #define USB_COUNT1_RX_BLSIZE                  USB_COUNT1_RX_BLSIZE_Msk         /*!< BLock SIZE */
7910 
7911 /*****************  Bit definition for USB_COUNT2_RX register  ****************/
7912 #define USB_COUNT2_RX_COUNT2_RX_Pos           (0U)
7913 #define USB_COUNT2_RX_COUNT2_RX_Msk           (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */
7914 #define USB_COUNT2_RX_COUNT2_RX               USB_COUNT2_RX_COUNT2_RX_Msk      /*!< Reception Byte Count */
7915 
7916 #define USB_COUNT2_RX_NUM_BLOCK_Pos           (10U)
7917 #define USB_COUNT2_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
7918 #define USB_COUNT2_RX_NUM_BLOCK               USB_COUNT2_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
7919 #define USB_COUNT2_RX_NUM_BLOCK_0             (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
7920 #define USB_COUNT2_RX_NUM_BLOCK_1             (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
7921 #define USB_COUNT2_RX_NUM_BLOCK_2             (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
7922 #define USB_COUNT2_RX_NUM_BLOCK_3             (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
7923 #define USB_COUNT2_RX_NUM_BLOCK_4             (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
7924 
7925 #define USB_COUNT2_RX_BLSIZE_Pos              (15U)
7926 #define USB_COUNT2_RX_BLSIZE_Msk              (0x1U << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */
7927 #define USB_COUNT2_RX_BLSIZE                  USB_COUNT2_RX_BLSIZE_Msk         /*!< BLock SIZE */
7928 
7929 /*****************  Bit definition for USB_COUNT3_RX register  ****************/
7930 #define USB_COUNT3_RX_COUNT3_RX_Pos           (0U)
7931 #define USB_COUNT3_RX_COUNT3_RX_Msk           (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */
7932 #define USB_COUNT3_RX_COUNT3_RX               USB_COUNT3_RX_COUNT3_RX_Msk      /*!< Reception Byte Count */
7933 
7934 #define USB_COUNT3_RX_NUM_BLOCK_Pos           (10U)
7935 #define USB_COUNT3_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
7936 #define USB_COUNT3_RX_NUM_BLOCK               USB_COUNT3_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
7937 #define USB_COUNT3_RX_NUM_BLOCK_0             (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
7938 #define USB_COUNT3_RX_NUM_BLOCK_1             (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
7939 #define USB_COUNT3_RX_NUM_BLOCK_2             (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
7940 #define USB_COUNT3_RX_NUM_BLOCK_3             (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
7941 #define USB_COUNT3_RX_NUM_BLOCK_4             (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
7942 
7943 #define USB_COUNT3_RX_BLSIZE_Pos              (15U)
7944 #define USB_COUNT3_RX_BLSIZE_Msk              (0x1U << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */
7945 #define USB_COUNT3_RX_BLSIZE                  USB_COUNT3_RX_BLSIZE_Msk         /*!< BLock SIZE */
7946 
7947 /*****************  Bit definition for USB_COUNT4_RX register  ****************/
7948 #define USB_COUNT4_RX_COUNT4_RX_Pos           (0U)
7949 #define USB_COUNT4_RX_COUNT4_RX_Msk           (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */
7950 #define USB_COUNT4_RX_COUNT4_RX               USB_COUNT4_RX_COUNT4_RX_Msk      /*!< Reception Byte Count */
7951 
7952 #define USB_COUNT4_RX_NUM_BLOCK_Pos           (10U)
7953 #define USB_COUNT4_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
7954 #define USB_COUNT4_RX_NUM_BLOCK               USB_COUNT4_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
7955 #define USB_COUNT4_RX_NUM_BLOCK_0             (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
7956 #define USB_COUNT4_RX_NUM_BLOCK_1             (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
7957 #define USB_COUNT4_RX_NUM_BLOCK_2             (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
7958 #define USB_COUNT4_RX_NUM_BLOCK_3             (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
7959 #define USB_COUNT4_RX_NUM_BLOCK_4             (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
7960 
7961 #define USB_COUNT4_RX_BLSIZE_Pos              (15U)
7962 #define USB_COUNT4_RX_BLSIZE_Msk              (0x1U << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */
7963 #define USB_COUNT4_RX_BLSIZE                  USB_COUNT4_RX_BLSIZE_Msk         /*!< BLock SIZE */
7964 
7965 /*****************  Bit definition for USB_COUNT5_RX register  ****************/
7966 #define USB_COUNT5_RX_COUNT5_RX_Pos           (0U)
7967 #define USB_COUNT5_RX_COUNT5_RX_Msk           (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */
7968 #define USB_COUNT5_RX_COUNT5_RX               USB_COUNT5_RX_COUNT5_RX_Msk      /*!< Reception Byte Count */
7969 
7970 #define USB_COUNT5_RX_NUM_BLOCK_Pos           (10U)
7971 #define USB_COUNT5_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
7972 #define USB_COUNT5_RX_NUM_BLOCK               USB_COUNT5_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
7973 #define USB_COUNT5_RX_NUM_BLOCK_0             (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
7974 #define USB_COUNT5_RX_NUM_BLOCK_1             (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
7975 #define USB_COUNT5_RX_NUM_BLOCK_2             (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
7976 #define USB_COUNT5_RX_NUM_BLOCK_3             (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
7977 #define USB_COUNT5_RX_NUM_BLOCK_4             (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
7978 
7979 #define USB_COUNT5_RX_BLSIZE_Pos              (15U)
7980 #define USB_COUNT5_RX_BLSIZE_Msk              (0x1U << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */
7981 #define USB_COUNT5_RX_BLSIZE                  USB_COUNT5_RX_BLSIZE_Msk         /*!< BLock SIZE */
7982 
7983 /*****************  Bit definition for USB_COUNT6_RX register  ****************/
7984 #define USB_COUNT6_RX_COUNT6_RX_Pos           (0U)
7985 #define USB_COUNT6_RX_COUNT6_RX_Msk           (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */
7986 #define USB_COUNT6_RX_COUNT6_RX               USB_COUNT6_RX_COUNT6_RX_Msk      /*!< Reception Byte Count */
7987 
7988 #define USB_COUNT6_RX_NUM_BLOCK_Pos           (10U)
7989 #define USB_COUNT6_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
7990 #define USB_COUNT6_RX_NUM_BLOCK               USB_COUNT6_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
7991 #define USB_COUNT6_RX_NUM_BLOCK_0             (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
7992 #define USB_COUNT6_RX_NUM_BLOCK_1             (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
7993 #define USB_COUNT6_RX_NUM_BLOCK_2             (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
7994 #define USB_COUNT6_RX_NUM_BLOCK_3             (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
7995 #define USB_COUNT6_RX_NUM_BLOCK_4             (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
7996 
7997 #define USB_COUNT6_RX_BLSIZE_Pos              (15U)
7998 #define USB_COUNT6_RX_BLSIZE_Msk              (0x1U << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */
7999 #define USB_COUNT6_RX_BLSIZE                  USB_COUNT6_RX_BLSIZE_Msk         /*!< BLock SIZE */
8000 
8001 /*****************  Bit definition for USB_COUNT7_RX register  ****************/
8002 #define USB_COUNT7_RX_COUNT7_RX_Pos           (0U)
8003 #define USB_COUNT7_RX_COUNT7_RX_Msk           (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */
8004 #define USB_COUNT7_RX_COUNT7_RX               USB_COUNT7_RX_COUNT7_RX_Msk      /*!< Reception Byte Count */
8005 
8006 #define USB_COUNT7_RX_NUM_BLOCK_Pos           (10U)
8007 #define USB_COUNT7_RX_NUM_BLOCK_Msk           (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */
8008 #define USB_COUNT7_RX_NUM_BLOCK               USB_COUNT7_RX_NUM_BLOCK_Msk      /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
8009 #define USB_COUNT7_RX_NUM_BLOCK_0             (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */
8010 #define USB_COUNT7_RX_NUM_BLOCK_1             (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */
8011 #define USB_COUNT7_RX_NUM_BLOCK_2             (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */
8012 #define USB_COUNT7_RX_NUM_BLOCK_3             (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */
8013 #define USB_COUNT7_RX_NUM_BLOCK_4             (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */
8014 
8015 #define USB_COUNT7_RX_BLSIZE_Pos              (15U)
8016 #define USB_COUNT7_RX_BLSIZE_Msk              (0x1U << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */
8017 #define USB_COUNT7_RX_BLSIZE                  USB_COUNT7_RX_BLSIZE_Msk         /*!< BLock SIZE */
8018 
8019 /*----------------------------------------------------------------------------*/
8020 
8021 /****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
8022 #define USB_COUNT0_RX_0_COUNT0_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
8023 
8024 #define USB_COUNT0_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
8025 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
8026 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
8027 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
8028 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
8029 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
8030 
8031 #define USB_COUNT0_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
8032 
8033 /****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
8034 #define USB_COUNT0_RX_1_COUNT0_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
8035 
8036 #define USB_COUNT0_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
8037 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 1 */
8038 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
8039 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
8040 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
8041 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
8042 
8043 #define USB_COUNT0_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
8044 
8045 /****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
8046 #define USB_COUNT1_RX_0_COUNT1_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
8047 
8048 #define USB_COUNT1_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
8049 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
8050 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
8051 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
8052 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
8053 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
8054 
8055 #define USB_COUNT1_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
8056 
8057 /****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
8058 #define USB_COUNT1_RX_1_COUNT1_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
8059 
8060 #define USB_COUNT1_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
8061 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
8062 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
8063 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
8064 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
8065 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
8066 
8067 #define USB_COUNT1_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
8068 
8069 /****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
8070 #define USB_COUNT2_RX_0_COUNT2_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
8071 
8072 #define USB_COUNT2_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
8073 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
8074 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
8075 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
8076 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
8077 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
8078 
8079 #define USB_COUNT2_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
8080 
8081 /****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
8082 #define USB_COUNT2_RX_1_COUNT2_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
8083 
8084 #define USB_COUNT2_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
8085 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
8086 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
8087 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
8088 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
8089 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
8090 
8091 #define USB_COUNT2_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
8092 
8093 /****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
8094 #define USB_COUNT3_RX_0_COUNT3_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
8095 
8096 #define USB_COUNT3_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
8097 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
8098 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
8099 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
8100 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
8101 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
8102 
8103 #define USB_COUNT3_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
8104 
8105 /****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
8106 #define USB_COUNT3_RX_1_COUNT3_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
8107 
8108 #define USB_COUNT3_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
8109 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
8110 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
8111 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
8112 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
8113 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
8114 
8115 #define USB_COUNT3_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
8116 
8117 /****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
8118 #define USB_COUNT4_RX_0_COUNT4_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
8119 
8120 #define USB_COUNT4_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
8121 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
8122 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
8123 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
8124 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
8125 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
8126 
8127 #define USB_COUNT4_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
8128 
8129 /****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
8130 #define USB_COUNT4_RX_1_COUNT4_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
8131 
8132 #define USB_COUNT4_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
8133 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
8134 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
8135 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
8136 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
8137 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
8138 
8139 #define USB_COUNT4_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
8140 
8141 /****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
8142 #define USB_COUNT5_RX_0_COUNT5_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
8143 
8144 #define USB_COUNT5_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
8145 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
8146 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
8147 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
8148 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
8149 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
8150 
8151 #define USB_COUNT5_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
8152 
8153 /****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
8154 #define USB_COUNT5_RX_1_COUNT5_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
8155 
8156 #define USB_COUNT5_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
8157 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
8158 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
8159 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
8160 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
8161 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
8162 
8163 #define USB_COUNT5_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
8164 
8165 /***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
8166 #define USB_COUNT6_RX_0_COUNT6_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
8167 
8168 #define USB_COUNT6_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
8169 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
8170 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
8171 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
8172 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
8173 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
8174 
8175 #define USB_COUNT6_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
8176 
8177 /****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
8178 #define USB_COUNT6_RX_1_COUNT6_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
8179 
8180 #define USB_COUNT6_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
8181 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
8182 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
8183 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
8184 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
8185 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
8186 
8187 #define USB_COUNT6_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
8188 
8189 /***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
8190 #define USB_COUNT7_RX_0_COUNT7_RX_0           (0x000003FFU)                    /*!< Reception Byte Count (low) */
8191 
8192 #define USB_COUNT7_RX_0_NUM_BLOCK_0           (0x00007C00U)                    /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
8193 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0         (0x00000400U)                    /*!< Bit 0 */
8194 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1         (0x00000800U)                    /*!< Bit 1 */
8195 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2         (0x00001000U)                    /*!< Bit 2 */
8196 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3         (0x00002000U)                    /*!< Bit 3 */
8197 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4         (0x00004000U)                    /*!< Bit 4 */
8198 
8199 #define USB_COUNT7_RX_0_BLSIZE_0              (0x00008000U)                    /*!< BLock SIZE (low) */
8200 
8201 /***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
8202 #define USB_COUNT7_RX_1_COUNT7_RX_1           (0x03FF0000U)                    /*!< Reception Byte Count (high) */
8203 
8204 #define USB_COUNT7_RX_1_NUM_BLOCK_1           (0x7C000000U)                    /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
8205 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0         (0x04000000U)                    /*!< Bit 0 */
8206 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1         (0x08000000U)                    /*!< Bit 1 */
8207 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2         (0x10000000U)                    /*!< Bit 2 */
8208 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3         (0x20000000U)                    /*!< Bit 3 */
8209 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4         (0x40000000U)                    /*!< Bit 4 */
8210 
8211 #define USB_COUNT7_RX_1_BLSIZE_1              (0x80000000U)                    /*!< BLock SIZE (high) */
8212 
8213 /******************************************************************************/
8214 /*                                                                            */
8215 /*                         Window WATCHDOG (WWDG)                             */
8216 /*                                                                            */
8217 /******************************************************************************/
8218 
8219 /*******************  Bit definition for WWDG_CR register  ********************/
8220 #define WWDG_CR_T_Pos                       (0U)
8221 #define WWDG_CR_T_Msk                       (0x7FU << WWDG_CR_T_Pos)           /*!< 0x0000007F */
8222 #define WWDG_CR_T                           WWDG_CR_T_Msk                      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
8223 #define WWDG_CR_T_0                         (0x01U << WWDG_CR_T_Pos)           /*!< 0x00000001 */
8224 #define WWDG_CR_T_1                         (0x02U << WWDG_CR_T_Pos)           /*!< 0x00000002 */
8225 #define WWDG_CR_T_2                         (0x04U << WWDG_CR_T_Pos)           /*!< 0x00000004 */
8226 #define WWDG_CR_T_3                         (0x08U << WWDG_CR_T_Pos)           /*!< 0x00000008 */
8227 #define WWDG_CR_T_4                         (0x10U << WWDG_CR_T_Pos)           /*!< 0x00000010 */
8228 #define WWDG_CR_T_5                         (0x20U << WWDG_CR_T_Pos)           /*!< 0x00000020 */
8229 #define WWDG_CR_T_6                         (0x40U << WWDG_CR_T_Pos)           /*!< 0x00000040 */
8230 
8231 /* Legacy defines */
8232 #define  WWDG_CR_T0 WWDG_CR_T_0
8233 #define  WWDG_CR_T1 WWDG_CR_T_1
8234 #define  WWDG_CR_T2 WWDG_CR_T_2
8235 #define  WWDG_CR_T3 WWDG_CR_T_3
8236 #define  WWDG_CR_T4 WWDG_CR_T_4
8237 #define  WWDG_CR_T5 WWDG_CR_T_5
8238 #define  WWDG_CR_T6 WWDG_CR_T_6
8239 
8240 #define WWDG_CR_WDGA_Pos                    (7U)
8241 #define WWDG_CR_WDGA_Msk                    (0x1U << WWDG_CR_WDGA_Pos)         /*!< 0x00000080 */
8242 #define WWDG_CR_WDGA                        WWDG_CR_WDGA_Msk                   /*!< Activation bit */
8243 
8244 /*******************  Bit definition for WWDG_CFR register  *******************/
8245 #define WWDG_CFR_W_Pos                      (0U)
8246 #define WWDG_CFR_W_Msk                      (0x7FU << WWDG_CFR_W_Pos)          /*!< 0x0000007F */
8247 #define WWDG_CFR_W                          WWDG_CFR_W_Msk                     /*!< W[6:0] bits (7-bit window value) */
8248 #define WWDG_CFR_W_0                        (0x01U << WWDG_CFR_W_Pos)          /*!< 0x00000001 */
8249 #define WWDG_CFR_W_1                        (0x02U << WWDG_CFR_W_Pos)          /*!< 0x00000002 */
8250 #define WWDG_CFR_W_2                        (0x04U << WWDG_CFR_W_Pos)          /*!< 0x00000004 */
8251 #define WWDG_CFR_W_3                        (0x08U << WWDG_CFR_W_Pos)          /*!< 0x00000008 */
8252 #define WWDG_CFR_W_4                        (0x10U << WWDG_CFR_W_Pos)          /*!< 0x00000010 */
8253 #define WWDG_CFR_W_5                        (0x20U << WWDG_CFR_W_Pos)          /*!< 0x00000020 */
8254 #define WWDG_CFR_W_6                        (0x40U << WWDG_CFR_W_Pos)          /*!< 0x00000040 */
8255 
8256 /* Legacy defines */
8257 #define  WWDG_CFR_W0 WWDG_CFR_W_0
8258 #define  WWDG_CFR_W1 WWDG_CFR_W_1
8259 #define  WWDG_CFR_W2 WWDG_CFR_W_2
8260 #define  WWDG_CFR_W3 WWDG_CFR_W_3
8261 #define  WWDG_CFR_W4 WWDG_CFR_W_4
8262 #define  WWDG_CFR_W5 WWDG_CFR_W_5
8263 #define  WWDG_CFR_W6 WWDG_CFR_W_6
8264 
8265 #define WWDG_CFR_WDGTB_Pos                  (7U)
8266 #define WWDG_CFR_WDGTB_Msk                  (0x3U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000180 */
8267 #define WWDG_CFR_WDGTB                      WWDG_CFR_WDGTB_Msk                 /*!< WDGTB[1:0] bits (Timer Base) */
8268 #define WWDG_CFR_WDGTB_0                    (0x1U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000080 */
8269 #define WWDG_CFR_WDGTB_1                    (0x2U << WWDG_CFR_WDGTB_Pos)       /*!< 0x00000100 */
8270 
8271 /* Legacy defines */
8272 #define  WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
8273 #define  WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
8274 
8275 #define WWDG_CFR_EWI_Pos                    (9U)
8276 #define WWDG_CFR_EWI_Msk                    (0x1U << WWDG_CFR_EWI_Pos)         /*!< 0x00000200 */
8277 #define WWDG_CFR_EWI                        WWDG_CFR_EWI_Msk                   /*!< Early Wakeup Interrupt */
8278 
8279 /*******************  Bit definition for WWDG_SR register  ********************/
8280 #define WWDG_SR_EWIF_Pos                    (0U)
8281 #define WWDG_SR_EWIF_Msk                    (0x1U << WWDG_SR_EWIF_Pos)         /*!< 0x00000001 */
8282 #define WWDG_SR_EWIF                        WWDG_SR_EWIF_Msk                   /*!< Early Wakeup Interrupt Flag */
8283 
8284 /******************************************************************************/
8285 /*                                                                            */
8286 /*                        SystemTick (SysTick)                                */
8287 /*                                                                            */
8288 /******************************************************************************/
8289 
8290 /*****************  Bit definition for SysTick_CTRL register  *****************/
8291 #define SysTick_CTRL_ENABLE                 (0x00000001U)                      /*!< Counter enable */
8292 #define SysTick_CTRL_TICKINT                (0x00000002U)                      /*!< Counting down to 0 pends the SysTick handler */
8293 #define SysTick_CTRL_CLKSOURCE              (0x00000004U)                      /*!< Clock source */
8294 #define SysTick_CTRL_COUNTFLAG              (0x00010000U)                      /*!< Count Flag */
8295 
8296 /*****************  Bit definition for SysTick_LOAD register  *****************/
8297 #define SysTick_LOAD_RELOAD                 (0x00FFFFFFU)                      /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
8298 
8299 /*****************  Bit definition for SysTick_VAL register  ******************/
8300 #define SysTick_VAL_CURRENT                 (0x00FFFFFFU)                      /*!< Current value at the time the register is accessed */
8301 
8302 /*****************  Bit definition for SysTick_CALIB register  ****************/
8303 #define SysTick_CALIB_TENMS                 (0x00FFFFFFU)                      /*!< Reload value to use for 10ms timing */
8304 #define SysTick_CALIB_SKEW                  (0x40000000U)                      /*!< Calibration value is not exactly 10 ms */
8305 #define SysTick_CALIB_NOREF                 (0x80000000U)                      /*!< The reference clock is not provided */
8306 
8307 /******************************************************************************/
8308 /*                                                                            */
8309 /*               Nested Vectored Interrupt Controller (NVIC)                  */
8310 /*                                                                            */
8311 /******************************************************************************/
8312 
8313 /******************  Bit definition for NVIC_ISER register  *******************/
8314 #define NVIC_ISER_SETENA_Pos                (0U)
8315 #define NVIC_ISER_SETENA_Msk                (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos) /*!< 0xFFFFFFFF */
8316 #define NVIC_ISER_SETENA                    NVIC_ISER_SETENA_Msk               /*!< Interrupt set enable bits */
8317 #define NVIC_ISER_SETENA_0                  (0x00000001U << NVIC_ISER_SETENA_Pos) /*!< 0x00000001 */
8318 #define NVIC_ISER_SETENA_1                  (0x00000002U << NVIC_ISER_SETENA_Pos) /*!< 0x00000002 */
8319 #define NVIC_ISER_SETENA_2                  (0x00000004U << NVIC_ISER_SETENA_Pos) /*!< 0x00000004 */
8320 #define NVIC_ISER_SETENA_3                  (0x00000008U << NVIC_ISER_SETENA_Pos) /*!< 0x00000008 */
8321 #define NVIC_ISER_SETENA_4                  (0x00000010U << NVIC_ISER_SETENA_Pos) /*!< 0x00000010 */
8322 #define NVIC_ISER_SETENA_5                  (0x00000020U << NVIC_ISER_SETENA_Pos) /*!< 0x00000020 */
8323 #define NVIC_ISER_SETENA_6                  (0x00000040U << NVIC_ISER_SETENA_Pos) /*!< 0x00000040 */
8324 #define NVIC_ISER_SETENA_7                  (0x00000080U << NVIC_ISER_SETENA_Pos) /*!< 0x00000080 */
8325 #define NVIC_ISER_SETENA_8                  (0x00000100U << NVIC_ISER_SETENA_Pos) /*!< 0x00000100 */
8326 #define NVIC_ISER_SETENA_9                  (0x00000200U << NVIC_ISER_SETENA_Pos) /*!< 0x00000200 */
8327 #define NVIC_ISER_SETENA_10                 (0x00000400U << NVIC_ISER_SETENA_Pos) /*!< 0x00000400 */
8328 #define NVIC_ISER_SETENA_11                 (0x00000800U << NVIC_ISER_SETENA_Pos) /*!< 0x00000800 */
8329 #define NVIC_ISER_SETENA_12                 (0x00001000U << NVIC_ISER_SETENA_Pos) /*!< 0x00001000 */
8330 #define NVIC_ISER_SETENA_13                 (0x00002000U << NVIC_ISER_SETENA_Pos) /*!< 0x00002000 */
8331 #define NVIC_ISER_SETENA_14                 (0x00004000U << NVIC_ISER_SETENA_Pos) /*!< 0x00004000 */
8332 #define NVIC_ISER_SETENA_15                 (0x00008000U << NVIC_ISER_SETENA_Pos) /*!< 0x00008000 */
8333 #define NVIC_ISER_SETENA_16                 (0x00010000U << NVIC_ISER_SETENA_Pos) /*!< 0x00010000 */
8334 #define NVIC_ISER_SETENA_17                 (0x00020000U << NVIC_ISER_SETENA_Pos) /*!< 0x00020000 */
8335 #define NVIC_ISER_SETENA_18                 (0x00040000U << NVIC_ISER_SETENA_Pos) /*!< 0x00040000 */
8336 #define NVIC_ISER_SETENA_19                 (0x00080000U << NVIC_ISER_SETENA_Pos) /*!< 0x00080000 */
8337 #define NVIC_ISER_SETENA_20                 (0x00100000U << NVIC_ISER_SETENA_Pos) /*!< 0x00100000 */
8338 #define NVIC_ISER_SETENA_21                 (0x00200000U << NVIC_ISER_SETENA_Pos) /*!< 0x00200000 */
8339 #define NVIC_ISER_SETENA_22                 (0x00400000U << NVIC_ISER_SETENA_Pos) /*!< 0x00400000 */
8340 #define NVIC_ISER_SETENA_23                 (0x00800000U << NVIC_ISER_SETENA_Pos) /*!< 0x00800000 */
8341 #define NVIC_ISER_SETENA_24                 (0x01000000U << NVIC_ISER_SETENA_Pos) /*!< 0x01000000 */
8342 #define NVIC_ISER_SETENA_25                 (0x02000000U << NVIC_ISER_SETENA_Pos) /*!< 0x02000000 */
8343 #define NVIC_ISER_SETENA_26                 (0x04000000U << NVIC_ISER_SETENA_Pos) /*!< 0x04000000 */
8344 #define NVIC_ISER_SETENA_27                 (0x08000000U << NVIC_ISER_SETENA_Pos) /*!< 0x08000000 */
8345 #define NVIC_ISER_SETENA_28                 (0x10000000U << NVIC_ISER_SETENA_Pos) /*!< 0x10000000 */
8346 #define NVIC_ISER_SETENA_29                 (0x20000000U << NVIC_ISER_SETENA_Pos) /*!< 0x20000000 */
8347 #define NVIC_ISER_SETENA_30                 (0x40000000U << NVIC_ISER_SETENA_Pos) /*!< 0x40000000 */
8348 #define NVIC_ISER_SETENA_31                 (0x80000000U << NVIC_ISER_SETENA_Pos) /*!< 0x80000000 */
8349 
8350 /******************  Bit definition for NVIC_ICER register  *******************/
8351 #define NVIC_ICER_CLRENA_Pos                (0U)
8352 #define NVIC_ICER_CLRENA_Msk                (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos) /*!< 0xFFFFFFFF */
8353 #define NVIC_ICER_CLRENA                    NVIC_ICER_CLRENA_Msk               /*!< Interrupt clear-enable bits */
8354 #define NVIC_ICER_CLRENA_0                  (0x00000001U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000001 */
8355 #define NVIC_ICER_CLRENA_1                  (0x00000002U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000002 */
8356 #define NVIC_ICER_CLRENA_2                  (0x00000004U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000004 */
8357 #define NVIC_ICER_CLRENA_3                  (0x00000008U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000008 */
8358 #define NVIC_ICER_CLRENA_4                  (0x00000010U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000010 */
8359 #define NVIC_ICER_CLRENA_5                  (0x00000020U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000020 */
8360 #define NVIC_ICER_CLRENA_6                  (0x00000040U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000040 */
8361 #define NVIC_ICER_CLRENA_7                  (0x00000080U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000080 */
8362 #define NVIC_ICER_CLRENA_8                  (0x00000100U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000100 */
8363 #define NVIC_ICER_CLRENA_9                  (0x00000200U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000200 */
8364 #define NVIC_ICER_CLRENA_10                 (0x00000400U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000400 */
8365 #define NVIC_ICER_CLRENA_11                 (0x00000800U << NVIC_ICER_CLRENA_Pos) /*!< 0x00000800 */
8366 #define NVIC_ICER_CLRENA_12                 (0x00001000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00001000 */
8367 #define NVIC_ICER_CLRENA_13                 (0x00002000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00002000 */
8368 #define NVIC_ICER_CLRENA_14                 (0x00004000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00004000 */
8369 #define NVIC_ICER_CLRENA_15                 (0x00008000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00008000 */
8370 #define NVIC_ICER_CLRENA_16                 (0x00010000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00010000 */
8371 #define NVIC_ICER_CLRENA_17                 (0x00020000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00020000 */
8372 #define NVIC_ICER_CLRENA_18                 (0x00040000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00040000 */
8373 #define NVIC_ICER_CLRENA_19                 (0x00080000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00080000 */
8374 #define NVIC_ICER_CLRENA_20                 (0x00100000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00100000 */
8375 #define NVIC_ICER_CLRENA_21                 (0x00200000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00200000 */
8376 #define NVIC_ICER_CLRENA_22                 (0x00400000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00400000 */
8377 #define NVIC_ICER_CLRENA_23                 (0x00800000U << NVIC_ICER_CLRENA_Pos) /*!< 0x00800000 */
8378 #define NVIC_ICER_CLRENA_24                 (0x01000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x01000000 */
8379 #define NVIC_ICER_CLRENA_25                 (0x02000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x02000000 */
8380 #define NVIC_ICER_CLRENA_26                 (0x04000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x04000000 */
8381 #define NVIC_ICER_CLRENA_27                 (0x08000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x08000000 */
8382 #define NVIC_ICER_CLRENA_28                 (0x10000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x10000000 */
8383 #define NVIC_ICER_CLRENA_29                 (0x20000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x20000000 */
8384 #define NVIC_ICER_CLRENA_30                 (0x40000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x40000000 */
8385 #define NVIC_ICER_CLRENA_31                 (0x80000000U << NVIC_ICER_CLRENA_Pos) /*!< 0x80000000 */
8386 
8387 /******************  Bit definition for NVIC_ISPR register  *******************/
8388 #define NVIC_ISPR_SETPEND_Pos               (0U)
8389 #define NVIC_ISPR_SETPEND_Msk               (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos) /*!< 0xFFFFFFFF */
8390 #define NVIC_ISPR_SETPEND                   NVIC_ISPR_SETPEND_Msk              /*!< Interrupt set-pending bits */
8391 #define NVIC_ISPR_SETPEND_0                 (0x00000001U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000001 */
8392 #define NVIC_ISPR_SETPEND_1                 (0x00000002U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000002 */
8393 #define NVIC_ISPR_SETPEND_2                 (0x00000004U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000004 */
8394 #define NVIC_ISPR_SETPEND_3                 (0x00000008U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000008 */
8395 #define NVIC_ISPR_SETPEND_4                 (0x00000010U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000010 */
8396 #define NVIC_ISPR_SETPEND_5                 (0x00000020U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000020 */
8397 #define NVIC_ISPR_SETPEND_6                 (0x00000040U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000040 */
8398 #define NVIC_ISPR_SETPEND_7                 (0x00000080U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000080 */
8399 #define NVIC_ISPR_SETPEND_8                 (0x00000100U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000100 */
8400 #define NVIC_ISPR_SETPEND_9                 (0x00000200U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000200 */
8401 #define NVIC_ISPR_SETPEND_10                (0x00000400U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000400 */
8402 #define NVIC_ISPR_SETPEND_11                (0x00000800U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00000800 */
8403 #define NVIC_ISPR_SETPEND_12                (0x00001000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00001000 */
8404 #define NVIC_ISPR_SETPEND_13                (0x00002000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00002000 */
8405 #define NVIC_ISPR_SETPEND_14                (0x00004000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00004000 */
8406 #define NVIC_ISPR_SETPEND_15                (0x00008000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00008000 */
8407 #define NVIC_ISPR_SETPEND_16                (0x00010000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00010000 */
8408 #define NVIC_ISPR_SETPEND_17                (0x00020000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00020000 */
8409 #define NVIC_ISPR_SETPEND_18                (0x00040000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00040000 */
8410 #define NVIC_ISPR_SETPEND_19                (0x00080000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00080000 */
8411 #define NVIC_ISPR_SETPEND_20                (0x00100000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00100000 */
8412 #define NVIC_ISPR_SETPEND_21                (0x00200000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00200000 */
8413 #define NVIC_ISPR_SETPEND_22                (0x00400000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00400000 */
8414 #define NVIC_ISPR_SETPEND_23                (0x00800000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x00800000 */
8415 #define NVIC_ISPR_SETPEND_24                (0x01000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x01000000 */
8416 #define NVIC_ISPR_SETPEND_25                (0x02000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x02000000 */
8417 #define NVIC_ISPR_SETPEND_26                (0x04000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x04000000 */
8418 #define NVIC_ISPR_SETPEND_27                (0x08000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x08000000 */
8419 #define NVIC_ISPR_SETPEND_28                (0x10000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x10000000 */
8420 #define NVIC_ISPR_SETPEND_29                (0x20000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x20000000 */
8421 #define NVIC_ISPR_SETPEND_30                (0x40000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x40000000 */
8422 #define NVIC_ISPR_SETPEND_31                (0x80000000U << NVIC_ISPR_SETPEND_Pos) /*!< 0x80000000 */
8423 
8424 /******************  Bit definition for NVIC_ICPR register  *******************/
8425 #define NVIC_ICPR_CLRPEND_Pos               (0U)
8426 #define NVIC_ICPR_CLRPEND_Msk               (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos) /*!< 0xFFFFFFFF */
8427 #define NVIC_ICPR_CLRPEND                   NVIC_ICPR_CLRPEND_Msk              /*!< Interrupt clear-pending bits */
8428 #define NVIC_ICPR_CLRPEND_0                 (0x00000001U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000001 */
8429 #define NVIC_ICPR_CLRPEND_1                 (0x00000002U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000002 */
8430 #define NVIC_ICPR_CLRPEND_2                 (0x00000004U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000004 */
8431 #define NVIC_ICPR_CLRPEND_3                 (0x00000008U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000008 */
8432 #define NVIC_ICPR_CLRPEND_4                 (0x00000010U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000010 */
8433 #define NVIC_ICPR_CLRPEND_5                 (0x00000020U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000020 */
8434 #define NVIC_ICPR_CLRPEND_6                 (0x00000040U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000040 */
8435 #define NVIC_ICPR_CLRPEND_7                 (0x00000080U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000080 */
8436 #define NVIC_ICPR_CLRPEND_8                 (0x00000100U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000100 */
8437 #define NVIC_ICPR_CLRPEND_9                 (0x00000200U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000200 */
8438 #define NVIC_ICPR_CLRPEND_10                (0x00000400U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000400 */
8439 #define NVIC_ICPR_CLRPEND_11                (0x00000800U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00000800 */
8440 #define NVIC_ICPR_CLRPEND_12                (0x00001000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00001000 */
8441 #define NVIC_ICPR_CLRPEND_13                (0x00002000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00002000 */
8442 #define NVIC_ICPR_CLRPEND_14                (0x00004000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00004000 */
8443 #define NVIC_ICPR_CLRPEND_15                (0x00008000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00008000 */
8444 #define NVIC_ICPR_CLRPEND_16                (0x00010000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00010000 */
8445 #define NVIC_ICPR_CLRPEND_17                (0x00020000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00020000 */
8446 #define NVIC_ICPR_CLRPEND_18                (0x00040000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00040000 */
8447 #define NVIC_ICPR_CLRPEND_19                (0x00080000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00080000 */
8448 #define NVIC_ICPR_CLRPEND_20                (0x00100000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00100000 */
8449 #define NVIC_ICPR_CLRPEND_21                (0x00200000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00200000 */
8450 #define NVIC_ICPR_CLRPEND_22                (0x00400000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00400000 */
8451 #define NVIC_ICPR_CLRPEND_23                (0x00800000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x00800000 */
8452 #define NVIC_ICPR_CLRPEND_24                (0x01000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x01000000 */
8453 #define NVIC_ICPR_CLRPEND_25                (0x02000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x02000000 */
8454 #define NVIC_ICPR_CLRPEND_26                (0x04000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x04000000 */
8455 #define NVIC_ICPR_CLRPEND_27                (0x08000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x08000000 */
8456 #define NVIC_ICPR_CLRPEND_28                (0x10000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x10000000 */
8457 #define NVIC_ICPR_CLRPEND_29                (0x20000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x20000000 */
8458 #define NVIC_ICPR_CLRPEND_30                (0x40000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x40000000 */
8459 #define NVIC_ICPR_CLRPEND_31                (0x80000000U << NVIC_ICPR_CLRPEND_Pos) /*!< 0x80000000 */
8460 
8461 /******************  Bit definition for NVIC_IABR register  *******************/
8462 #define NVIC_IABR_ACTIVE_Pos                (0U)
8463 #define NVIC_IABR_ACTIVE_Msk                (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos) /*!< 0xFFFFFFFF */
8464 #define NVIC_IABR_ACTIVE                    NVIC_IABR_ACTIVE_Msk               /*!< Interrupt active flags */
8465 #define NVIC_IABR_ACTIVE_0                  (0x00000001U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000001 */
8466 #define NVIC_IABR_ACTIVE_1                  (0x00000002U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000002 */
8467 #define NVIC_IABR_ACTIVE_2                  (0x00000004U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000004 */
8468 #define NVIC_IABR_ACTIVE_3                  (0x00000008U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000008 */
8469 #define NVIC_IABR_ACTIVE_4                  (0x00000010U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000010 */
8470 #define NVIC_IABR_ACTIVE_5                  (0x00000020U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000020 */
8471 #define NVIC_IABR_ACTIVE_6                  (0x00000040U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000040 */
8472 #define NVIC_IABR_ACTIVE_7                  (0x00000080U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000080 */
8473 #define NVIC_IABR_ACTIVE_8                  (0x00000100U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000100 */
8474 #define NVIC_IABR_ACTIVE_9                  (0x00000200U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000200 */
8475 #define NVIC_IABR_ACTIVE_10                 (0x00000400U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000400 */
8476 #define NVIC_IABR_ACTIVE_11                 (0x00000800U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00000800 */
8477 #define NVIC_IABR_ACTIVE_12                 (0x00001000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00001000 */
8478 #define NVIC_IABR_ACTIVE_13                 (0x00002000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00002000 */
8479 #define NVIC_IABR_ACTIVE_14                 (0x00004000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00004000 */
8480 #define NVIC_IABR_ACTIVE_15                 (0x00008000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00008000 */
8481 #define NVIC_IABR_ACTIVE_16                 (0x00010000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00010000 */
8482 #define NVIC_IABR_ACTIVE_17                 (0x00020000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00020000 */
8483 #define NVIC_IABR_ACTIVE_18                 (0x00040000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00040000 */
8484 #define NVIC_IABR_ACTIVE_19                 (0x00080000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00080000 */
8485 #define NVIC_IABR_ACTIVE_20                 (0x00100000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00100000 */
8486 #define NVIC_IABR_ACTIVE_21                 (0x00200000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00200000 */
8487 #define NVIC_IABR_ACTIVE_22                 (0x00400000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00400000 */
8488 #define NVIC_IABR_ACTIVE_23                 (0x00800000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x00800000 */
8489 #define NVIC_IABR_ACTIVE_24                 (0x01000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x01000000 */
8490 #define NVIC_IABR_ACTIVE_25                 (0x02000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x02000000 */
8491 #define NVIC_IABR_ACTIVE_26                 (0x04000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x04000000 */
8492 #define NVIC_IABR_ACTIVE_27                 (0x08000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x08000000 */
8493 #define NVIC_IABR_ACTIVE_28                 (0x10000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x10000000 */
8494 #define NVIC_IABR_ACTIVE_29                 (0x20000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x20000000 */
8495 #define NVIC_IABR_ACTIVE_30                 (0x40000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x40000000 */
8496 #define NVIC_IABR_ACTIVE_31                 (0x80000000U << NVIC_IABR_ACTIVE_Pos) /*!< 0x80000000 */
8497 
8498 /******************  Bit definition for NVIC_PRI0 register  *******************/
8499 #define NVIC_IPR0_PRI_0                     (0x000000FFU)                      /*!< Priority of interrupt 0 */
8500 #define NVIC_IPR0_PRI_1                     (0x0000FF00U)                      /*!< Priority of interrupt 1 */
8501 #define NVIC_IPR0_PRI_2                     (0x00FF0000U)                      /*!< Priority of interrupt 2 */
8502 #define NVIC_IPR0_PRI_3                     (0xFF000000U)                      /*!< Priority of interrupt 3 */
8503 
8504 /******************  Bit definition for NVIC_PRI1 register  *******************/
8505 #define NVIC_IPR1_PRI_4                     (0x000000FFU)                      /*!< Priority of interrupt 4 */
8506 #define NVIC_IPR1_PRI_5                     (0x0000FF00U)                      /*!< Priority of interrupt 5 */
8507 #define NVIC_IPR1_PRI_6                     (0x00FF0000U)                      /*!< Priority of interrupt 6 */
8508 #define NVIC_IPR1_PRI_7                     (0xFF000000U)                      /*!< Priority of interrupt 7 */
8509 
8510 /******************  Bit definition for NVIC_PRI2 register  *******************/
8511 #define NVIC_IPR2_PRI_8                     (0x000000FFU)                      /*!< Priority of interrupt 8 */
8512 #define NVIC_IPR2_PRI_9                     (0x0000FF00U)                      /*!< Priority of interrupt 9 */
8513 #define NVIC_IPR2_PRI_10                    (0x00FF0000U)                      /*!< Priority of interrupt 10 */
8514 #define NVIC_IPR2_PRI_11                    (0xFF000000U)                      /*!< Priority of interrupt 11 */
8515 
8516 /******************  Bit definition for NVIC_PRI3 register  *******************/
8517 #define NVIC_IPR3_PRI_12                    (0x000000FFU)                      /*!< Priority of interrupt 12 */
8518 #define NVIC_IPR3_PRI_13                    (0x0000FF00U)                      /*!< Priority of interrupt 13 */
8519 #define NVIC_IPR3_PRI_14                    (0x00FF0000U)                      /*!< Priority of interrupt 14 */
8520 #define NVIC_IPR3_PRI_15                    (0xFF000000U)                      /*!< Priority of interrupt 15 */
8521 
8522 /******************  Bit definition for NVIC_PRI4 register  *******************/
8523 #define NVIC_IPR4_PRI_16                    (0x000000FFU)                      /*!< Priority of interrupt 16 */
8524 #define NVIC_IPR4_PRI_17                    (0x0000FF00U)                      /*!< Priority of interrupt 17 */
8525 #define NVIC_IPR4_PRI_18                    (0x00FF0000U)                      /*!< Priority of interrupt 18 */
8526 #define NVIC_IPR4_PRI_19                    (0xFF000000U)                      /*!< Priority of interrupt 19 */
8527 
8528 /******************  Bit definition for NVIC_PRI5 register  *******************/
8529 #define NVIC_IPR5_PRI_20                    (0x000000FFU)                      /*!< Priority of interrupt 20 */
8530 #define NVIC_IPR5_PRI_21                    (0x0000FF00U)                      /*!< Priority of interrupt 21 */
8531 #define NVIC_IPR5_PRI_22                    (0x00FF0000U)                      /*!< Priority of interrupt 22 */
8532 #define NVIC_IPR5_PRI_23                    (0xFF000000U)                      /*!< Priority of interrupt 23 */
8533 
8534 /******************  Bit definition for NVIC_PRI6 register  *******************/
8535 #define NVIC_IPR6_PRI_24                    (0x000000FFU)                      /*!< Priority of interrupt 24 */
8536 #define NVIC_IPR6_PRI_25                    (0x0000FF00U)                      /*!< Priority of interrupt 25 */
8537 #define NVIC_IPR6_PRI_26                    (0x00FF0000U)                      /*!< Priority of interrupt 26 */
8538 #define NVIC_IPR6_PRI_27                    (0xFF000000U)                      /*!< Priority of interrupt 27 */
8539 
8540 /******************  Bit definition for NVIC_PRI7 register  *******************/
8541 #define NVIC_IPR7_PRI_28                    (0x000000FFU)                      /*!< Priority of interrupt 28 */
8542 #define NVIC_IPR7_PRI_29                    (0x0000FF00U)                      /*!< Priority of interrupt 29 */
8543 #define NVIC_IPR7_PRI_30                    (0x00FF0000U)                      /*!< Priority of interrupt 30 */
8544 #define NVIC_IPR7_PRI_31                    (0xFF000000U)                      /*!< Priority of interrupt 31 */
8545 
8546 /******************  Bit definition for SCB_CPUID register  *******************/
8547 #define SCB_CPUID_REVISION                  (0x0000000FU)                      /*!< Implementation defined revision number */
8548 #define SCB_CPUID_PARTNO                    (0x0000FFF0U)                      /*!< Number of processor within serie */
8549 #define SCB_CPUID_Constant                  (0x000F0000U)                      /*!< Reads as 0x0F */
8550 #define SCB_CPUID_VARIANT                   (0x00F00000U)                      /*!< Implementation defined variant number */
8551 #define SCB_CPUID_IMPLEMENTER               (0xFF000000U)                      /*!< Implementer code. ARM is 0x41 */
8552 
8553 /*******************  Bit definition for SCB_ICSR register  *******************/
8554 #define SCB_ICSR_VECTACTIVE                 (0x000001FFU)                      /*!< Active ISR number field */
8555 #define SCB_ICSR_RETTOBASE                  (0x00000800U)                      /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
8556 #define SCB_ICSR_VECTPENDING                (0x003FF000U)                      /*!< Pending ISR number field */
8557 #define SCB_ICSR_ISRPENDING                 (0x00400000U)                      /*!< Interrupt pending flag */
8558 #define SCB_ICSR_ISRPREEMPT                 (0x00800000U)                      /*!< It indicates that a pending interrupt becomes active in the next running cycle */
8559 #define SCB_ICSR_PENDSTCLR                  (0x02000000U)                      /*!< Clear pending SysTick bit */
8560 #define SCB_ICSR_PENDSTSET                  (0x04000000U)                      /*!< Set pending SysTick bit */
8561 #define SCB_ICSR_PENDSVCLR                  (0x08000000U)                      /*!< Clear pending pendSV bit */
8562 #define SCB_ICSR_PENDSVSET                  (0x10000000U)                      /*!< Set pending pendSV bit */
8563 #define SCB_ICSR_NMIPENDSET                 (0x80000000U)                      /*!< Set pending NMI bit */
8564 
8565 /*******************  Bit definition for SCB_VTOR register  *******************/
8566 #define SCB_VTOR_TBLOFF                     (0x1FFFFF80U)                      /*!< Vector table base offset field */
8567 #define SCB_VTOR_TBLBASE                    (0x20000000U)                      /*!< Table base in code(0) or RAM(1) */
8568 
8569 /*!<*****************  Bit definition for SCB_AIRCR register  *******************/
8570 #define SCB_AIRCR_VECTRESET                 (0x00000001U)                      /*!< System Reset bit */
8571 #define SCB_AIRCR_VECTCLRACTIVE             (0x00000002U)                      /*!< Clear active vector bit */
8572 #define SCB_AIRCR_SYSRESETREQ               (0x00000004U)                      /*!< Requests chip control logic to generate a reset */
8573 
8574 #define SCB_AIRCR_PRIGROUP                  (0x00000700U)                      /*!< PRIGROUP[2:0] bits (Priority group) */
8575 #define SCB_AIRCR_PRIGROUP_0                (0x00000100U)                      /*!< Bit 0 */
8576 #define SCB_AIRCR_PRIGROUP_1                (0x00000200U)                      /*!< Bit 1 */
8577 #define SCB_AIRCR_PRIGROUP_2                (0x00000400U)                      /*!< Bit 2  */
8578 
8579 /* prority group configuration */
8580 #define SCB_AIRCR_PRIGROUP0                 (0x00000000U)                      /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
8581 #define SCB_AIRCR_PRIGROUP1                 (0x00000100U)                      /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
8582 #define SCB_AIRCR_PRIGROUP2                 (0x00000200U)                      /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
8583 #define SCB_AIRCR_PRIGROUP3                 (0x00000300U)                      /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
8584 #define SCB_AIRCR_PRIGROUP4                 (0x00000400U)                      /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
8585 #define SCB_AIRCR_PRIGROUP5                 (0x00000500U)                      /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
8586 #define SCB_AIRCR_PRIGROUP6                 (0x00000600U)                      /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
8587 #define SCB_AIRCR_PRIGROUP7                 (0x00000700U)                      /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
8588 
8589 #define SCB_AIRCR_ENDIANESS                 (0x00008000U)                      /*!< Data endianness bit */
8590 #define SCB_AIRCR_VECTKEY                   (0xFFFF0000U)                      /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
8591 
8592 /*******************  Bit definition for SCB_SCR register  ********************/
8593 #define SCB_SCR_SLEEPONEXIT                 (0x00000002U)                      /*!< Sleep on exit bit */
8594 #define SCB_SCR_SLEEPDEEP                   (0x00000004U)                      /*!< Sleep deep bit */
8595 #define SCB_SCR_SEVONPEND                   (0x00000010U)                      /*!< Wake up from WFE */
8596 
8597 /********************  Bit definition for SCB_CCR register  *******************/
8598 #define SCB_CCR_NONBASETHRDENA              (0x00000001U)                      /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
8599 #define SCB_CCR_USERSETMPEND                (0x00000002U)                      /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
8600 #define SCB_CCR_UNALIGN_TRP                 (0x00000008U)                      /*!< Trap for unaligned access */
8601 #define SCB_CCR_DIV_0_TRP                   (0x00000010U)                      /*!< Trap on Divide by 0 */
8602 #define SCB_CCR_BFHFNMIGN                   (0x00000100U)                      /*!< Handlers running at priority -1 and -2 */
8603 #define SCB_CCR_STKALIGN                    (0x00000200U)                      /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
8604 
8605 /*******************  Bit definition for SCB_SHPR register ********************/
8606 #define SCB_SHPR_PRI_N_Pos                  (0U)
8607 #define SCB_SHPR_PRI_N_Msk                  (0xFFU << SCB_SHPR_PRI_N_Pos)      /*!< 0x000000FF */
8608 #define SCB_SHPR_PRI_N                      SCB_SHPR_PRI_N_Msk                 /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
8609 #define SCB_SHPR_PRI_N1_Pos                 (8U)
8610 #define SCB_SHPR_PRI_N1_Msk                 (0xFFU << SCB_SHPR_PRI_N1_Pos)     /*!< 0x0000FF00 */
8611 #define SCB_SHPR_PRI_N1                     SCB_SHPR_PRI_N1_Msk                /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
8612 #define SCB_SHPR_PRI_N2_Pos                 (16U)
8613 #define SCB_SHPR_PRI_N2_Msk                 (0xFFU << SCB_SHPR_PRI_N2_Pos)     /*!< 0x00FF0000 */
8614 #define SCB_SHPR_PRI_N2                     SCB_SHPR_PRI_N2_Msk                /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
8615 #define SCB_SHPR_PRI_N3_Pos                 (24U)
8616 #define SCB_SHPR_PRI_N3_Msk                 (0xFFU << SCB_SHPR_PRI_N3_Pos)     /*!< 0xFF000000 */
8617 #define SCB_SHPR_PRI_N3                     SCB_SHPR_PRI_N3_Msk                /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
8618 
8619 /******************  Bit definition for SCB_SHCSR register  *******************/
8620 #define SCB_SHCSR_MEMFAULTACT               (0x00000001U)                      /*!< MemManage is active */
8621 #define SCB_SHCSR_BUSFAULTACT               (0x00000002U)                      /*!< BusFault is active */
8622 #define SCB_SHCSR_USGFAULTACT               (0x00000008U)                      /*!< UsageFault is active */
8623 #define SCB_SHCSR_SVCALLACT                 (0x00000080U)                      /*!< SVCall is active */
8624 #define SCB_SHCSR_MONITORACT                (0x00000100U)                      /*!< Monitor is active */
8625 #define SCB_SHCSR_PENDSVACT                 (0x00000400U)                      /*!< PendSV is active */
8626 #define SCB_SHCSR_SYSTICKACT                (0x00000800U)                      /*!< SysTick is active */
8627 #define SCB_SHCSR_USGFAULTPENDED            (0x00001000U)                      /*!< Usage Fault is pended */
8628 #define SCB_SHCSR_MEMFAULTPENDED            (0x00002000U)                      /*!< MemManage is pended */
8629 #define SCB_SHCSR_BUSFAULTPENDED            (0x00004000U)                      /*!< Bus Fault is pended */
8630 #define SCB_SHCSR_SVCALLPENDED              (0x00008000U)                      /*!< SVCall is pended */
8631 #define SCB_SHCSR_MEMFAULTENA               (0x00010000U)                      /*!< MemManage enable */
8632 #define SCB_SHCSR_BUSFAULTENA               (0x00020000U)                      /*!< Bus Fault enable */
8633 #define SCB_SHCSR_USGFAULTENA               (0x00040000U)                      /*!< UsageFault enable */
8634 
8635 /*******************  Bit definition for SCB_CFSR register  *******************/
8636 /*!< MFSR */
8637 #define SCB_CFSR_IACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 0U)    /*!< SCB CFSR (MMFSR): IACCVIOL Position */
8638 #define SCB_CFSR_IACCVIOL_Msk              (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)  /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
8639 #define SCB_CFSR_IACCVIOL                   SCB_CFSR_IACCVIOL_Msk              /*!< Instruction access violation */
8640 #define SCB_CFSR_DACCVIOL_Pos              (SCB_SHCSR_MEMFAULTACT_Pos + 1U)    /*!< SCB CFSR (MMFSR): DACCVIOL Position */
8641 #define SCB_CFSR_DACCVIOL_Msk              (1UL << SCB_CFSR_DACCVIOL_Pos)      /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
8642 #define SCB_CFSR_DACCVIOL                   SCB_CFSR_DACCVIOL_Msk              /*!< Data access violation */
8643 #define SCB_CFSR_MUNSTKERR_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 3U)    /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
8644 #define SCB_CFSR_MUNSTKERR_Msk             (1UL << SCB_CFSR_MUNSTKERR_Pos)     /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
8645 #define SCB_CFSR_MUNSTKERR                  SCB_CFSR_MUNSTKERR_Msk             /*!< Unstacking error */
8646 #define SCB_CFSR_MSTKERR_Pos               (SCB_SHCSR_MEMFAULTACT_Pos + 4U)    /*!< SCB CFSR (MMFSR): MSTKERR Position */
8647 #define SCB_CFSR_MSTKERR_Msk               (1UL << SCB_CFSR_MSTKERR_Pos)       /*!< SCB CFSR (MMFSR): MSTKERR Mask */
8648 #define SCB_CFSR_MSTKERR                    SCB_CFSR_MSTKERR_Msk               /*!< Stacking error */
8649 #define SCB_CFSR_MMARVALID_Pos             (SCB_SHCSR_MEMFAULTACT_Pos + 7U)    /*!< SCB CFSR (MMFSR): MMARVALID Position */
8650 #define SCB_CFSR_MMARVALID_Msk             (1UL << SCB_CFSR_MMARVALID_Pos)     /*!< SCB CFSR (MMFSR): MMARVALID Mask */
8651 #define SCB_CFSR_MMARVALID                  SCB_CFSR_MMARVALID_Msk             /*!< Memory Manage Address Register address valid flag */
8652 /*!< BFSR */
8653 #define SCB_CFSR_IBUSERR_Pos              (SCB_CFSR_BUSFAULTSR_Pos + 0U)       /*!< SCB CFSR (BFSR): IBUSERR Position */
8654 #define SCB_CFSR_IBUSERR_Msk              (1UL << SCB_CFSR_IBUSERR_Pos)        /*!< SCB CFSR (BFSR): IBUSERR Mask */
8655 #define SCB_CFSR_IBUSERR                    SCB_CFSR_IBUSERR_Msk               /*!< Instruction bus error flag */
8656 #define SCB_CFSR_PRECISERR_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 1U)       /*!< SCB CFSR (BFSR): PRECISERR Position */
8657 #define SCB_CFSR_PRECISERR_Msk            (1UL << SCB_CFSR_PRECISERR_Pos)      /*!< SCB CFSR (BFSR): PRECISERR Mask */
8658 #define SCB_CFSR_PRECISERR                  SCB_CFSR_PRECISERR_Msk             /*!< Precise data bus error */
8659 #define SCB_CFSR_IMPRECISERR_Pos          (SCB_CFSR_BUSFAULTSR_Pos + 2U)       /*!< SCB CFSR (BFSR): IMPRECISERR Position */
8660 #define SCB_CFSR_IMPRECISERR_Msk          (1UL << SCB_CFSR_IMPRECISERR_Pos)    /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
8661 #define SCB_CFSR_IMPRECISERR                SCB_CFSR_IMPRECISERR_Msk           /*!< Imprecise data bus error */
8662 #define SCB_CFSR_UNSTKERR_Pos             (SCB_CFSR_BUSFAULTSR_Pos + 3U)       /*!< SCB CFSR (BFSR): UNSTKERR Position */
8663 #define SCB_CFSR_UNSTKERR_Msk             (1UL << SCB_CFSR_UNSTKERR_Pos)       /*!< SCB CFSR (BFSR): UNSTKERR Mask */
8664 #define SCB_CFSR_UNSTKERR                   SCB_CFSR_UNSTKERR_Msk              /*!< Unstacking error */
8665 #define SCB_CFSR_STKERR_Pos               (SCB_CFSR_BUSFAULTSR_Pos + 4U)       /*!< SCB CFSR (BFSR): STKERR Position */
8666 #define SCB_CFSR_STKERR_Msk               (1UL << SCB_CFSR_STKERR_Pos)         /*!< SCB CFSR (BFSR): STKERR Mask */
8667 #define SCB_CFSR_STKERR                     SCB_CFSR_STKERR_Msk                /*!< Stacking error */
8668 #define SCB_CFSR_BFARVALID_Pos            (SCB_CFSR_BUSFAULTSR_Pos + 7U)       /*!< SCB CFSR (BFSR): BFARVALID Position */
8669 #define SCB_CFSR_BFARVALID_Msk            (1UL << SCB_CFSR_BFARVALID_Pos)      /*!< SCB CFSR (BFSR): BFARVALID Mask */
8670 #define SCB_CFSR_BFARVALID                  SCB_CFSR_BFARVALID_Msk             /*!< Bus Fault Address Register address valid flag */
8671 /*!< UFSR */
8672 #define SCB_CFSR_UNDEFINSTR_Pos           (SCB_CFSR_USGFAULTSR_Pos + 0U)       /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
8673 #define SCB_CFSR_UNDEFINSTR_Msk           (1UL << SCB_CFSR_UNDEFINSTR_Pos)     /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
8674 #define SCB_CFSR_UNDEFINSTR                 SCB_CFSR_UNDEFINSTR_Msk            /*!< The processor attempt to excecute an undefined instruction */
8675 #define SCB_CFSR_INVSTATE_Pos             (SCB_CFSR_USGFAULTSR_Pos + 1U)       /*!< SCB CFSR (UFSR): INVSTATE Position */
8676 #define SCB_CFSR_INVSTATE_Msk             (1UL << SCB_CFSR_INVSTATE_Pos)       /*!< SCB CFSR (UFSR): INVSTATE Mask */
8677 #define SCB_CFSR_INVSTATE                   SCB_CFSR_INVSTATE_Msk              /*!< Invalid combination of EPSR and instruction */
8678 #define SCB_CFSR_INVPC_Pos                (SCB_CFSR_USGFAULTSR_Pos + 2U)       /*!< SCB CFSR (UFSR): INVPC Position */
8679 #define SCB_CFSR_INVPC_Msk                (1UL << SCB_CFSR_INVPC_Pos)          /*!< SCB CFSR (UFSR): INVPC Mask */
8680 #define SCB_CFSR_INVPC                      SCB_CFSR_INVPC_Msk                 /*!< Attempt to load EXC_RETURN into pc illegally */
8681 #define SCB_CFSR_NOCP_Pos                 (SCB_CFSR_USGFAULTSR_Pos + 3U)       /*!< SCB CFSR (UFSR): NOCP Position */
8682 #define SCB_CFSR_NOCP_Msk                 (1UL << SCB_CFSR_NOCP_Pos)           /*!< SCB CFSR (UFSR): NOCP Mask */
8683 #define SCB_CFSR_NOCP                       SCB_CFSR_NOCP_Msk                  /*!< Attempt to use a coprocessor instruction */
8684 #define SCB_CFSR_UNALIGNED_Pos            (SCB_CFSR_USGFAULTSR_Pos + 8U)       /*!< SCB CFSR (UFSR): UNALIGNED Position */
8685 #define SCB_CFSR_UNALIGNED_Msk            (1UL << SCB_CFSR_UNALIGNED_Pos)      /*!< SCB CFSR (UFSR): UNALIGNED Mask */
8686 #define SCB_CFSR_UNALIGNED                  SCB_CFSR_UNALIGNED_Msk             /*!< Fault occurs when there is an attempt to make an unaligned memory access */
8687 #define SCB_CFSR_DIVBYZERO_Pos            (SCB_CFSR_USGFAULTSR_Pos + 9U)       /*!< SCB CFSR (UFSR): DIVBYZERO Position */
8688 #define SCB_CFSR_DIVBYZERO_Msk            (1UL << SCB_CFSR_DIVBYZERO_Pos)      /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
8689 #define SCB_CFSR_DIVBYZERO                  SCB_CFSR_DIVBYZERO_Msk             /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
8690 
8691 /*******************  Bit definition for SCB_HFSR register  *******************/
8692 #define SCB_HFSR_VECTTBL                    (0x00000002U)                      /*!< Fault occures because of vector table read on exception processing */
8693 #define SCB_HFSR_FORCED                     (0x40000000U)                      /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
8694 #define SCB_HFSR_DEBUGEVT                   (0x80000000U)                      /*!< Fault related to debug */
8695 
8696 /*******************  Bit definition for SCB_DFSR register  *******************/
8697 #define SCB_DFSR_HALTED                     (0x00000001U)                      /*!< Halt request flag */
8698 #define SCB_DFSR_BKPT                       (0x00000002U)                      /*!< BKPT flag */
8699 #define SCB_DFSR_DWTTRAP                    (0x00000004U)                      /*!< Data Watchpoint and Trace (DWT) flag */
8700 #define SCB_DFSR_VCATCH                     (0x00000008U)                      /*!< Vector catch flag */
8701 #define SCB_DFSR_EXTERNAL                   (0x00000010U)                      /*!< External debug request flag */
8702 
8703 /*******************  Bit definition for SCB_MMFAR register  ******************/
8704 #define SCB_MMFAR_ADDRESS_Pos               (0U)
8705 #define SCB_MMFAR_ADDRESS_Msk               (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
8706 #define SCB_MMFAR_ADDRESS                   SCB_MMFAR_ADDRESS_Msk              /*!< Mem Manage fault address field */
8707 
8708 /*******************  Bit definition for SCB_BFAR register  *******************/
8709 #define SCB_BFAR_ADDRESS_Pos                (0U)
8710 #define SCB_BFAR_ADDRESS_Msk                (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
8711 #define SCB_BFAR_ADDRESS                    SCB_BFAR_ADDRESS_Msk               /*!< Bus fault address field */
8712 
8713 /*******************  Bit definition for SCB_afsr register  *******************/
8714 #define SCB_AFSR_IMPDEF_Pos                 (0U)
8715 #define SCB_AFSR_IMPDEF_Msk                 (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos) /*!< 0xFFFFFFFF */
8716 #define SCB_AFSR_IMPDEF                     SCB_AFSR_IMPDEF_Msk                /*!< Implementation defined */
8717 /**
8718   * @}
8719   */
8720 
8721  /**
8722   * @}
8723   */
8724 /** @addtogroup Exported_macro
8725   * @{
8726   */
8727 
8728 /****************************** ADC Instances *********************************/
8729 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
8730 
8731 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC1_COMMON)
8732 
8733 /******************************** COMP Instances ******************************/
8734 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
8735                                         ((INSTANCE) == COMP2))
8736 
8737 #define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
8738 
8739 /****************************** CRC Instances *********************************/
8740 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
8741 
8742 /****************************** DAC Instances *********************************/
8743 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
8744 
8745 /****************************** DMA Instances *********************************/
8746 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
8747                                        ((INSTANCE) == DMA1_Channel2) || \
8748                                        ((INSTANCE) == DMA1_Channel3) || \
8749                                        ((INSTANCE) == DMA1_Channel4) || \
8750                                        ((INSTANCE) == DMA1_Channel5) || \
8751                                        ((INSTANCE) == DMA1_Channel6) || \
8752                                        ((INSTANCE) == DMA1_Channel7) || \
8753                                        ((INSTANCE) == DMA2_Channel1) || \
8754                                        ((INSTANCE) == DMA2_Channel2) || \
8755                                        ((INSTANCE) == DMA2_Channel3) || \
8756                                        ((INSTANCE) == DMA2_Channel4) || \
8757                                        ((INSTANCE) == DMA2_Channel5))
8758 
8759 /******************************* GPIO Instances *******************************/
8760 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
8761                                         ((INSTANCE) == GPIOB) || \
8762                                         ((INSTANCE) == GPIOC) || \
8763                                         ((INSTANCE) == GPIOD) || \
8764                                         ((INSTANCE) == GPIOE) || \
8765                                         ((INSTANCE) == GPIOH))
8766 
8767 /**************************** GPIO Alternate Function Instances ***************/
8768 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
8769 
8770 /**************************** GPIO Lock Instances *****************************/
8771 /* On L1, all GPIO Bank support the Lock mechanism */
8772 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
8773 
8774 /******************************** I2C Instances *******************************/
8775 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
8776                                        ((INSTANCE) == I2C2))
8777 
8778 /****************************** SMBUS Instances *******************************/
8779 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
8780 
8781 /******************************** I2S Instances *******************************/
8782 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \
8783                                        ((INSTANCE) == SPI3))
8784 /****************************** IWDG Instances ********************************/
8785 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
8786 
8787 /****************************** OPAMP Instances *******************************/
8788 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
8789                                          ((INSTANCE) == OPAMP2))
8790 
8791 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
8792 
8793 /****************************** RTC Instances *********************************/
8794 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
8795 
8796 /******************************** SPI Instances *******************************/
8797 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
8798                                        ((INSTANCE) == SPI2) || \
8799                                        ((INSTANCE) == SPI3))
8800 
8801 /****************************** TIM Instances *********************************/
8802 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
8803                                    ((INSTANCE) == TIM3)    || \
8804                                    ((INSTANCE) == TIM4)    || \
8805                                    ((INSTANCE) == TIM5)    || \
8806                                    ((INSTANCE) == TIM6)    || \
8807                                    ((INSTANCE) == TIM7)    || \
8808                                    ((INSTANCE) == TIM9)    || \
8809                                    ((INSTANCE) == TIM10)   || \
8810                                    ((INSTANCE) == TIM11))
8811 
8812 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8813                                        ((INSTANCE) == TIM3)  || \
8814                                        ((INSTANCE) == TIM4)  || \
8815                                        ((INSTANCE) == TIM5)  || \
8816                                        ((INSTANCE) == TIM9)  || \
8817                                        ((INSTANCE) == TIM10) || \
8818                                        ((INSTANCE) == TIM11))
8819 
8820 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8821                                        ((INSTANCE) == TIM3)  || \
8822                                        ((INSTANCE) == TIM4)  || \
8823                                        ((INSTANCE) == TIM5)  || \
8824                                        ((INSTANCE) == TIM9))
8825 
8826 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8827                                        ((INSTANCE) == TIM3)  || \
8828                                        ((INSTANCE) == TIM4)  || \
8829                                        ((INSTANCE) == TIM5))
8830 
8831 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8832                                        ((INSTANCE) == TIM3)  || \
8833                                        ((INSTANCE) == TIM4)  || \
8834                                        ((INSTANCE) == TIM5))
8835 
8836 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8837                                                         ((INSTANCE) == TIM3)  || \
8838                                                         ((INSTANCE) == TIM4)  || \
8839                                                         ((INSTANCE) == TIM5)  || \
8840                                                         ((INSTANCE) == TIM9))
8841 
8842 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8843                                                         ((INSTANCE) == TIM3)  || \
8844                                                         ((INSTANCE) == TIM4)  || \
8845                                                         ((INSTANCE) == TIM5)  || \
8846                                                         ((INSTANCE) == TIM9)  || \
8847                                                         ((INSTANCE) == TIM10) || \
8848                                                         ((INSTANCE) == TIM11))
8849 
8850 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8851                                                    ((INSTANCE) == TIM3)  || \
8852                                                    ((INSTANCE) == TIM4)  || \
8853                                                    ((INSTANCE) == TIM5)  || \
8854                                                    ((INSTANCE) == TIM9))
8855 
8856 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8857                                                     ((INSTANCE) == TIM3)  || \
8858                                                     ((INSTANCE) == TIM4)  || \
8859                                                     ((INSTANCE) == TIM5)  || \
8860                                                     ((INSTANCE) == TIM9))
8861 
8862 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8863                                                 ((INSTANCE) == TIM3)  || \
8864                                                 ((INSTANCE) == TIM4))
8865 
8866 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8867                                        ((INSTANCE) == TIM3)  || \
8868                                        ((INSTANCE) == TIM4)  || \
8869                                        ((INSTANCE) == TIM5))
8870 
8871 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8872                                        ((INSTANCE) == TIM3)  || \
8873                                        ((INSTANCE) == TIM4)  || \
8874                                        ((INSTANCE) == TIM5))
8875 
8876 
8877 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8878                                           ((INSTANCE) == TIM3)  || \
8879                                           ((INSTANCE) == TIM4)  || \
8880                                           ((INSTANCE) == TIM5)  || \
8881                                           ((INSTANCE) == TIM6)  || \
8882                                           ((INSTANCE) == TIM7)  || \
8883                                           ((INSTANCE) == TIM9))
8884 
8885 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8886                                          ((INSTANCE) == TIM3)  || \
8887                                          ((INSTANCE) == TIM4)  || \
8888                                          ((INSTANCE) == TIM5)  || \
8889                                          ((INSTANCE) == TIM9))
8890 
8891 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
8892 
8893 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8894                                             ((INSTANCE) == TIM3)  || \
8895                                             ((INSTANCE) == TIM4)  || \
8896                                             ((INSTANCE) == TIM5))
8897 
8898 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
8899     ((((INSTANCE) == TIM2) &&                   \
8900      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8901       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8902       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8903       ((CHANNEL) == TIM_CHANNEL_4)))           \
8904     ||                                         \
8905     (((INSTANCE) == TIM3) &&                   \
8906      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8907       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8908       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8909       ((CHANNEL) == TIM_CHANNEL_4)))           \
8910     ||                                         \
8911     (((INSTANCE) == TIM4) &&                   \
8912      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8913       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8914       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8915       ((CHANNEL) == TIM_CHANNEL_4)))           \
8916     ||                                         \
8917     (((INSTANCE) == TIM5) &&                   \
8918      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8919       ((CHANNEL) == TIM_CHANNEL_2) ||          \
8920       ((CHANNEL) == TIM_CHANNEL_3) ||          \
8921       ((CHANNEL) == TIM_CHANNEL_4)))           \
8922     ||                                         \
8923     (((INSTANCE) == TIM9) &&                  \
8924      (((CHANNEL) == TIM_CHANNEL_1) ||          \
8925       ((CHANNEL) == TIM_CHANNEL_2)))           \
8926     ||                                         \
8927     (((INSTANCE) == TIM10) &&                  \
8928      (((CHANNEL) == TIM_CHANNEL_1)))           \
8929     ||                                         \
8930     (((INSTANCE) == TIM11) &&                  \
8931      (((CHANNEL) == TIM_CHANNEL_1))))
8932 
8933 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8934                                                   ((INSTANCE) == TIM3)  || \
8935                                                   ((INSTANCE) == TIM4)  || \
8936                                                   ((INSTANCE) == TIM5)  || \
8937                                                   ((INSTANCE) == TIM9)  || \
8938                                                   ((INSTANCE) == TIM10) || \
8939                                                   ((INSTANCE) == TIM11))
8940 
8941 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
8942                                        ((INSTANCE) == TIM3)    || \
8943                                        ((INSTANCE) == TIM4)    || \
8944                                        ((INSTANCE) == TIM5)    || \
8945                                        ((INSTANCE) == TIM6)    || \
8946                                        ((INSTANCE) == TIM7))
8947 
8948 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8949                                           ((INSTANCE) == TIM3)  || \
8950                                           ((INSTANCE) == TIM4)  || \
8951                                           ((INSTANCE) == TIM5))
8952 
8953 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
8954                                                        ((INSTANCE) == TIM3)    || \
8955                                                        ((INSTANCE) == TIM4)    || \
8956                                                        ((INSTANCE) == TIM5)    || \
8957                                                        ((INSTANCE) == TIM9))
8958 
8959 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
8960                                                      ((INSTANCE) == TIM3)  || \
8961                                                      ((INSTANCE) == TIM4)  || \
8962                                                      ((INSTANCE) == TIM5)  || \
8963                                                      ((INSTANCE) == TIM9))
8964 
8965 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
8966                                          ((INSTANCE) == TIM3)    || \
8967                                          ((INSTANCE) == TIM9)    || \
8968                                          ((INSTANCE) == TIM10)   || \
8969                                          ((INSTANCE) == TIM11))
8970 
8971 /******************** USART Instances : Synchronous mode **********************/
8972 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8973                                      ((INSTANCE) == USART2) || \
8974                                      ((INSTANCE) == USART3))
8975 
8976 /******************** UART Instances : Asynchronous mode **********************/
8977 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8978                                     ((INSTANCE) == USART2) || \
8979                                     ((INSTANCE) == USART3))
8980 
8981 /******************** UART Instances : Half-Duplex mode **********************/
8982 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
8983                                                  ((INSTANCE) == USART2) || \
8984                                                  ((INSTANCE) == USART3))
8985 
8986 /******************** UART Instances : LIN mode **********************/
8987 #define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
8988                                           ((INSTANCE) == USART2) || \
8989                                           ((INSTANCE) == USART3))
8990 
8991 /****************** UART Instances : Hardware Flow control ********************/
8992 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8993                                            ((INSTANCE) == USART2) || \
8994                                            ((INSTANCE) == USART3))
8995 
8996 /********************* UART Instances : Smard card mode ***********************/
8997 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
8998                                          ((INSTANCE) == USART2) || \
8999                                          ((INSTANCE) == USART3))
9000 
9001 /*********************** UART Instances : IRDA mode ***************************/
9002 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
9003                                     ((INSTANCE) == USART2) || \
9004                                     ((INSTANCE) == USART3))
9005 
9006 /***************** UART Instances : Multi-Processor mode **********************/
9007 #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
9008                                                      ((INSTANCE) == USART2) || \
9009                                                      ((INSTANCE) == USART3))
9010 
9011 /****************************** WWDG Instances ********************************/
9012 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
9013 
9014 
9015 /****************************** LCD Instances ********************************/
9016 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
9017 
9018 /****************************** USB Instances ********************************/
9019 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
9020 
9021 /**
9022   * @}
9023   */
9024 
9025 /******************************************************************************/
9026 /*  For a painless codes migration between the STM32L1xx device product       */
9027 /*  lines, the aliases defined below are put in place to overcome the         */
9028 /*  differences in the interrupt handlers and IRQn definitions.               */
9029 /*  No need to update developed interrupt code when moving across             */
9030 /*  product lines within the same STM32L1 Family                              */
9031 /******************************************************************************/
9032 
9033 /* Aliases for __IRQn */
9034 
9035 /* Aliases for __IRQHandler */
9036 
9037 /**
9038   * @}
9039   */
9040 
9041 /**
9042   * @}
9043   */
9044 
9045 #ifdef __cplusplus
9046 }
9047 #endif /* __cplusplus */
9048 
9049 #endif /* __STM32L152xC_H */
9050 
9051 
9052 
9053 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
9054