1 /** 2 * \file 3 * 4 * \brief Header file for SAML21E15B 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21E15B_ 30 #define _SAML21E15B_ 31 32 /** 33 * \ingroup SAML21_definitions 34 * \addtogroup SAML21E15B_definitions SAML21E15B definitions 35 * This file defines all structures and symbols for SAML21E15B: 36 * - registers and bitfields 37 * - peripheral base address 38 * - peripheral ID 39 * - PIO definitions 40 */ 41 /*@{*/ 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 #include <stdint.h> 49 #ifndef __cplusplus 50 typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 51 typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 52 typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 53 #else 54 typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ 55 typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ 56 typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ 57 #endif 58 typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ 59 typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ 60 typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ 61 typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ 62 typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ 63 typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ 64 #if !defined(_UL) 65 #define _U(x) x ## U /**< C code: Unsigned integer literal constant value */ 66 #define _L(x) x ## L /**< C code: Long integer literal constant value */ 67 #define _UL(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ 68 #endif 69 #else 70 #if !defined(_UL) 71 #define _U(x) x /**< Assembler: Unsigned integer literal constant value */ 72 #define _L(x) x /**< Assembler: Long integer literal constant value */ 73 #define _UL(x) x /**< Assembler: Unsigned Long integer literal constant value */ 74 #endif 75 #endif 76 77 /* ************************************************************************** */ 78 /** CMSIS DEFINITIONS FOR SAML21E15B */ 79 /* ************************************************************************** */ 80 /** \defgroup SAML21E15B_cmsis CMSIS Definitions */ 81 /*@{*/ 82 83 /** Interrupt Number Definition */ 84 typedef enum IRQn 85 { 86 /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ 87 NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ 88 HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ 89 SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ 90 PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ 91 SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ 92 /****** SAML21E15B-specific Interrupt Numbers ***********************/ 93 SYSTEM_IRQn = 0, /**< 0 SAML21E15B System Interrupts */ 94 WDT_IRQn = 1, /**< 1 SAML21E15B Watchdog Timer (WDT) */ 95 RTC_IRQn = 2, /**< 2 SAML21E15B Real-Time Counter (RTC) */ 96 EIC_IRQn = 3, /**< 3 SAML21E15B External Interrupt Controller (EIC) */ 97 NVMCTRL_IRQn = 4, /**< 4 SAML21E15B Non-Volatile Memory Controller (NVMCTRL) */ 98 DMAC_IRQn = 5, /**< 5 SAML21E15B Direct Memory Access Controller (DMAC) */ 99 USB_IRQn = 6, /**< 6 SAML21E15B Universal Serial Bus (USB) */ 100 EVSYS_IRQn = 7, /**< 7 SAML21E15B Event System Interface (EVSYS) */ 101 SERCOM0_IRQn = 8, /**< 8 SAML21E15B Serial Communication Interface 0 (SERCOM0) */ 102 SERCOM1_IRQn = 9, /**< 9 SAML21E15B Serial Communication Interface 1 (SERCOM1) */ 103 SERCOM2_IRQn = 10, /**< 10 SAML21E15B Serial Communication Interface 2 (SERCOM2) */ 104 SERCOM3_IRQn = 11, /**< 11 SAML21E15B Serial Communication Interface 3 (SERCOM3) */ 105 SERCOM4_IRQn = 12, /**< 12 SAML21E15B Serial Communication Interface 4 (SERCOM4) */ 106 SERCOM5_IRQn = 13, /**< 13 SAML21E15B Serial Communication Interface 5 (SERCOM5) */ 107 TCC0_IRQn = 14, /**< 14 SAML21E15B Timer Counter Control 0 (TCC0) */ 108 TCC1_IRQn = 15, /**< 15 SAML21E15B Timer Counter Control 1 (TCC1) */ 109 TCC2_IRQn = 16, /**< 16 SAML21E15B Timer Counter Control 2 (TCC2) */ 110 TC0_IRQn = 17, /**< 17 SAML21E15B Basic Timer Counter 0 (TC0) */ 111 TC1_IRQn = 18, /**< 18 SAML21E15B Basic Timer Counter 1 (TC1) */ 112 TC4_IRQn = 21, /**< 21 SAML21E15B Basic Timer Counter 4 (TC4) */ 113 ADC_IRQn = 22, /**< 22 SAML21E15B Analog Digital Converter (ADC) */ 114 AC_IRQn = 23, /**< 23 SAML21E15B Analog Comparators (AC) */ 115 DAC_IRQn = 24, /**< 24 SAML21E15B Digital-to-Analog Converter (DAC) */ 116 PTC_IRQn = 25, /**< 25 SAML21E15B Peripheral Touch Controller (PTC) */ 117 AES_IRQn = 26, /**< 26 SAML21E15B Advanced Encryption Standard (AES) */ 118 TRNG_IRQn = 27, /**< 27 SAML21E15B True Random Generator (TRNG) */ 119 120 PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */ 121 } IRQn_Type; 122 123 typedef struct _DeviceVectors 124 { 125 /* Stack pointer */ 126 void* pvStack; 127 128 /* Cortex-M handlers */ 129 void* pfnReset_Handler; 130 void* pfnNMI_Handler; 131 void* pfnHardFault_Handler; 132 void* pvReservedM12; 133 void* pvReservedM11; 134 void* pvReservedM10; 135 void* pvReservedM9; 136 void* pvReservedM8; 137 void* pvReservedM7; 138 void* pvReservedM6; 139 void* pfnSVC_Handler; 140 void* pvReservedM4; 141 void* pvReservedM3; 142 void* pfnPendSV_Handler; 143 void* pfnSysTick_Handler; 144 145 /* Peripheral handlers */ 146 void* pfnSYSTEM_Handler; /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */ 147 void* pfnWDT_Handler; /* 1 Watchdog Timer */ 148 void* pfnRTC_Handler; /* 2 Real-Time Counter */ 149 void* pfnEIC_Handler; /* 3 External Interrupt Controller */ 150 void* pfnNVMCTRL_Handler; /* 4 Non-Volatile Memory Controller */ 151 void* pfnDMAC_Handler; /* 5 Direct Memory Access Controller */ 152 void* pfnUSB_Handler; /* 6 Universal Serial Bus */ 153 void* pfnEVSYS_Handler; /* 7 Event System Interface */ 154 void* pfnSERCOM0_Handler; /* 8 Serial Communication Interface 0 */ 155 void* pfnSERCOM1_Handler; /* 9 Serial Communication Interface 1 */ 156 void* pfnSERCOM2_Handler; /* 10 Serial Communication Interface 2 */ 157 void* pfnSERCOM3_Handler; /* 11 Serial Communication Interface 3 */ 158 void* pfnSERCOM4_Handler; /* 12 Serial Communication Interface 4 */ 159 void* pfnSERCOM5_Handler; /* 13 Serial Communication Interface 5 */ 160 void* pfnTCC0_Handler; /* 14 Timer Counter Control 0 */ 161 void* pfnTCC1_Handler; /* 15 Timer Counter Control 1 */ 162 void* pfnTCC2_Handler; /* 16 Timer Counter Control 2 */ 163 void* pfnTC0_Handler; /* 17 Basic Timer Counter 0 */ 164 void* pfnTC1_Handler; /* 18 Basic Timer Counter 1 */ 165 void* pvReserved19; 166 void* pvReserved20; 167 void* pfnTC4_Handler; /* 21 Basic Timer Counter 4 */ 168 void* pfnADC_Handler; /* 22 Analog Digital Converter */ 169 void* pfnAC_Handler; /* 23 Analog Comparators */ 170 void* pfnDAC_Handler; /* 24 Digital-to-Analog Converter */ 171 void* pfnPTC_Handler; /* 25 Peripheral Touch Controller */ 172 void* pfnAES_Handler; /* 26 Advanced Encryption Standard */ 173 void* pfnTRNG_Handler; /* 27 True Random Generator */ 174 void* pvReserved28; 175 } DeviceVectors; 176 177 /* Cortex-M0+ processor handlers */ 178 void Reset_Handler ( void ); 179 void NMI_Handler ( void ); 180 void HardFault_Handler ( void ); 181 void SVC_Handler ( void ); 182 void PendSV_Handler ( void ); 183 void SysTick_Handler ( void ); 184 185 /* Peripherals handlers */ 186 void SYSTEM_Handler ( void ); 187 void WDT_Handler ( void ); 188 void RTC_Handler ( void ); 189 void EIC_Handler ( void ); 190 void NVMCTRL_Handler ( void ); 191 void DMAC_Handler ( void ); 192 void USB_Handler ( void ); 193 void EVSYS_Handler ( void ); 194 void SERCOM0_Handler ( void ); 195 void SERCOM1_Handler ( void ); 196 void SERCOM2_Handler ( void ); 197 void SERCOM3_Handler ( void ); 198 void SERCOM4_Handler ( void ); 199 void SERCOM5_Handler ( void ); 200 void TCC0_Handler ( void ); 201 void TCC1_Handler ( void ); 202 void TCC2_Handler ( void ); 203 void TC0_Handler ( void ); 204 void TC1_Handler ( void ); 205 void TC4_Handler ( void ); 206 void ADC_Handler ( void ); 207 void AC_Handler ( void ); 208 void DAC_Handler ( void ); 209 void PTC_Handler ( void ); 210 void AES_Handler ( void ); 211 void TRNG_Handler ( void ); 212 213 /* 214 * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals 215 */ 216 217 #define LITTLE_ENDIAN 1 218 #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ 219 #define __MPU_PRESENT 0 /*!< MPU present or not */ 220 #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ 221 #define __VTOR_PRESENT 1 /*!< VTOR present or not */ 222 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ 223 224 /** 225 * \brief CMSIS includes 226 */ 227 228 #include <core_cm0plus.h> 229 #if !defined DONT_USE_CMSIS_INIT 230 #include "system_saml21.h" 231 #endif /* DONT_USE_CMSIS_INIT */ 232 233 /*@}*/ 234 235 /* ************************************************************************** */ 236 /** SOFTWARE PERIPHERAL API DEFINITION FOR SAML21E15B */ 237 /* ************************************************************************** */ 238 /** \defgroup SAML21E15B_api Peripheral Software API */ 239 /*@{*/ 240 241 #include "component/ac.h" 242 #include "component/adc.h" 243 #include "component/aes.h" 244 #include "component/ccl.h" 245 #include "component/dac.h" 246 #include "component/dmac.h" 247 #include "component/dsu.h" 248 #include "component/eic.h" 249 #include "component/evsys.h" 250 #include "component/gclk.h" 251 #include "component/mclk.h" 252 #include "component/mtb.h" 253 #include "component/nvmctrl.h" 254 #include "component/opamp.h" 255 #include "component/oscctrl.h" 256 #include "component/osc32kctrl.h" 257 #include "component/pac.h" 258 #include "component/pm.h" 259 #include "component/port.h" 260 #include "component/rstc.h" 261 #include "component/rtc.h" 262 #include "component/sercom.h" 263 #include "component/supc.h" 264 #include "component/tal.h" 265 #include "component/tc.h" 266 #include "component/tcc.h" 267 #include "component/trng.h" 268 #include "component/usb.h" 269 #include "component/wdt.h" 270 /*@}*/ 271 272 /* ************************************************************************** */ 273 /** REGISTERS ACCESS DEFINITIONS FOR SAML21E15B */ 274 /* ************************************************************************** */ 275 /** \defgroup SAML21E15B_reg Registers Access Definitions */ 276 /*@{*/ 277 278 #include "instance/ac.h" 279 #include "instance/adc.h" 280 #include "instance/aes.h" 281 #include "instance/ccl.h" 282 #include "instance/dac.h" 283 #include "instance/dmac.h" 284 #include "instance/dsu.h" 285 #include "instance/eic.h" 286 #include "instance/evsys.h" 287 #include "instance/gclk.h" 288 #include "instance/mclk.h" 289 #include "instance/mtb.h" 290 #include "instance/nvmctrl.h" 291 #include "instance/opamp.h" 292 #include "instance/oscctrl.h" 293 #include "instance/osc32kctrl.h" 294 #include "instance/pac.h" 295 #include "instance/pm.h" 296 #include "instance/port.h" 297 #include "instance/rstc.h" 298 #include "instance/rtc.h" 299 #include "instance/sercom0.h" 300 #include "instance/sercom1.h" 301 #include "instance/sercom2.h" 302 #include "instance/sercom3.h" 303 #include "instance/sercom4.h" 304 #include "instance/sercom5.h" 305 #include "instance/supc.h" 306 #include "instance/tal.h" 307 #include "instance/tc0.h" 308 #include "instance/tc1.h" 309 #include "instance/tc4.h" 310 #include "instance/tcc0.h" 311 #include "instance/tcc1.h" 312 #include "instance/tcc2.h" 313 #include "instance/trng.h" 314 #include "instance/usb.h" 315 #include "instance/wdt.h" 316 /*@}*/ 317 318 /* ************************************************************************** */ 319 /** PERIPHERAL ID DEFINITIONS FOR SAML21E15B */ 320 /* ************************************************************************** */ 321 /** \defgroup SAML21E15B_id Peripheral Ids Definitions */ 322 /*@{*/ 323 324 // Peripheral instances on HPB0 bridge 325 #define ID_PM 0 /**< \brief Power Manager (PM) */ 326 #define ID_MCLK 1 /**< \brief Main Clock (MCLK) */ 327 #define ID_RSTC 2 /**< \brief Reset Controller (RSTC) */ 328 #define ID_OSCCTRL 3 /**< \brief Oscillators Control (OSCCTRL) */ 329 #define ID_OSC32KCTRL 4 /**< \brief 32k Oscillators Control (OSC32KCTRL) */ 330 #define ID_SUPC 5 /**< \brief Supply Controller (SUPC) */ 331 #define ID_GCLK 6 /**< \brief Generic Clock Generator (GCLK) */ 332 #define ID_WDT 7 /**< \brief Watchdog Timer (WDT) */ 333 #define ID_RTC 8 /**< \brief Real-Time Counter (RTC) */ 334 #define ID_EIC 9 /**< \brief External Interrupt Controller (EIC) */ 335 #define ID_PORT 10 /**< \brief Port Module (PORT) */ 336 #define ID_TAL 11 /**< \brief Trigger Allocator (TAL) */ 337 338 // Peripheral instances on HPB1 bridge 339 #define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ 340 #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ 341 #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ 342 #define ID_MTB 35 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ 343 344 // Peripheral instances on HPB2 bridge 345 #define ID_SERCOM0 64 /**< \brief Serial Communication Interface 0 (SERCOM0) */ 346 #define ID_SERCOM1 65 /**< \brief Serial Communication Interface 1 (SERCOM1) */ 347 #define ID_SERCOM2 66 /**< \brief Serial Communication Interface 2 (SERCOM2) */ 348 #define ID_SERCOM3 67 /**< \brief Serial Communication Interface 3 (SERCOM3) */ 349 #define ID_SERCOM4 68 /**< \brief Serial Communication Interface 4 (SERCOM4) */ 350 #define ID_TCC0 69 /**< \brief Timer Counter Control 0 (TCC0) */ 351 #define ID_TCC1 70 /**< \brief Timer Counter Control 1 (TCC1) */ 352 #define ID_TCC2 71 /**< \brief Timer Counter Control 2 (TCC2) */ 353 #define ID_TC0 72 /**< \brief Basic Timer Counter 0 (TC0) */ 354 #define ID_TC1 73 /**< \brief Basic Timer Counter 1 (TC1) */ 355 #define ID_DAC 76 /**< \brief Digital-to-Analog Converter (DAC) */ 356 #define ID_AES 77 /**< \brief Advanced Encryption Standard (AES) */ 357 #define ID_TRNG 78 /**< \brief True Random Generator (TRNG) */ 358 359 // Peripheral instances on HPB3 bridge 360 #define ID_EVSYS 96 /**< \brief Event System Interface (EVSYS) */ 361 #define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ 362 #define ID_TC4 98 /**< \brief Basic Timer Counter 4 (TC4) */ 363 #define ID_ADC 99 /**< \brief Analog Digital Converter (ADC) */ 364 #define ID_AC 100 /**< \brief Analog Comparators (AC) */ 365 #define ID_PTC 101 /**< \brief Peripheral Touch Controller (PTC) */ 366 #define ID_OPAMP 102 /**< \brief Operational Amplifier (OPAMP) */ 367 #define ID_CCL 103 /**< \brief Configurable Custom Logic (CCL) */ 368 369 // Peripheral instances on HPB4 bridge 370 #define ID_PAC 128 /**< \brief Peripheral Access Controller (PAC) */ 371 #define ID_DMAC 129 /**< \brief Direct Memory Access Controller (DMAC) */ 372 373 #define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ 374 /*@}*/ 375 376 /* ************************************************************************** */ 377 /** BASE ADDRESS DEFINITIONS FOR SAML21E15B */ 378 /* ************************************************************************** */ 379 /** \defgroup SAML21E15B_base Peripheral Base Address Definitions */ 380 /*@{*/ 381 382 #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) 383 #define AC (0x43001000) /**< \brief (AC) APB Base Address */ 384 #define ADC (0x43000C00) /**< \brief (ADC) APB Base Address */ 385 #define AES (0x42003400) /**< \brief (AES) APB Base Address */ 386 #define CCL (0x43001C00) /**< \brief (CCL) APB Base Address */ 387 #define DAC (0x42003000) /**< \brief (DAC) APB Base Address */ 388 #define DMAC (0x44000400) /**< \brief (DMAC) APB Base Address */ 389 #define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ 390 #define EIC (0x40002400) /**< \brief (EIC) APB Base Address */ 391 #define EVSYS (0x43000000) /**< \brief (EVSYS) APB Base Address */ 392 #define GCLK (0x40001800) /**< \brief (GCLK) APB Base Address */ 393 #define MCLK (0x40000400) /**< \brief (MCLK) APB Base Address */ 394 #define MTB (0x41006000) /**< \brief (MTB) APB Base Address */ 395 #define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ 396 #define NVMCTRL_CAL (0x00800000) /**< \brief (NVMCTRL) CAL Base Address */ 397 #define NVMCTRL_LOCKBIT (0x00802000) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 398 #define NVMCTRL_OTP1 (0x00806000) /**< \brief (NVMCTRL) OTP1 Base Address */ 399 #define NVMCTRL_OTP2 (0x00806008) /**< \brief (NVMCTRL) OTP2 Base Address */ 400 #define NVMCTRL_OTP3 (0x00806010) /**< \brief (NVMCTRL) OTP3 Base Address */ 401 #define NVMCTRL_OTP4 (0x00806018) /**< \brief (NVMCTRL) OTP4 Base Address */ 402 #define NVMCTRL_OTP5 (0x00806020) /**< \brief (NVMCTRL) OTP5 Base Address */ 403 #define NVMCTRL_TEMP_LOG (0x00806030) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 404 #define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ 405 #define OPAMP (0x43001800) /**< \brief (OPAMP) APB Base Address */ 406 #define OSCCTRL (0x40000C00) /**< \brief (OSCCTRL) APB Base Address */ 407 #define OSC32KCTRL (0x40001000) /**< \brief (OSC32KCTRL) APB Base Address */ 408 #define PAC (0x44000000) /**< \brief (PAC) APB Base Address */ 409 #define PM (0x40000000) /**< \brief (PM) APB Base Address */ 410 #define PORT (0x40002800) /**< \brief (PORT) APB Base Address */ 411 #define PORT_IOBUS (0x60000000) /**< \brief (PORT) IOBUS Base Address */ 412 #define PTC (0x43001400) /**< \brief (PTC) APB Base Address */ 413 #define RSTC (0x40000800) /**< \brief (RSTC) APB Base Address */ 414 #define RTC (0x40002000) /**< \brief (RTC) APB Base Address */ 415 #define SERCOM0 (0x42000000) /**< \brief (SERCOM0) APB Base Address */ 416 #define SERCOM1 (0x42000400) /**< \brief (SERCOM1) APB Base Address */ 417 #define SERCOM2 (0x42000800) /**< \brief (SERCOM2) APB Base Address */ 418 #define SERCOM3 (0x42000C00) /**< \brief (SERCOM3) APB Base Address */ 419 #define SERCOM4 (0x42001000) /**< \brief (SERCOM4) APB Base Address */ 420 #define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ 421 #define SUPC (0x40001400) /**< \brief (SUPC) APB Base Address */ 422 #define TAL (0x40002C00) /**< \brief (TAL) APB Base Address */ 423 #define TC0 (0x42002000) /**< \brief (TC0) APB Base Address */ 424 #define TC1 (0x42002400) /**< \brief (TC1) APB Base Address */ 425 #define TC4 (0x43000800) /**< \brief (TC4) APB Base Address */ 426 #define TCC0 (0x42001400) /**< \brief (TCC0) APB Base Address */ 427 #define TCC1 (0x42001800) /**< \brief (TCC1) APB Base Address */ 428 #define TCC2 (0x42001C00) /**< \brief (TCC2) APB Base Address */ 429 #define TRNG (0x42003800) /**< \brief (TRNG) APB Base Address */ 430 #define USB (0x41000000) /**< \brief (USB) APB Base Address */ 431 #define WDT (0x40001C00) /**< \brief (WDT) APB Base Address */ 432 #else 433 #define AC ((Ac *)0x43001000UL) /**< \brief (AC) APB Base Address */ 434 #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ 435 #define AC_INSTS { AC } /**< \brief (AC) Instances List */ 436 437 #define ADC ((Adc *)0x43000C00UL) /**< \brief (ADC) APB Base Address */ 438 #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ 439 #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ 440 441 #define AES ((Aes *)0x42003400UL) /**< \brief (AES) APB Base Address */ 442 #define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ 443 #define AES_INSTS { AES } /**< \brief (AES) Instances List */ 444 445 #define CCL ((Ccl *)0x43001C00UL) /**< \brief (CCL) APB Base Address */ 446 #define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ 447 #define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ 448 449 #define DAC ((Dac *)0x42003000UL) /**< \brief (DAC) APB Base Address */ 450 #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ 451 #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ 452 453 #define DMAC ((Dmac *)0x44000400UL) /**< \brief (DMAC) APB Base Address */ 454 #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ 455 #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ 456 457 #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ 458 #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ 459 #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ 460 461 #define EIC ((Eic *)0x40002400UL) /**< \brief (EIC) APB Base Address */ 462 #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ 463 #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ 464 465 #define EVSYS ((Evsys *)0x43000000UL) /**< \brief (EVSYS) APB Base Address */ 466 #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ 467 #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ 468 469 #define GCLK ((Gclk *)0x40001800UL) /**< \brief (GCLK) APB Base Address */ 470 #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ 471 #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ 472 473 #define MCLK ((Mclk *)0x40000400UL) /**< \brief (MCLK) APB Base Address */ 474 #define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ 475 #define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ 476 477 #define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ 478 #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ 479 #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ 480 481 #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ 482 #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ 483 #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ 484 #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ 485 #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ 486 #define NVMCTRL_OTP3 (0x00806010UL) /**< \brief (NVMCTRL) OTP3 Base Address */ 487 #define NVMCTRL_OTP4 (0x00806018UL) /**< \brief (NVMCTRL) OTP4 Base Address */ 488 #define NVMCTRL_OTP5 (0x00806020UL) /**< \brief (NVMCTRL) OTP5 Base Address */ 489 #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ 490 #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ 491 #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ 492 #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ 493 494 #define OPAMP ((Opamp *)0x43001800UL) /**< \brief (OPAMP) APB Base Address */ 495 #define OPAMP_INST_NUM 1 /**< \brief (OPAMP) Number of instances */ 496 #define OPAMP_INSTS { OPAMP } /**< \brief (OPAMP) Instances List */ 497 498 #define OSCCTRL ((Oscctrl *)0x40000C00UL) /**< \brief (OSCCTRL) APB Base Address */ 499 #define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ 500 #define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ 501 502 #define OSC32KCTRL ((Osc32kctrl *)0x40001000UL) /**< \brief (OSC32KCTRL) APB Base Address */ 503 #define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ 504 #define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ 505 506 #define PAC ((Pac *)0x44000000UL) /**< \brief (PAC) APB Base Address */ 507 #define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ 508 #define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ 509 510 #define PM ((Pm *)0x40000000UL) /**< \brief (PM) APB Base Address */ 511 #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ 512 #define PM_INSTS { PM } /**< \brief (PM) Instances List */ 513 514 #define PORT ((Port *)0x40002800UL) /**< \brief (PORT) APB Base Address */ 515 #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ 516 #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ 517 #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ 518 #define PORT_IOBUS_INST_NUM 1 /**< \brief (PORT) Number of instances */ 519 #define PORT_IOBUS_INSTS { PORT_IOBUS } /**< \brief (PORT) Instances List */ 520 521 #define PTC ((void *)0x43001400UL) /**< \brief (PTC) APB Base Address */ 522 #define PTC_GCLK_ID 33 523 #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ 524 #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ 525 526 #define RSTC ((Rstc *)0x40000800UL) /**< \brief (RSTC) APB Base Address */ 527 #define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ 528 #define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ 529 530 #define RTC ((Rtc *)0x40002000UL) /**< \brief (RTC) APB Base Address */ 531 #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ 532 #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ 533 534 #define SERCOM0 ((Sercom *)0x42000000UL) /**< \brief (SERCOM0) APB Base Address */ 535 #define SERCOM1 ((Sercom *)0x42000400UL) /**< \brief (SERCOM1) APB Base Address */ 536 #define SERCOM2 ((Sercom *)0x42000800UL) /**< \brief (SERCOM2) APB Base Address */ 537 #define SERCOM3 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM3) APB Base Address */ 538 #define SERCOM4 ((Sercom *)0x42001000UL) /**< \brief (SERCOM4) APB Base Address */ 539 #define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ 540 #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ 541 #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ 542 543 #define SUPC ((Supc *)0x40001400UL) /**< \brief (SUPC) APB Base Address */ 544 #define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ 545 #define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ 546 547 #define TAL ((Tal *)0x40002C00UL) /**< \brief (TAL) APB Base Address */ 548 #define TAL_INST_NUM 1 /**< \brief (TAL) Number of instances */ 549 #define TAL_INSTS { TAL } /**< \brief (TAL) Instances List */ 550 551 #define TC0 ((Tc *)0x42002000UL) /**< \brief (TC0) APB Base Address */ 552 #define TC1 ((Tc *)0x42002400UL) /**< \brief (TC1) APB Base Address */ 553 #define TC4 ((Tc *)0x43000800UL) /**< \brief (TC4) APB Base Address */ 554 #define TC_INST_NUM 3 /**< \brief (TC) Number of instances */ 555 #define TC_INSTS { TC0, TC1, TC4 } /**< \brief (TC) Instances List */ 556 557 #define TCC0 ((Tcc *)0x42001400UL) /**< \brief (TCC0) APB Base Address */ 558 #define TCC1 ((Tcc *)0x42001800UL) /**< \brief (TCC1) APB Base Address */ 559 #define TCC2 ((Tcc *)0x42001C00UL) /**< \brief (TCC2) APB Base Address */ 560 #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ 561 #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ 562 563 #define TRNG ((Trng *)0x42003800UL) /**< \brief (TRNG) APB Base Address */ 564 #define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ 565 #define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ 566 567 #define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ 568 #define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ 569 #define USB_INSTS { USB } /**< \brief (USB) Instances List */ 570 571 #define WDT ((Wdt *)0x40001C00UL) /**< \brief (WDT) APB Base Address */ 572 #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ 573 #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ 574 575 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 576 /*@}*/ 577 578 /* ************************************************************************** */ 579 /** PORT DEFINITIONS FOR SAML21E15B */ 580 /* ************************************************************************** */ 581 /** \defgroup SAML21E15B_port PORT Definitions */ 582 /*@{*/ 583 584 #include "pio/saml21e15b.h" 585 /*@}*/ 586 587 /* ************************************************************************** */ 588 /** MEMORY MAPPING DEFINITIONS FOR SAML21E15B */ 589 /* ************************************************************************** */ 590 591 #define FLASH_SIZE _UL(0x00008000) /* 32 kB */ 592 #define FLASH_PAGE_SIZE 64 593 #define FLASH_NB_OF_PAGES 512 594 #define FLASH_USER_PAGE_SIZE 64 595 #define HSRAM_SIZE _UL(0x00001000) /* 4 kB */ 596 #define LPRAM_SIZE _UL(0x00000800) /* 2 kB */ 597 598 #define FLASH_ADDR _UL(0x00000000) /**< FLASH base address */ 599 #define FLASH_USER_PAGE_ADDR _UL(0x00800000) /**< FLASH_USER_PAGE base address */ 600 #define HSRAM_ADDR _UL(0x20000000) /**< HSRAM base address */ 601 #define LPRAM_ADDR _UL(0x30000000) /**< LPRAM base address */ 602 #define HPB0_ADDR _UL(0x40000000) /**< HPB0 base address */ 603 #define HPB1_ADDR _UL(0x41000000) /**< HPB1 base address */ 604 #define HPB2_ADDR _UL(0x42000000) /**< HPB2 base address */ 605 #define HPB3_ADDR _UL(0x43000000) /**< HPB3 base address */ 606 #define HPB4_ADDR _UL(0x44000000) /**< HPB4 base address */ 607 #define PPB_ADDR _UL(0xE0000000) /**< PPB base address */ 608 609 #define DSU_DID_RESETVALUE _UL(0x1081021C) 610 #define NVMCTRL_RWW_EEPROM_SIZE _UL(0x00000400) /* 1 kB */ 611 #define PORT_GROUPS 1 612 #define USB_HOST_IMPLEMENTED 1 613 614 /* ************************************************************************** */ 615 /** ELECTRICAL DEFINITIONS FOR SAML21E15B */ 616 /* ************************************************************************** */ 617 618 619 #ifdef __cplusplus 620 } 621 #endif 622 623 /*@}*/ 624 625 #endif /* SAML21E15B_H */ 626
