1 /** 2 * \file 3 * 4 * \brief Peripheral I/O description for SAML21E18B 5 * 6 * Copyright (c) 2017 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21E18B_PIO_ 30 #define _SAML21E18B_PIO_ 31 32 #define PIN_PA00 0 /**< \brief Pin Number for PA00 */ 33 #define PORT_PA00 (_UL(1) << 0) /**< \brief PORT Mask for PA00 */ 34 #define PIN_PA01 1 /**< \brief Pin Number for PA01 */ 35 #define PORT_PA01 (_UL(1) << 1) /**< \brief PORT Mask for PA01 */ 36 #define PIN_PA02 2 /**< \brief Pin Number for PA02 */ 37 #define PORT_PA02 (_UL(1) << 2) /**< \brief PORT Mask for PA02 */ 38 #define PIN_PA03 3 /**< \brief Pin Number for PA03 */ 39 #define PORT_PA03 (_UL(1) << 3) /**< \brief PORT Mask for PA03 */ 40 #define PIN_PA04 4 /**< \brief Pin Number for PA04 */ 41 #define PORT_PA04 (_UL(1) << 4) /**< \brief PORT Mask for PA04 */ 42 #define PIN_PA05 5 /**< \brief Pin Number for PA05 */ 43 #define PORT_PA05 (_UL(1) << 5) /**< \brief PORT Mask for PA05 */ 44 #define PIN_PA06 6 /**< \brief Pin Number for PA06 */ 45 #define PORT_PA06 (_UL(1) << 6) /**< \brief PORT Mask for PA06 */ 46 #define PIN_PA07 7 /**< \brief Pin Number for PA07 */ 47 #define PORT_PA07 (_UL(1) << 7) /**< \brief PORT Mask for PA07 */ 48 #define PIN_PA08 8 /**< \brief Pin Number for PA08 */ 49 #define PORT_PA08 (_UL(1) << 8) /**< \brief PORT Mask for PA08 */ 50 #define PIN_PA09 9 /**< \brief Pin Number for PA09 */ 51 #define PORT_PA09 (_UL(1) << 9) /**< \brief PORT Mask for PA09 */ 52 #define PIN_PA10 10 /**< \brief Pin Number for PA10 */ 53 #define PORT_PA10 (_UL(1) << 10) /**< \brief PORT Mask for PA10 */ 54 #define PIN_PA11 11 /**< \brief Pin Number for PA11 */ 55 #define PORT_PA11 (_UL(1) << 11) /**< \brief PORT Mask for PA11 */ 56 #define PIN_PA14 14 /**< \brief Pin Number for PA14 */ 57 #define PORT_PA14 (_UL(1) << 14) /**< \brief PORT Mask for PA14 */ 58 #define PIN_PA15 15 /**< \brief Pin Number for PA15 */ 59 #define PORT_PA15 (_UL(1) << 15) /**< \brief PORT Mask for PA15 */ 60 #define PIN_PA16 16 /**< \brief Pin Number for PA16 */ 61 #define PORT_PA16 (_UL(1) << 16) /**< \brief PORT Mask for PA16 */ 62 #define PIN_PA17 17 /**< \brief Pin Number for PA17 */ 63 #define PORT_PA17 (_UL(1) << 17) /**< \brief PORT Mask for PA17 */ 64 #define PIN_PA18 18 /**< \brief Pin Number for PA18 */ 65 #define PORT_PA18 (_UL(1) << 18) /**< \brief PORT Mask for PA18 */ 66 #define PIN_PA19 19 /**< \brief Pin Number for PA19 */ 67 #define PORT_PA19 (_UL(1) << 19) /**< \brief PORT Mask for PA19 */ 68 #define PIN_PA22 22 /**< \brief Pin Number for PA22 */ 69 #define PORT_PA22 (_UL(1) << 22) /**< \brief PORT Mask for PA22 */ 70 #define PIN_PA23 23 /**< \brief Pin Number for PA23 */ 71 #define PORT_PA23 (_UL(1) << 23) /**< \brief PORT Mask for PA23 */ 72 #define PIN_PA24 24 /**< \brief Pin Number for PA24 */ 73 #define PORT_PA24 (_UL(1) << 24) /**< \brief PORT Mask for PA24 */ 74 #define PIN_PA25 25 /**< \brief Pin Number for PA25 */ 75 #define PORT_PA25 (_UL(1) << 25) /**< \brief PORT Mask for PA25 */ 76 #define PIN_PA27 27 /**< \brief Pin Number for PA27 */ 77 #define PORT_PA27 (_UL(1) << 27) /**< \brief PORT Mask for PA27 */ 78 #define PIN_PA30 30 /**< \brief Pin Number for PA30 */ 79 #define PORT_PA30 (_UL(1) << 30) /**< \brief PORT Mask for PA30 */ 80 #define PIN_PA31 31 /**< \brief Pin Number for PA31 */ 81 #define PORT_PA31 (_UL(1) << 31) /**< \brief PORT Mask for PA31 */ 82 /* ========== PORT definition for RSTC peripheral ========== */ 83 #define PIN_PA00A_RSTC_EXTWAKE0 _L(0) /**< \brief RSTC signal: EXTWAKE0 on PA00 mux A */ 84 #define MUX_PA00A_RSTC_EXTWAKE0 _L(0) 85 #define PINMUX_PA00A_RSTC_EXTWAKE0 ((PIN_PA00A_RSTC_EXTWAKE0 << 16) | MUX_PA00A_RSTC_EXTWAKE0) 86 #define PORT_PA00A_RSTC_EXTWAKE0 (_UL(1) << 0) 87 #define PIN_PA01A_RSTC_EXTWAKE1 _L(1) /**< \brief RSTC signal: EXTWAKE1 on PA01 mux A */ 88 #define MUX_PA01A_RSTC_EXTWAKE1 _L(0) 89 #define PINMUX_PA01A_RSTC_EXTWAKE1 ((PIN_PA01A_RSTC_EXTWAKE1 << 16) | MUX_PA01A_RSTC_EXTWAKE1) 90 #define PORT_PA01A_RSTC_EXTWAKE1 (_UL(1) << 1) 91 #define PIN_PA02A_RSTC_EXTWAKE2 _L(2) /**< \brief RSTC signal: EXTWAKE2 on PA02 mux A */ 92 #define MUX_PA02A_RSTC_EXTWAKE2 _L(0) 93 #define PINMUX_PA02A_RSTC_EXTWAKE2 ((PIN_PA02A_RSTC_EXTWAKE2 << 16) | MUX_PA02A_RSTC_EXTWAKE2) 94 #define PORT_PA02A_RSTC_EXTWAKE2 (_UL(1) << 2) 95 #define PIN_PA03A_RSTC_EXTWAKE3 _L(3) /**< \brief RSTC signal: EXTWAKE3 on PA03 mux A */ 96 #define MUX_PA03A_RSTC_EXTWAKE3 _L(0) 97 #define PINMUX_PA03A_RSTC_EXTWAKE3 ((PIN_PA03A_RSTC_EXTWAKE3 << 16) | MUX_PA03A_RSTC_EXTWAKE3) 98 #define PORT_PA03A_RSTC_EXTWAKE3 (_UL(1) << 3) 99 #define PIN_PA04A_RSTC_EXTWAKE4 _L(4) /**< \brief RSTC signal: EXTWAKE4 on PA04 mux A */ 100 #define MUX_PA04A_RSTC_EXTWAKE4 _L(0) 101 #define PINMUX_PA04A_RSTC_EXTWAKE4 ((PIN_PA04A_RSTC_EXTWAKE4 << 16) | MUX_PA04A_RSTC_EXTWAKE4) 102 #define PORT_PA04A_RSTC_EXTWAKE4 (_UL(1) << 4) 103 #define PIN_PA05A_RSTC_EXTWAKE5 _L(5) /**< \brief RSTC signal: EXTWAKE5 on PA05 mux A */ 104 #define MUX_PA05A_RSTC_EXTWAKE5 _L(0) 105 #define PINMUX_PA05A_RSTC_EXTWAKE5 ((PIN_PA05A_RSTC_EXTWAKE5 << 16) | MUX_PA05A_RSTC_EXTWAKE5) 106 #define PORT_PA05A_RSTC_EXTWAKE5 (_UL(1) << 5) 107 #define PIN_PA06A_RSTC_EXTWAKE6 _L(6) /**< \brief RSTC signal: EXTWAKE6 on PA06 mux A */ 108 #define MUX_PA06A_RSTC_EXTWAKE6 _L(0) 109 #define PINMUX_PA06A_RSTC_EXTWAKE6 ((PIN_PA06A_RSTC_EXTWAKE6 << 16) | MUX_PA06A_RSTC_EXTWAKE6) 110 #define PORT_PA06A_RSTC_EXTWAKE6 (_UL(1) << 6) 111 #define PIN_PA07A_RSTC_EXTWAKE7 _L(7) /**< \brief RSTC signal: EXTWAKE7 on PA07 mux A */ 112 #define MUX_PA07A_RSTC_EXTWAKE7 _L(0) 113 #define PINMUX_PA07A_RSTC_EXTWAKE7 ((PIN_PA07A_RSTC_EXTWAKE7 << 16) | MUX_PA07A_RSTC_EXTWAKE7) 114 #define PORT_PA07A_RSTC_EXTWAKE7 (_UL(1) << 7) 115 /* ========== PORT definition for GCLK peripheral ========== */ 116 #define PIN_PA14H_GCLK_IO0 _L(14) /**< \brief GCLK signal: IO0 on PA14 mux H */ 117 #define MUX_PA14H_GCLK_IO0 _L(7) 118 #define PINMUX_PA14H_GCLK_IO0 ((PIN_PA14H_GCLK_IO0 << 16) | MUX_PA14H_GCLK_IO0) 119 #define PORT_PA14H_GCLK_IO0 (_UL(1) << 14) 120 #define PIN_PA27H_GCLK_IO0 _L(27) /**< \brief GCLK signal: IO0 on PA27 mux H */ 121 #define MUX_PA27H_GCLK_IO0 _L(7) 122 #define PINMUX_PA27H_GCLK_IO0 ((PIN_PA27H_GCLK_IO0 << 16) | MUX_PA27H_GCLK_IO0) 123 #define PORT_PA27H_GCLK_IO0 (_UL(1) << 27) 124 #define PIN_PA30H_GCLK_IO0 _L(30) /**< \brief GCLK signal: IO0 on PA30 mux H */ 125 #define MUX_PA30H_GCLK_IO0 _L(7) 126 #define PINMUX_PA30H_GCLK_IO0 ((PIN_PA30H_GCLK_IO0 << 16) | MUX_PA30H_GCLK_IO0) 127 #define PORT_PA30H_GCLK_IO0 (_UL(1) << 30) 128 #define PIN_PA15H_GCLK_IO1 _L(15) /**< \brief GCLK signal: IO1 on PA15 mux H */ 129 #define MUX_PA15H_GCLK_IO1 _L(7) 130 #define PINMUX_PA15H_GCLK_IO1 ((PIN_PA15H_GCLK_IO1 << 16) | MUX_PA15H_GCLK_IO1) 131 #define PORT_PA15H_GCLK_IO1 (_UL(1) << 15) 132 #define PIN_PA16H_GCLK_IO2 _L(16) /**< \brief GCLK signal: IO2 on PA16 mux H */ 133 #define MUX_PA16H_GCLK_IO2 _L(7) 134 #define PINMUX_PA16H_GCLK_IO2 ((PIN_PA16H_GCLK_IO2 << 16) | MUX_PA16H_GCLK_IO2) 135 #define PORT_PA16H_GCLK_IO2 (_UL(1) << 16) 136 #define PIN_PA17H_GCLK_IO3 _L(17) /**< \brief GCLK signal: IO3 on PA17 mux H */ 137 #define MUX_PA17H_GCLK_IO3 _L(7) 138 #define PINMUX_PA17H_GCLK_IO3 ((PIN_PA17H_GCLK_IO3 << 16) | MUX_PA17H_GCLK_IO3) 139 #define PORT_PA17H_GCLK_IO3 (_UL(1) << 17) 140 #define PIN_PA10H_GCLK_IO4 _L(10) /**< \brief GCLK signal: IO4 on PA10 mux H */ 141 #define MUX_PA10H_GCLK_IO4 _L(7) 142 #define PINMUX_PA10H_GCLK_IO4 ((PIN_PA10H_GCLK_IO4 << 16) | MUX_PA10H_GCLK_IO4) 143 #define PORT_PA10H_GCLK_IO4 (_UL(1) << 10) 144 #define PIN_PA11H_GCLK_IO5 _L(11) /**< \brief GCLK signal: IO5 on PA11 mux H */ 145 #define MUX_PA11H_GCLK_IO5 _L(7) 146 #define PINMUX_PA11H_GCLK_IO5 ((PIN_PA11H_GCLK_IO5 << 16) | MUX_PA11H_GCLK_IO5) 147 #define PORT_PA11H_GCLK_IO5 (_UL(1) << 11) 148 #define PIN_PA22H_GCLK_IO6 _L(22) /**< \brief GCLK signal: IO6 on PA22 mux H */ 149 #define MUX_PA22H_GCLK_IO6 _L(7) 150 #define PINMUX_PA22H_GCLK_IO6 ((PIN_PA22H_GCLK_IO6 << 16) | MUX_PA22H_GCLK_IO6) 151 #define PORT_PA22H_GCLK_IO6 (_UL(1) << 22) 152 #define PIN_PA23H_GCLK_IO7 _L(23) /**< \brief GCLK signal: IO7 on PA23 mux H */ 153 #define MUX_PA23H_GCLK_IO7 _L(7) 154 #define PINMUX_PA23H_GCLK_IO7 ((PIN_PA23H_GCLK_IO7 << 16) | MUX_PA23H_GCLK_IO7) 155 #define PORT_PA23H_GCLK_IO7 (_UL(1) << 23) 156 /* ========== PORT definition for EIC peripheral ========== */ 157 #define PIN_PA16A_EIC_EXTINT0 _L(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ 158 #define MUX_PA16A_EIC_EXTINT0 _L(0) 159 #define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) 160 #define PORT_PA16A_EIC_EXTINT0 (_UL(1) << 16) 161 #define PIN_PA16A_EIC_EXTINT_NUM _L(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ 162 #define PIN_PA00A_EIC_EXTINT0 _L(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ 163 #define MUX_PA00A_EIC_EXTINT0 _L(0) 164 #define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) 165 #define PORT_PA00A_EIC_EXTINT0 (_UL(1) << 0) 166 #define PIN_PA00A_EIC_EXTINT_NUM _L(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ 167 #define PIN_PA17A_EIC_EXTINT1 _L(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ 168 #define MUX_PA17A_EIC_EXTINT1 _L(0) 169 #define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) 170 #define PORT_PA17A_EIC_EXTINT1 (_UL(1) << 17) 171 #define PIN_PA17A_EIC_EXTINT_NUM _L(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ 172 #define PIN_PA01A_EIC_EXTINT1 _L(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ 173 #define MUX_PA01A_EIC_EXTINT1 _L(0) 174 #define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) 175 #define PORT_PA01A_EIC_EXTINT1 (_UL(1) << 1) 176 #define PIN_PA01A_EIC_EXTINT_NUM _L(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ 177 #define PIN_PA02A_EIC_EXTINT2 _L(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ 178 #define MUX_PA02A_EIC_EXTINT2 _L(0) 179 #define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) 180 #define PORT_PA02A_EIC_EXTINT2 (_UL(1) << 2) 181 #define PIN_PA02A_EIC_EXTINT_NUM _L(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ 182 #define PIN_PA18A_EIC_EXTINT2 _L(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ 183 #define MUX_PA18A_EIC_EXTINT2 _L(0) 184 #define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) 185 #define PORT_PA18A_EIC_EXTINT2 (_UL(1) << 18) 186 #define PIN_PA18A_EIC_EXTINT_NUM _L(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ 187 #define PIN_PA03A_EIC_EXTINT3 _L(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ 188 #define MUX_PA03A_EIC_EXTINT3 _L(0) 189 #define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) 190 #define PORT_PA03A_EIC_EXTINT3 (_UL(1) << 3) 191 #define PIN_PA03A_EIC_EXTINT_NUM _L(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ 192 #define PIN_PA19A_EIC_EXTINT3 _L(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ 193 #define MUX_PA19A_EIC_EXTINT3 _L(0) 194 #define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) 195 #define PORT_PA19A_EIC_EXTINT3 (_UL(1) << 19) 196 #define PIN_PA19A_EIC_EXTINT_NUM _L(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ 197 #define PIN_PA04A_EIC_EXTINT4 _L(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ 198 #define MUX_PA04A_EIC_EXTINT4 _L(0) 199 #define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) 200 #define PORT_PA04A_EIC_EXTINT4 (_UL(1) << 4) 201 #define PIN_PA04A_EIC_EXTINT_NUM _L(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ 202 #define PIN_PA05A_EIC_EXTINT5 _L(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ 203 #define MUX_PA05A_EIC_EXTINT5 _L(0) 204 #define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) 205 #define PORT_PA05A_EIC_EXTINT5 (_UL(1) << 5) 206 #define PIN_PA05A_EIC_EXTINT_NUM _L(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ 207 #define PIN_PA06A_EIC_EXTINT6 _L(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ 208 #define MUX_PA06A_EIC_EXTINT6 _L(0) 209 #define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) 210 #define PORT_PA06A_EIC_EXTINT6 (_UL(1) << 6) 211 #define PIN_PA06A_EIC_EXTINT_NUM _L(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ 212 #define PIN_PA22A_EIC_EXTINT6 _L(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ 213 #define MUX_PA22A_EIC_EXTINT6 _L(0) 214 #define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) 215 #define PORT_PA22A_EIC_EXTINT6 (_UL(1) << 22) 216 #define PIN_PA22A_EIC_EXTINT_NUM _L(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ 217 #define PIN_PA07A_EIC_EXTINT7 _L(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ 218 #define MUX_PA07A_EIC_EXTINT7 _L(0) 219 #define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) 220 #define PORT_PA07A_EIC_EXTINT7 (_UL(1) << 7) 221 #define PIN_PA07A_EIC_EXTINT_NUM _L(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ 222 #define PIN_PA23A_EIC_EXTINT7 _L(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ 223 #define MUX_PA23A_EIC_EXTINT7 _L(0) 224 #define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) 225 #define PORT_PA23A_EIC_EXTINT7 (_UL(1) << 23) 226 #define PIN_PA23A_EIC_EXTINT_NUM _L(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ 227 #define PIN_PA09A_EIC_EXTINT9 _L(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ 228 #define MUX_PA09A_EIC_EXTINT9 _L(0) 229 #define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) 230 #define PORT_PA09A_EIC_EXTINT9 (_UL(1) << 9) 231 #define PIN_PA09A_EIC_EXTINT_NUM _L(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ 232 #define PIN_PA10A_EIC_EXTINT10 _L(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ 233 #define MUX_PA10A_EIC_EXTINT10 _L(0) 234 #define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) 235 #define PORT_PA10A_EIC_EXTINT10 (_UL(1) << 10) 236 #define PIN_PA10A_EIC_EXTINT_NUM _L(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ 237 #define PIN_PA30A_EIC_EXTINT10 _L(30) /**< \brief EIC signal: EXTINT10 on PA30 mux A */ 238 #define MUX_PA30A_EIC_EXTINT10 _L(0) 239 #define PINMUX_PA30A_EIC_EXTINT10 ((PIN_PA30A_EIC_EXTINT10 << 16) | MUX_PA30A_EIC_EXTINT10) 240 #define PORT_PA30A_EIC_EXTINT10 (_UL(1) << 30) 241 #define PIN_PA30A_EIC_EXTINT_NUM _L(10) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ 242 #define PIN_PA11A_EIC_EXTINT11 _L(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ 243 #define MUX_PA11A_EIC_EXTINT11 _L(0) 244 #define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) 245 #define PORT_PA11A_EIC_EXTINT11 (_UL(1) << 11) 246 #define PIN_PA11A_EIC_EXTINT_NUM _L(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ 247 #define PIN_PA31A_EIC_EXTINT11 _L(31) /**< \brief EIC signal: EXTINT11 on PA31 mux A */ 248 #define MUX_PA31A_EIC_EXTINT11 _L(0) 249 #define PINMUX_PA31A_EIC_EXTINT11 ((PIN_PA31A_EIC_EXTINT11 << 16) | MUX_PA31A_EIC_EXTINT11) 250 #define PORT_PA31A_EIC_EXTINT11 (_UL(1) << 31) 251 #define PIN_PA31A_EIC_EXTINT_NUM _L(11) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ 252 #define PIN_PA24A_EIC_EXTINT12 _L(24) /**< \brief EIC signal: EXTINT12 on PA24 mux A */ 253 #define MUX_PA24A_EIC_EXTINT12 _L(0) 254 #define PINMUX_PA24A_EIC_EXTINT12 ((PIN_PA24A_EIC_EXTINT12 << 16) | MUX_PA24A_EIC_EXTINT12) 255 #define PORT_PA24A_EIC_EXTINT12 (_UL(1) << 24) 256 #define PIN_PA24A_EIC_EXTINT_NUM _L(12) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ 257 #define PIN_PA25A_EIC_EXTINT13 _L(25) /**< \brief EIC signal: EXTINT13 on PA25 mux A */ 258 #define MUX_PA25A_EIC_EXTINT13 _L(0) 259 #define PINMUX_PA25A_EIC_EXTINT13 ((PIN_PA25A_EIC_EXTINT13 << 16) | MUX_PA25A_EIC_EXTINT13) 260 #define PORT_PA25A_EIC_EXTINT13 (_UL(1) << 25) 261 #define PIN_PA25A_EIC_EXTINT_NUM _L(13) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ 262 #define PIN_PA14A_EIC_EXTINT14 _L(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ 263 #define MUX_PA14A_EIC_EXTINT14 _L(0) 264 #define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) 265 #define PORT_PA14A_EIC_EXTINT14 (_UL(1) << 14) 266 #define PIN_PA14A_EIC_EXTINT_NUM _L(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ 267 #define PIN_PA27A_EIC_EXTINT15 _L(27) /**< \brief EIC signal: EXTINT15 on PA27 mux A */ 268 #define MUX_PA27A_EIC_EXTINT15 _L(0) 269 #define PINMUX_PA27A_EIC_EXTINT15 ((PIN_PA27A_EIC_EXTINT15 << 16) | MUX_PA27A_EIC_EXTINT15) 270 #define PORT_PA27A_EIC_EXTINT15 (_UL(1) << 27) 271 #define PIN_PA27A_EIC_EXTINT_NUM _L(15) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ 272 #define PIN_PA15A_EIC_EXTINT15 _L(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ 273 #define MUX_PA15A_EIC_EXTINT15 _L(0) 274 #define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) 275 #define PORT_PA15A_EIC_EXTINT15 (_UL(1) << 15) 276 #define PIN_PA15A_EIC_EXTINT_NUM _L(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ 277 #define PIN_PA08A_EIC_NMI _L(8) /**< \brief EIC signal: NMI on PA08 mux A */ 278 #define MUX_PA08A_EIC_NMI _L(0) 279 #define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) 280 #define PORT_PA08A_EIC_NMI (_UL(1) << 8) 281 /* ========== PORT definition for TAL peripheral ========== */ 282 #define PIN_PA27G_TAL_BRK _L(27) /**< \brief TAL signal: BRK on PA27 mux G */ 283 #define MUX_PA27G_TAL_BRK _L(6) 284 #define PINMUX_PA27G_TAL_BRK ((PIN_PA27G_TAL_BRK << 16) | MUX_PA27G_TAL_BRK) 285 #define PORT_PA27G_TAL_BRK (_UL(1) << 27) 286 /* ========== PORT definition for USB peripheral ========== */ 287 #define PIN_PA24G_USB_DM _L(24) /**< \brief USB signal: DM on PA24 mux G */ 288 #define MUX_PA24G_USB_DM _L(6) 289 #define PINMUX_PA24G_USB_DM ((PIN_PA24G_USB_DM << 16) | MUX_PA24G_USB_DM) 290 #define PORT_PA24G_USB_DM (_UL(1) << 24) 291 #define PIN_PA25G_USB_DP _L(25) /**< \brief USB signal: DP on PA25 mux G */ 292 #define MUX_PA25G_USB_DP _L(6) 293 #define PINMUX_PA25G_USB_DP ((PIN_PA25G_USB_DP << 16) | MUX_PA25G_USB_DP) 294 #define PORT_PA25G_USB_DP (_UL(1) << 25) 295 #define PIN_PA23G_USB_SOF_1KHZ _L(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux G */ 296 #define MUX_PA23G_USB_SOF_1KHZ _L(6) 297 #define PINMUX_PA23G_USB_SOF_1KHZ ((PIN_PA23G_USB_SOF_1KHZ << 16) | MUX_PA23G_USB_SOF_1KHZ) 298 #define PORT_PA23G_USB_SOF_1KHZ (_UL(1) << 23) 299 /* ========== PORT definition for SERCOM0 peripheral ========== */ 300 #define PIN_PA04D_SERCOM0_PAD0 _L(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ 301 #define MUX_PA04D_SERCOM0_PAD0 _L(3) 302 #define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) 303 #define PORT_PA04D_SERCOM0_PAD0 (_UL(1) << 4) 304 #define PIN_PA08C_SERCOM0_PAD0 _L(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ 305 #define MUX_PA08C_SERCOM0_PAD0 _L(2) 306 #define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) 307 #define PORT_PA08C_SERCOM0_PAD0 (_UL(1) << 8) 308 #define PIN_PA05D_SERCOM0_PAD1 _L(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ 309 #define MUX_PA05D_SERCOM0_PAD1 _L(3) 310 #define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) 311 #define PORT_PA05D_SERCOM0_PAD1 (_UL(1) << 5) 312 #define PIN_PA09C_SERCOM0_PAD1 _L(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ 313 #define MUX_PA09C_SERCOM0_PAD1 _L(2) 314 #define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) 315 #define PORT_PA09C_SERCOM0_PAD1 (_UL(1) << 9) 316 #define PIN_PA06D_SERCOM0_PAD2 _L(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ 317 #define MUX_PA06D_SERCOM0_PAD2 _L(3) 318 #define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) 319 #define PORT_PA06D_SERCOM0_PAD2 (_UL(1) << 6) 320 #define PIN_PA10C_SERCOM0_PAD2 _L(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ 321 #define MUX_PA10C_SERCOM0_PAD2 _L(2) 322 #define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) 323 #define PORT_PA10C_SERCOM0_PAD2 (_UL(1) << 10) 324 #define PIN_PA07D_SERCOM0_PAD3 _L(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ 325 #define MUX_PA07D_SERCOM0_PAD3 _L(3) 326 #define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) 327 #define PORT_PA07D_SERCOM0_PAD3 (_UL(1) << 7) 328 #define PIN_PA11C_SERCOM0_PAD3 _L(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ 329 #define MUX_PA11C_SERCOM0_PAD3 _L(2) 330 #define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) 331 #define PORT_PA11C_SERCOM0_PAD3 (_UL(1) << 11) 332 /* ========== PORT definition for SERCOM1 peripheral ========== */ 333 #define PIN_PA16C_SERCOM1_PAD0 _L(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ 334 #define MUX_PA16C_SERCOM1_PAD0 _L(2) 335 #define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) 336 #define PORT_PA16C_SERCOM1_PAD0 (_UL(1) << 16) 337 #define PIN_PA00D_SERCOM1_PAD0 _L(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ 338 #define MUX_PA00D_SERCOM1_PAD0 _L(3) 339 #define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) 340 #define PORT_PA00D_SERCOM1_PAD0 (_UL(1) << 0) 341 #define PIN_PA17C_SERCOM1_PAD1 _L(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ 342 #define MUX_PA17C_SERCOM1_PAD1 _L(2) 343 #define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) 344 #define PORT_PA17C_SERCOM1_PAD1 (_UL(1) << 17) 345 #define PIN_PA01D_SERCOM1_PAD1 _L(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ 346 #define MUX_PA01D_SERCOM1_PAD1 _L(3) 347 #define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) 348 #define PORT_PA01D_SERCOM1_PAD1 (_UL(1) << 1) 349 #define PIN_PA30D_SERCOM1_PAD2 _L(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ 350 #define MUX_PA30D_SERCOM1_PAD2 _L(3) 351 #define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) 352 #define PORT_PA30D_SERCOM1_PAD2 (_UL(1) << 30) 353 #define PIN_PA18C_SERCOM1_PAD2 _L(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ 354 #define MUX_PA18C_SERCOM1_PAD2 _L(2) 355 #define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) 356 #define PORT_PA18C_SERCOM1_PAD2 (_UL(1) << 18) 357 #define PIN_PA31D_SERCOM1_PAD3 _L(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ 358 #define MUX_PA31D_SERCOM1_PAD3 _L(3) 359 #define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) 360 #define PORT_PA31D_SERCOM1_PAD3 (_UL(1) << 31) 361 #define PIN_PA19C_SERCOM1_PAD3 _L(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ 362 #define MUX_PA19C_SERCOM1_PAD3 _L(2) 363 #define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) 364 #define PORT_PA19C_SERCOM1_PAD3 (_UL(1) << 19) 365 /* ========== PORT definition for SERCOM2 peripheral ========== */ 366 #define PIN_PA08D_SERCOM2_PAD0 _L(8) /**< \brief SERCOM2 signal: PAD0 on PA08 mux D */ 367 #define MUX_PA08D_SERCOM2_PAD0 _L(3) 368 #define PINMUX_PA08D_SERCOM2_PAD0 ((PIN_PA08D_SERCOM2_PAD0 << 16) | MUX_PA08D_SERCOM2_PAD0) 369 #define PORT_PA08D_SERCOM2_PAD0 (_UL(1) << 8) 370 #define PIN_PA09D_SERCOM2_PAD1 _L(9) /**< \brief SERCOM2 signal: PAD1 on PA09 mux D */ 371 #define MUX_PA09D_SERCOM2_PAD1 _L(3) 372 #define PINMUX_PA09D_SERCOM2_PAD1 ((PIN_PA09D_SERCOM2_PAD1 << 16) | MUX_PA09D_SERCOM2_PAD1) 373 #define PORT_PA09D_SERCOM2_PAD1 (_UL(1) << 9) 374 #define PIN_PA10D_SERCOM2_PAD2 _L(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ 375 #define MUX_PA10D_SERCOM2_PAD2 _L(3) 376 #define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) 377 #define PORT_PA10D_SERCOM2_PAD2 (_UL(1) << 10) 378 #define PIN_PA14C_SERCOM2_PAD2 _L(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ 379 #define MUX_PA14C_SERCOM2_PAD2 _L(2) 380 #define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) 381 #define PORT_PA14C_SERCOM2_PAD2 (_UL(1) << 14) 382 #define PIN_PA11D_SERCOM2_PAD3 _L(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ 383 #define MUX_PA11D_SERCOM2_PAD3 _L(3) 384 #define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) 385 #define PORT_PA11D_SERCOM2_PAD3 (_UL(1) << 11) 386 #define PIN_PA15C_SERCOM2_PAD3 _L(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ 387 #define MUX_PA15C_SERCOM2_PAD3 _L(2) 388 #define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) 389 #define PORT_PA15C_SERCOM2_PAD3 (_UL(1) << 15) 390 /* ========== PORT definition for SERCOM3 peripheral ========== */ 391 #define PIN_PA16D_SERCOM3_PAD0 _L(16) /**< \brief SERCOM3 signal: PAD0 on PA16 mux D */ 392 #define MUX_PA16D_SERCOM3_PAD0 _L(3) 393 #define PINMUX_PA16D_SERCOM3_PAD0 ((PIN_PA16D_SERCOM3_PAD0 << 16) | MUX_PA16D_SERCOM3_PAD0) 394 #define PORT_PA16D_SERCOM3_PAD0 (_UL(1) << 16) 395 #define PIN_PA22C_SERCOM3_PAD0 _L(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ 396 #define MUX_PA22C_SERCOM3_PAD0 _L(2) 397 #define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) 398 #define PORT_PA22C_SERCOM3_PAD0 (_UL(1) << 22) 399 #define PIN_PA17D_SERCOM3_PAD1 _L(17) /**< \brief SERCOM3 signal: PAD1 on PA17 mux D */ 400 #define MUX_PA17D_SERCOM3_PAD1 _L(3) 401 #define PINMUX_PA17D_SERCOM3_PAD1 ((PIN_PA17D_SERCOM3_PAD1 << 16) | MUX_PA17D_SERCOM3_PAD1) 402 #define PORT_PA17D_SERCOM3_PAD1 (_UL(1) << 17) 403 #define PIN_PA23C_SERCOM3_PAD1 _L(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ 404 #define MUX_PA23C_SERCOM3_PAD1 _L(2) 405 #define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) 406 #define PORT_PA23C_SERCOM3_PAD1 (_UL(1) << 23) 407 #define PIN_PA18D_SERCOM3_PAD2 _L(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ 408 #define MUX_PA18D_SERCOM3_PAD2 _L(3) 409 #define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) 410 #define PORT_PA18D_SERCOM3_PAD2 (_UL(1) << 18) 411 #define PIN_PA24C_SERCOM3_PAD2 _L(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ 412 #define MUX_PA24C_SERCOM3_PAD2 _L(2) 413 #define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) 414 #define PORT_PA24C_SERCOM3_PAD2 (_UL(1) << 24) 415 #define PIN_PA19D_SERCOM3_PAD3 _L(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ 416 #define MUX_PA19D_SERCOM3_PAD3 _L(3) 417 #define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) 418 #define PORT_PA19D_SERCOM3_PAD3 (_UL(1) << 19) 419 #define PIN_PA25C_SERCOM3_PAD3 _L(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ 420 #define MUX_PA25C_SERCOM3_PAD3 _L(2) 421 #define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) 422 #define PORT_PA25C_SERCOM3_PAD3 (_UL(1) << 25) 423 /* ========== PORT definition for SERCOM4 peripheral ========== */ 424 #define PIN_PA14D_SERCOM4_PAD2 _L(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ 425 #define MUX_PA14D_SERCOM4_PAD2 _L(3) 426 #define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) 427 #define PORT_PA14D_SERCOM4_PAD2 (_UL(1) << 14) 428 #define PIN_PA15D_SERCOM4_PAD3 _L(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ 429 #define MUX_PA15D_SERCOM4_PAD3 _L(3) 430 #define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) 431 #define PORT_PA15D_SERCOM4_PAD3 (_UL(1) << 15) 432 /* ========== PORT definition for TCC0 peripheral ========== */ 433 #define PIN_PA04E_TCC0_WO0 _L(4) /**< \brief TCC0 signal: WO0 on PA04 mux E */ 434 #define MUX_PA04E_TCC0_WO0 _L(4) 435 #define PINMUX_PA04E_TCC0_WO0 ((PIN_PA04E_TCC0_WO0 << 16) | MUX_PA04E_TCC0_WO0) 436 #define PORT_PA04E_TCC0_WO0 (_UL(1) << 4) 437 #define PIN_PA08E_TCC0_WO0 _L(8) /**< \brief TCC0 signal: WO0 on PA08 mux E */ 438 #define MUX_PA08E_TCC0_WO0 _L(4) 439 #define PINMUX_PA08E_TCC0_WO0 ((PIN_PA08E_TCC0_WO0 << 16) | MUX_PA08E_TCC0_WO0) 440 #define PORT_PA08E_TCC0_WO0 (_UL(1) << 8) 441 #define PIN_PA05E_TCC0_WO1 _L(5) /**< \brief TCC0 signal: WO1 on PA05 mux E */ 442 #define MUX_PA05E_TCC0_WO1 _L(4) 443 #define PINMUX_PA05E_TCC0_WO1 ((PIN_PA05E_TCC0_WO1 << 16) | MUX_PA05E_TCC0_WO1) 444 #define PORT_PA05E_TCC0_WO1 (_UL(1) << 5) 445 #define PIN_PA09E_TCC0_WO1 _L(9) /**< \brief TCC0 signal: WO1 on PA09 mux E */ 446 #define MUX_PA09E_TCC0_WO1 _L(4) 447 #define PINMUX_PA09E_TCC0_WO1 ((PIN_PA09E_TCC0_WO1 << 16) | MUX_PA09E_TCC0_WO1) 448 #define PORT_PA09E_TCC0_WO1 (_UL(1) << 9) 449 #define PIN_PA10F_TCC0_WO2 _L(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ 450 #define MUX_PA10F_TCC0_WO2 _L(5) 451 #define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) 452 #define PORT_PA10F_TCC0_WO2 (_UL(1) << 10) 453 #define PIN_PA18F_TCC0_WO2 _L(18) /**< \brief TCC0 signal: WO2 on PA18 mux F */ 454 #define MUX_PA18F_TCC0_WO2 _L(5) 455 #define PINMUX_PA18F_TCC0_WO2 ((PIN_PA18F_TCC0_WO2 << 16) | MUX_PA18F_TCC0_WO2) 456 #define PORT_PA18F_TCC0_WO2 (_UL(1) << 18) 457 #define PIN_PA11F_TCC0_WO3 _L(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ 458 #define MUX_PA11F_TCC0_WO3 _L(5) 459 #define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) 460 #define PORT_PA11F_TCC0_WO3 (_UL(1) << 11) 461 #define PIN_PA19F_TCC0_WO3 _L(19) /**< \brief TCC0 signal: WO3 on PA19 mux F */ 462 #define MUX_PA19F_TCC0_WO3 _L(5) 463 #define PINMUX_PA19F_TCC0_WO3 ((PIN_PA19F_TCC0_WO3 << 16) | MUX_PA19F_TCC0_WO3) 464 #define PORT_PA19F_TCC0_WO3 (_UL(1) << 19) 465 #define PIN_PA22F_TCC0_WO4 _L(22) /**< \brief TCC0 signal: WO4 on PA22 mux F */ 466 #define MUX_PA22F_TCC0_WO4 _L(5) 467 #define PINMUX_PA22F_TCC0_WO4 ((PIN_PA22F_TCC0_WO4 << 16) | MUX_PA22F_TCC0_WO4) 468 #define PORT_PA22F_TCC0_WO4 (_UL(1) << 22) 469 #define PIN_PA14F_TCC0_WO4 _L(14) /**< \brief TCC0 signal: WO4 on PA14 mux F */ 470 #define MUX_PA14F_TCC0_WO4 _L(5) 471 #define PINMUX_PA14F_TCC0_WO4 ((PIN_PA14F_TCC0_WO4 << 16) | MUX_PA14F_TCC0_WO4) 472 #define PORT_PA14F_TCC0_WO4 (_UL(1) << 14) 473 #define PIN_PA15F_TCC0_WO5 _L(15) /**< \brief TCC0 signal: WO5 on PA15 mux F */ 474 #define MUX_PA15F_TCC0_WO5 _L(5) 475 #define PINMUX_PA15F_TCC0_WO5 ((PIN_PA15F_TCC0_WO5 << 16) | MUX_PA15F_TCC0_WO5) 476 #define PORT_PA15F_TCC0_WO5 (_UL(1) << 15) 477 #define PIN_PA23F_TCC0_WO5 _L(23) /**< \brief TCC0 signal: WO5 on PA23 mux F */ 478 #define MUX_PA23F_TCC0_WO5 _L(5) 479 #define PINMUX_PA23F_TCC0_WO5 ((PIN_PA23F_TCC0_WO5 << 16) | MUX_PA23F_TCC0_WO5) 480 #define PORT_PA23F_TCC0_WO5 (_UL(1) << 23) 481 #define PIN_PA16F_TCC0_WO6 _L(16) /**< \brief TCC0 signal: WO6 on PA16 mux F */ 482 #define MUX_PA16F_TCC0_WO6 _L(5) 483 #define PINMUX_PA16F_TCC0_WO6 ((PIN_PA16F_TCC0_WO6 << 16) | MUX_PA16F_TCC0_WO6) 484 #define PORT_PA16F_TCC0_WO6 (_UL(1) << 16) 485 #define PIN_PA17F_TCC0_WO7 _L(17) /**< \brief TCC0 signal: WO7 on PA17 mux F */ 486 #define MUX_PA17F_TCC0_WO7 _L(5) 487 #define PINMUX_PA17F_TCC0_WO7 ((PIN_PA17F_TCC0_WO7 << 16) | MUX_PA17F_TCC0_WO7) 488 #define PORT_PA17F_TCC0_WO7 (_UL(1) << 17) 489 /* ========== PORT definition for TCC1 peripheral ========== */ 490 #define PIN_PA06E_TCC1_WO0 _L(6) /**< \brief TCC1 signal: WO0 on PA06 mux E */ 491 #define MUX_PA06E_TCC1_WO0 _L(4) 492 #define PINMUX_PA06E_TCC1_WO0 ((PIN_PA06E_TCC1_WO0 << 16) | MUX_PA06E_TCC1_WO0) 493 #define PORT_PA06E_TCC1_WO0 (_UL(1) << 6) 494 #define PIN_PA10E_TCC1_WO0 _L(10) /**< \brief TCC1 signal: WO0 on PA10 mux E */ 495 #define MUX_PA10E_TCC1_WO0 _L(4) 496 #define PINMUX_PA10E_TCC1_WO0 ((PIN_PA10E_TCC1_WO0 << 16) | MUX_PA10E_TCC1_WO0) 497 #define PORT_PA10E_TCC1_WO0 (_UL(1) << 10) 498 #define PIN_PA30E_TCC1_WO0 _L(30) /**< \brief TCC1 signal: WO0 on PA30 mux E */ 499 #define MUX_PA30E_TCC1_WO0 _L(4) 500 #define PINMUX_PA30E_TCC1_WO0 ((PIN_PA30E_TCC1_WO0 << 16) | MUX_PA30E_TCC1_WO0) 501 #define PORT_PA30E_TCC1_WO0 (_UL(1) << 30) 502 #define PIN_PA07E_TCC1_WO1 _L(7) /**< \brief TCC1 signal: WO1 on PA07 mux E */ 503 #define MUX_PA07E_TCC1_WO1 _L(4) 504 #define PINMUX_PA07E_TCC1_WO1 ((PIN_PA07E_TCC1_WO1 << 16) | MUX_PA07E_TCC1_WO1) 505 #define PORT_PA07E_TCC1_WO1 (_UL(1) << 7) 506 #define PIN_PA11E_TCC1_WO1 _L(11) /**< \brief TCC1 signal: WO1 on PA11 mux E */ 507 #define MUX_PA11E_TCC1_WO1 _L(4) 508 #define PINMUX_PA11E_TCC1_WO1 ((PIN_PA11E_TCC1_WO1 << 16) | MUX_PA11E_TCC1_WO1) 509 #define PORT_PA11E_TCC1_WO1 (_UL(1) << 11) 510 #define PIN_PA31E_TCC1_WO1 _L(31) /**< \brief TCC1 signal: WO1 on PA31 mux E */ 511 #define MUX_PA31E_TCC1_WO1 _L(4) 512 #define PINMUX_PA31E_TCC1_WO1 ((PIN_PA31E_TCC1_WO1 << 16) | MUX_PA31E_TCC1_WO1) 513 #define PORT_PA31E_TCC1_WO1 (_UL(1) << 31) 514 #define PIN_PA08F_TCC1_WO2 _L(8) /**< \brief TCC1 signal: WO2 on PA08 mux F */ 515 #define MUX_PA08F_TCC1_WO2 _L(5) 516 #define PINMUX_PA08F_TCC1_WO2 ((PIN_PA08F_TCC1_WO2 << 16) | MUX_PA08F_TCC1_WO2) 517 #define PORT_PA08F_TCC1_WO2 (_UL(1) << 8) 518 #define PIN_PA24F_TCC1_WO2 _L(24) /**< \brief TCC1 signal: WO2 on PA24 mux F */ 519 #define MUX_PA24F_TCC1_WO2 _L(5) 520 #define PINMUX_PA24F_TCC1_WO2 ((PIN_PA24F_TCC1_WO2 << 16) | MUX_PA24F_TCC1_WO2) 521 #define PORT_PA24F_TCC1_WO2 (_UL(1) << 24) 522 #define PIN_PA09F_TCC1_WO3 _L(9) /**< \brief TCC1 signal: WO3 on PA09 mux F */ 523 #define MUX_PA09F_TCC1_WO3 _L(5) 524 #define PINMUX_PA09F_TCC1_WO3 ((PIN_PA09F_TCC1_WO3 << 16) | MUX_PA09F_TCC1_WO3) 525 #define PORT_PA09F_TCC1_WO3 (_UL(1) << 9) 526 #define PIN_PA25F_TCC1_WO3 _L(25) /**< \brief TCC1 signal: WO3 on PA25 mux F */ 527 #define MUX_PA25F_TCC1_WO3 _L(5) 528 #define PINMUX_PA25F_TCC1_WO3 ((PIN_PA25F_TCC1_WO3 << 16) | MUX_PA25F_TCC1_WO3) 529 #define PORT_PA25F_TCC1_WO3 (_UL(1) << 25) 530 /* ========== PORT definition for TCC2 peripheral ========== */ 531 #define PIN_PA16E_TCC2_WO0 _L(16) /**< \brief TCC2 signal: WO0 on PA16 mux E */ 532 #define MUX_PA16E_TCC2_WO0 _L(4) 533 #define PINMUX_PA16E_TCC2_WO0 ((PIN_PA16E_TCC2_WO0 << 16) | MUX_PA16E_TCC2_WO0) 534 #define PORT_PA16E_TCC2_WO0 (_UL(1) << 16) 535 #define PIN_PA00E_TCC2_WO0 _L(0) /**< \brief TCC2 signal: WO0 on PA00 mux E */ 536 #define MUX_PA00E_TCC2_WO0 _L(4) 537 #define PINMUX_PA00E_TCC2_WO0 ((PIN_PA00E_TCC2_WO0 << 16) | MUX_PA00E_TCC2_WO0) 538 #define PORT_PA00E_TCC2_WO0 (_UL(1) << 0) 539 #define PIN_PA17E_TCC2_WO1 _L(17) /**< \brief TCC2 signal: WO1 on PA17 mux E */ 540 #define MUX_PA17E_TCC2_WO1 _L(4) 541 #define PINMUX_PA17E_TCC2_WO1 ((PIN_PA17E_TCC2_WO1 << 16) | MUX_PA17E_TCC2_WO1) 542 #define PORT_PA17E_TCC2_WO1 (_UL(1) << 17) 543 #define PIN_PA01E_TCC2_WO1 _L(1) /**< \brief TCC2 signal: WO1 on PA01 mux E */ 544 #define MUX_PA01E_TCC2_WO1 _L(4) 545 #define PINMUX_PA01E_TCC2_WO1 ((PIN_PA01E_TCC2_WO1 << 16) | MUX_PA01E_TCC2_WO1) 546 #define PORT_PA01E_TCC2_WO1 (_UL(1) << 1) 547 /* ========== PORT definition for TC0 peripheral ========== */ 548 #define PIN_PA22E_TC0_WO0 _L(22) /**< \brief TC0 signal: WO0 on PA22 mux E */ 549 #define MUX_PA22E_TC0_WO0 _L(4) 550 #define PINMUX_PA22E_TC0_WO0 ((PIN_PA22E_TC0_WO0 << 16) | MUX_PA22E_TC0_WO0) 551 #define PORT_PA22E_TC0_WO0 (_UL(1) << 22) 552 #define PIN_PA23E_TC0_WO1 _L(23) /**< \brief TC0 signal: WO1 on PA23 mux E */ 553 #define MUX_PA23E_TC0_WO1 _L(4) 554 #define PINMUX_PA23E_TC0_WO1 ((PIN_PA23E_TC0_WO1 << 16) | MUX_PA23E_TC0_WO1) 555 #define PORT_PA23E_TC0_WO1 (_UL(1) << 23) 556 /* ========== PORT definition for TC1 peripheral ========== */ 557 #define PIN_PA24E_TC1_WO0 _L(24) /**< \brief TC1 signal: WO0 on PA24 mux E */ 558 #define MUX_PA24E_TC1_WO0 _L(4) 559 #define PINMUX_PA24E_TC1_WO0 ((PIN_PA24E_TC1_WO0 << 16) | MUX_PA24E_TC1_WO0) 560 #define PORT_PA24E_TC1_WO0 (_UL(1) << 24) 561 #define PIN_PA25E_TC1_WO1 _L(25) /**< \brief TC1 signal: WO1 on PA25 mux E */ 562 #define MUX_PA25E_TC1_WO1 _L(4) 563 #define PINMUX_PA25E_TC1_WO1 ((PIN_PA25E_TC1_WO1 << 16) | MUX_PA25E_TC1_WO1) 564 #define PORT_PA25E_TC1_WO1 (_UL(1) << 25) 565 /* ========== PORT definition for DAC peripheral ========== */ 566 #define PIN_PA02B_DAC_VOUT0 _L(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ 567 #define MUX_PA02B_DAC_VOUT0 _L(1) 568 #define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) 569 #define PORT_PA02B_DAC_VOUT0 (_UL(1) << 2) 570 #define PIN_PA05B_DAC_VOUT1 _L(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ 571 #define MUX_PA05B_DAC_VOUT1 _L(1) 572 #define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) 573 #define PORT_PA05B_DAC_VOUT1 (_UL(1) << 5) 574 #define PIN_PA03B_DAC_VREFP _L(3) /**< \brief DAC signal: VREFP on PA03 mux B */ 575 #define MUX_PA03B_DAC_VREFP _L(1) 576 #define PINMUX_PA03B_DAC_VREFP ((PIN_PA03B_DAC_VREFP << 16) | MUX_PA03B_DAC_VREFP) 577 #define PORT_PA03B_DAC_VREFP (_UL(1) << 3) 578 /* ========== PORT definition for SERCOM5 peripheral ========== */ 579 #define PIN_PA22D_SERCOM5_PAD0 _L(22) /**< \brief SERCOM5 signal: PAD0 on PA22 mux D */ 580 #define MUX_PA22D_SERCOM5_PAD0 _L(3) 581 #define PINMUX_PA22D_SERCOM5_PAD0 ((PIN_PA22D_SERCOM5_PAD0 << 16) | MUX_PA22D_SERCOM5_PAD0) 582 #define PORT_PA22D_SERCOM5_PAD0 (_UL(1) << 22) 583 #define PIN_PA23D_SERCOM5_PAD1 _L(23) /**< \brief SERCOM5 signal: PAD1 on PA23 mux D */ 584 #define MUX_PA23D_SERCOM5_PAD1 _L(3) 585 #define PINMUX_PA23D_SERCOM5_PAD1 ((PIN_PA23D_SERCOM5_PAD1 << 16) | MUX_PA23D_SERCOM5_PAD1) 586 #define PORT_PA23D_SERCOM5_PAD1 (_UL(1) << 23) 587 #define PIN_PA24D_SERCOM5_PAD2 _L(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ 588 #define MUX_PA24D_SERCOM5_PAD2 _L(3) 589 #define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) 590 #define PORT_PA24D_SERCOM5_PAD2 (_UL(1) << 24) 591 #define PIN_PA25D_SERCOM5_PAD3 _L(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ 592 #define MUX_PA25D_SERCOM5_PAD3 _L(3) 593 #define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) 594 #define PORT_PA25D_SERCOM5_PAD3 (_UL(1) << 25) 595 /* ========== PORT definition for TC4 peripheral ========== */ 596 #define PIN_PA18E_TC4_WO0 _L(18) /**< \brief TC4 signal: WO0 on PA18 mux E */ 597 #define MUX_PA18E_TC4_WO0 _L(4) 598 #define PINMUX_PA18E_TC4_WO0 ((PIN_PA18E_TC4_WO0 << 16) | MUX_PA18E_TC4_WO0) 599 #define PORT_PA18E_TC4_WO0 (_UL(1) << 18) 600 #define PIN_PA14E_TC4_WO0 _L(14) /**< \brief TC4 signal: WO0 on PA14 mux E */ 601 #define MUX_PA14E_TC4_WO0 _L(4) 602 #define PINMUX_PA14E_TC4_WO0 ((PIN_PA14E_TC4_WO0 << 16) | MUX_PA14E_TC4_WO0) 603 #define PORT_PA14E_TC4_WO0 (_UL(1) << 14) 604 #define PIN_PA19E_TC4_WO1 _L(19) /**< \brief TC4 signal: WO1 on PA19 mux E */ 605 #define MUX_PA19E_TC4_WO1 _L(4) 606 #define PINMUX_PA19E_TC4_WO1 ((PIN_PA19E_TC4_WO1 << 16) | MUX_PA19E_TC4_WO1) 607 #define PORT_PA19E_TC4_WO1 (_UL(1) << 19) 608 #define PIN_PA15E_TC4_WO1 _L(15) /**< \brief TC4 signal: WO1 on PA15 mux E */ 609 #define MUX_PA15E_TC4_WO1 _L(4) 610 #define PINMUX_PA15E_TC4_WO1 ((PIN_PA15E_TC4_WO1 << 16) | MUX_PA15E_TC4_WO1) 611 #define PORT_PA15E_TC4_WO1 (_UL(1) << 15) 612 /* ========== PORT definition for ADC peripheral ========== */ 613 #define PIN_PA02B_ADC_AIN0 _L(2) /**< \brief ADC signal: AIN0 on PA02 mux B */ 614 #define MUX_PA02B_ADC_AIN0 _L(1) 615 #define PINMUX_PA02B_ADC_AIN0 ((PIN_PA02B_ADC_AIN0 << 16) | MUX_PA02B_ADC_AIN0) 616 #define PORT_PA02B_ADC_AIN0 (_UL(1) << 2) 617 #define PIN_PA03B_ADC_AIN1 _L(3) /**< \brief ADC signal: AIN1 on PA03 mux B */ 618 #define MUX_PA03B_ADC_AIN1 _L(1) 619 #define PINMUX_PA03B_ADC_AIN1 ((PIN_PA03B_ADC_AIN1 << 16) | MUX_PA03B_ADC_AIN1) 620 #define PORT_PA03B_ADC_AIN1 (_UL(1) << 3) 621 #define PIN_PA04B_ADC_AIN4 _L(4) /**< \brief ADC signal: AIN4 on PA04 mux B */ 622 #define MUX_PA04B_ADC_AIN4 _L(1) 623 #define PINMUX_PA04B_ADC_AIN4 ((PIN_PA04B_ADC_AIN4 << 16) | MUX_PA04B_ADC_AIN4) 624 #define PORT_PA04B_ADC_AIN4 (_UL(1) << 4) 625 #define PIN_PA05B_ADC_AIN5 _L(5) /**< \brief ADC signal: AIN5 on PA05 mux B */ 626 #define MUX_PA05B_ADC_AIN5 _L(1) 627 #define PINMUX_PA05B_ADC_AIN5 ((PIN_PA05B_ADC_AIN5 << 16) | MUX_PA05B_ADC_AIN5) 628 #define PORT_PA05B_ADC_AIN5 (_UL(1) << 5) 629 #define PIN_PA06B_ADC_AIN6 _L(6) /**< \brief ADC signal: AIN6 on PA06 mux B */ 630 #define MUX_PA06B_ADC_AIN6 _L(1) 631 #define PINMUX_PA06B_ADC_AIN6 ((PIN_PA06B_ADC_AIN6 << 16) | MUX_PA06B_ADC_AIN6) 632 #define PORT_PA06B_ADC_AIN6 (_UL(1) << 6) 633 #define PIN_PA07B_ADC_AIN7 _L(7) /**< \brief ADC signal: AIN7 on PA07 mux B */ 634 #define MUX_PA07B_ADC_AIN7 _L(1) 635 #define PINMUX_PA07B_ADC_AIN7 ((PIN_PA07B_ADC_AIN7 << 16) | MUX_PA07B_ADC_AIN7) 636 #define PORT_PA07B_ADC_AIN7 (_UL(1) << 7) 637 #define PIN_PA08B_ADC_AIN16 _L(8) /**< \brief ADC signal: AIN16 on PA08 mux B */ 638 #define MUX_PA08B_ADC_AIN16 _L(1) 639 #define PINMUX_PA08B_ADC_AIN16 ((PIN_PA08B_ADC_AIN16 << 16) | MUX_PA08B_ADC_AIN16) 640 #define PORT_PA08B_ADC_AIN16 (_UL(1) << 8) 641 #define PIN_PA09B_ADC_AIN17 _L(9) /**< \brief ADC signal: AIN17 on PA09 mux B */ 642 #define MUX_PA09B_ADC_AIN17 _L(1) 643 #define PINMUX_PA09B_ADC_AIN17 ((PIN_PA09B_ADC_AIN17 << 16) | MUX_PA09B_ADC_AIN17) 644 #define PORT_PA09B_ADC_AIN17 (_UL(1) << 9) 645 #define PIN_PA10B_ADC_AIN18 _L(10) /**< \brief ADC signal: AIN18 on PA10 mux B */ 646 #define MUX_PA10B_ADC_AIN18 _L(1) 647 #define PINMUX_PA10B_ADC_AIN18 ((PIN_PA10B_ADC_AIN18 << 16) | MUX_PA10B_ADC_AIN18) 648 #define PORT_PA10B_ADC_AIN18 (_UL(1) << 10) 649 #define PIN_PA11B_ADC_AIN19 _L(11) /**< \brief ADC signal: AIN19 on PA11 mux B */ 650 #define MUX_PA11B_ADC_AIN19 _L(1) 651 #define PINMUX_PA11B_ADC_AIN19 ((PIN_PA11B_ADC_AIN19 << 16) | MUX_PA11B_ADC_AIN19) 652 #define PORT_PA11B_ADC_AIN19 (_UL(1) << 11) 653 #define PIN_PA04B_ADC_VREFP _L(4) /**< \brief ADC signal: VREFP on PA04 mux B */ 654 #define MUX_PA04B_ADC_VREFP _L(1) 655 #define PINMUX_PA04B_ADC_VREFP ((PIN_PA04B_ADC_VREFP << 16) | MUX_PA04B_ADC_VREFP) 656 #define PORT_PA04B_ADC_VREFP (_UL(1) << 4) 657 /* ========== PORT definition for AC peripheral ========== */ 658 #define PIN_PA04B_AC_AIN0 _L(4) /**< \brief AC signal: AIN0 on PA04 mux B */ 659 #define MUX_PA04B_AC_AIN0 _L(1) 660 #define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) 661 #define PORT_PA04B_AC_AIN0 (_UL(1) << 4) 662 #define PIN_PA05B_AC_AIN1 _L(5) /**< \brief AC signal: AIN1 on PA05 mux B */ 663 #define MUX_PA05B_AC_AIN1 _L(1) 664 #define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) 665 #define PORT_PA05B_AC_AIN1 (_UL(1) << 5) 666 #define PIN_PA06B_AC_AIN2 _L(6) /**< \brief AC signal: AIN2 on PA06 mux B */ 667 #define MUX_PA06B_AC_AIN2 _L(1) 668 #define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) 669 #define PORT_PA06B_AC_AIN2 (_UL(1) << 6) 670 #define PIN_PA07B_AC_AIN3 _L(7) /**< \brief AC signal: AIN3 on PA07 mux B */ 671 #define MUX_PA07B_AC_AIN3 _L(1) 672 #define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) 673 #define PORT_PA07B_AC_AIN3 (_UL(1) << 7) 674 #define PIN_PA18H_AC_CMP0 _L(18) /**< \brief AC signal: CMP0 on PA18 mux H */ 675 #define MUX_PA18H_AC_CMP0 _L(7) 676 #define PINMUX_PA18H_AC_CMP0 ((PIN_PA18H_AC_CMP0 << 16) | MUX_PA18H_AC_CMP0) 677 #define PORT_PA18H_AC_CMP0 (_UL(1) << 18) 678 #define PIN_PA19H_AC_CMP1 _L(19) /**< \brief AC signal: CMP1 on PA19 mux H */ 679 #define MUX_PA19H_AC_CMP1 _L(7) 680 #define PINMUX_PA19H_AC_CMP1 ((PIN_PA19H_AC_CMP1 << 16) | MUX_PA19H_AC_CMP1) 681 #define PORT_PA19H_AC_CMP1 (_UL(1) << 19) 682 /* ========== PORT definition for OPAMP peripheral ========== */ 683 #define PIN_PA02B_OPAMP_OANEG0 _L(2) /**< \brief OPAMP signal: OANEG0 on PA02 mux B */ 684 #define MUX_PA02B_OPAMP_OANEG0 _L(1) 685 #define PINMUX_PA02B_OPAMP_OANEG0 ((PIN_PA02B_OPAMP_OANEG0 << 16) | MUX_PA02B_OPAMP_OANEG0) 686 #define PORT_PA02B_OPAMP_OANEG0 (_UL(1) << 2) 687 #define PIN_PA07B_OPAMP_OAOUT0 _L(7) /**< \brief OPAMP signal: OAOUT0 on PA07 mux B */ 688 #define MUX_PA07B_OPAMP_OAOUT0 _L(1) 689 #define PINMUX_PA07B_OPAMP_OAOUT0 ((PIN_PA07B_OPAMP_OAOUT0 << 16) | MUX_PA07B_OPAMP_OAOUT0) 690 #define PORT_PA07B_OPAMP_OAOUT0 (_UL(1) << 7) 691 #define PIN_PA04B_OPAMP_OAOUT2 _L(4) /**< \brief OPAMP signal: OAOUT2 on PA04 mux B */ 692 #define MUX_PA04B_OPAMP_OAOUT2 _L(1) 693 #define PINMUX_PA04B_OPAMP_OAOUT2 ((PIN_PA04B_OPAMP_OAOUT2 << 16) | MUX_PA04B_OPAMP_OAOUT2) 694 #define PORT_PA04B_OPAMP_OAOUT2 (_UL(1) << 4) 695 #define PIN_PA06B_OPAMP_OAPOS0 _L(6) /**< \brief OPAMP signal: OAPOS0 on PA06 mux B */ 696 #define MUX_PA06B_OPAMP_OAPOS0 _L(1) 697 #define PINMUX_PA06B_OPAMP_OAPOS0 ((PIN_PA06B_OPAMP_OAPOS0 << 16) | MUX_PA06B_OPAMP_OAPOS0) 698 #define PORT_PA06B_OPAMP_OAPOS0 (_UL(1) << 6) 699 #define PIN_PA05B_OPAMP_OAPOS2 _L(5) /**< \brief OPAMP signal: OAPOS2 on PA05 mux B */ 700 #define MUX_PA05B_OPAMP_OAPOS2 _L(1) 701 #define PINMUX_PA05B_OPAMP_OAPOS2 ((PIN_PA05B_OPAMP_OAPOS2 << 16) | MUX_PA05B_OPAMP_OAPOS2) 702 #define PORT_PA05B_OPAMP_OAPOS2 (_UL(1) << 5) 703 /* ========== PORT definition for CCL peripheral ========== */ 704 #define PIN_PA04I_CCL_IN0 _L(4) /**< \brief CCL signal: IN0 on PA04 mux I */ 705 #define MUX_PA04I_CCL_IN0 _L(8) 706 #define PINMUX_PA04I_CCL_IN0 ((PIN_PA04I_CCL_IN0 << 16) | MUX_PA04I_CCL_IN0) 707 #define PORT_PA04I_CCL_IN0 (_UL(1) << 4) 708 #define PIN_PA16I_CCL_IN0 _L(16) /**< \brief CCL signal: IN0 on PA16 mux I */ 709 #define MUX_PA16I_CCL_IN0 _L(8) 710 #define PINMUX_PA16I_CCL_IN0 ((PIN_PA16I_CCL_IN0 << 16) | MUX_PA16I_CCL_IN0) 711 #define PORT_PA16I_CCL_IN0 (_UL(1) << 16) 712 #define PIN_PA05I_CCL_IN1 _L(5) /**< \brief CCL signal: IN1 on PA05 mux I */ 713 #define MUX_PA05I_CCL_IN1 _L(8) 714 #define PINMUX_PA05I_CCL_IN1 ((PIN_PA05I_CCL_IN1 << 16) | MUX_PA05I_CCL_IN1) 715 #define PORT_PA05I_CCL_IN1 (_UL(1) << 5) 716 #define PIN_PA17I_CCL_IN1 _L(17) /**< \brief CCL signal: IN1 on PA17 mux I */ 717 #define MUX_PA17I_CCL_IN1 _L(8) 718 #define PINMUX_PA17I_CCL_IN1 ((PIN_PA17I_CCL_IN1 << 16) | MUX_PA17I_CCL_IN1) 719 #define PORT_PA17I_CCL_IN1 (_UL(1) << 17) 720 #define PIN_PA06I_CCL_IN2 _L(6) /**< \brief CCL signal: IN2 on PA06 mux I */ 721 #define MUX_PA06I_CCL_IN2 _L(8) 722 #define PINMUX_PA06I_CCL_IN2 ((PIN_PA06I_CCL_IN2 << 16) | MUX_PA06I_CCL_IN2) 723 #define PORT_PA06I_CCL_IN2 (_UL(1) << 6) 724 #define PIN_PA18I_CCL_IN2 _L(18) /**< \brief CCL signal: IN2 on PA18 mux I */ 725 #define MUX_PA18I_CCL_IN2 _L(8) 726 #define PINMUX_PA18I_CCL_IN2 ((PIN_PA18I_CCL_IN2 << 16) | MUX_PA18I_CCL_IN2) 727 #define PORT_PA18I_CCL_IN2 (_UL(1) << 18) 728 #define PIN_PA08I_CCL_IN3 _L(8) /**< \brief CCL signal: IN3 on PA08 mux I */ 729 #define MUX_PA08I_CCL_IN3 _L(8) 730 #define PINMUX_PA08I_CCL_IN3 ((PIN_PA08I_CCL_IN3 << 16) | MUX_PA08I_CCL_IN3) 731 #define PORT_PA08I_CCL_IN3 (_UL(1) << 8) 732 #define PIN_PA30I_CCL_IN3 _L(30) /**< \brief CCL signal: IN3 on PA30 mux I */ 733 #define MUX_PA30I_CCL_IN3 _L(8) 734 #define PINMUX_PA30I_CCL_IN3 ((PIN_PA30I_CCL_IN3 << 16) | MUX_PA30I_CCL_IN3) 735 #define PORT_PA30I_CCL_IN3 (_UL(1) << 30) 736 #define PIN_PA09I_CCL_IN4 _L(9) /**< \brief CCL signal: IN4 on PA09 mux I */ 737 #define MUX_PA09I_CCL_IN4 _L(8) 738 #define PINMUX_PA09I_CCL_IN4 ((PIN_PA09I_CCL_IN4 << 16) | MUX_PA09I_CCL_IN4) 739 #define PORT_PA09I_CCL_IN4 (_UL(1) << 9) 740 #define PIN_PA10I_CCL_IN5 _L(10) /**< \brief CCL signal: IN5 on PA10 mux I */ 741 #define MUX_PA10I_CCL_IN5 _L(8) 742 #define PINMUX_PA10I_CCL_IN5 ((PIN_PA10I_CCL_IN5 << 16) | MUX_PA10I_CCL_IN5) 743 #define PORT_PA10I_CCL_IN5 (_UL(1) << 10) 744 #define PIN_PA22I_CCL_IN6 _L(22) /**< \brief CCL signal: IN6 on PA22 mux I */ 745 #define MUX_PA22I_CCL_IN6 _L(8) 746 #define PINMUX_PA22I_CCL_IN6 ((PIN_PA22I_CCL_IN6 << 16) | MUX_PA22I_CCL_IN6) 747 #define PORT_PA22I_CCL_IN6 (_UL(1) << 22) 748 #define PIN_PA23I_CCL_IN7 _L(23) /**< \brief CCL signal: IN7 on PA23 mux I */ 749 #define MUX_PA23I_CCL_IN7 _L(8) 750 #define PINMUX_PA23I_CCL_IN7 ((PIN_PA23I_CCL_IN7 << 16) | MUX_PA23I_CCL_IN7) 751 #define PORT_PA23I_CCL_IN7 (_UL(1) << 23) 752 #define PIN_PA24I_CCL_IN8 _L(24) /**< \brief CCL signal: IN8 on PA24 mux I */ 753 #define MUX_PA24I_CCL_IN8 _L(8) 754 #define PINMUX_PA24I_CCL_IN8 ((PIN_PA24I_CCL_IN8 << 16) | MUX_PA24I_CCL_IN8) 755 #define PORT_PA24I_CCL_IN8 (_UL(1) << 24) 756 #define PIN_PA07I_CCL_OUT0 _L(7) /**< \brief CCL signal: OUT0 on PA07 mux I */ 757 #define MUX_PA07I_CCL_OUT0 _L(8) 758 #define PINMUX_PA07I_CCL_OUT0 ((PIN_PA07I_CCL_OUT0 << 16) | MUX_PA07I_CCL_OUT0) 759 #define PORT_PA07I_CCL_OUT0 (_UL(1) << 7) 760 #define PIN_PA19I_CCL_OUT0 _L(19) /**< \brief CCL signal: OUT0 on PA19 mux I */ 761 #define MUX_PA19I_CCL_OUT0 _L(8) 762 #define PINMUX_PA19I_CCL_OUT0 ((PIN_PA19I_CCL_OUT0 << 16) | MUX_PA19I_CCL_OUT0) 763 #define PORT_PA19I_CCL_OUT0 (_UL(1) << 19) 764 #define PIN_PA11I_CCL_OUT1 _L(11) /**< \brief CCL signal: OUT1 on PA11 mux I */ 765 #define MUX_PA11I_CCL_OUT1 _L(8) 766 #define PINMUX_PA11I_CCL_OUT1 ((PIN_PA11I_CCL_OUT1 << 16) | MUX_PA11I_CCL_OUT1) 767 #define PORT_PA11I_CCL_OUT1 (_UL(1) << 11) 768 #define PIN_PA31I_CCL_OUT1 _L(31) /**< \brief CCL signal: OUT1 on PA31 mux I */ 769 #define MUX_PA31I_CCL_OUT1 _L(8) 770 #define PINMUX_PA31I_CCL_OUT1 ((PIN_PA31I_CCL_OUT1 << 16) | MUX_PA31I_CCL_OUT1) 771 #define PORT_PA31I_CCL_OUT1 (_UL(1) << 31) 772 #define PIN_PA25I_CCL_OUT2 _L(25) /**< \brief CCL signal: OUT2 on PA25 mux I */ 773 #define MUX_PA25I_CCL_OUT2 _L(8) 774 #define PINMUX_PA25I_CCL_OUT2 ((PIN_PA25I_CCL_OUT2 << 16) | MUX_PA25I_CCL_OUT2) 775 #define PORT_PA25I_CCL_OUT2 (_UL(1) << 25) 776 777 #endif /* _SAML21E18B_PIO_ */ 778
