1 /** 2 * \file 3 * 4 * \brief Component description for SUPC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_SUPC_COMPONENT_ 30 #define _SAML21_SUPC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR SUPC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_SUPC Supply Controller */ 36 /*@{*/ 37 38 #define SUPC_U2117 39 #define REV_SUPC 0x110 40 41 /* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ 46 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ 47 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ 48 uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ 49 uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ 50 uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ 51 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 52 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ 53 uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ 54 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ 55 uint32_t :21; /*!< bit: 11..31 Reserved */ 56 } bit; /*!< Structure used for bit access */ 57 uint32_t reg; /*!< Type used for register access */ 58 } SUPC_INTENCLR_Type; 59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 #define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */ 62 #define SUPC_INTENCLR_RESETVALUE _U(0x00000000) /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */ 63 64 #define SUPC_INTENCLR_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENCLR) BOD33 Ready */ 65 #define SUPC_INTENCLR_BOD33RDY (_U(0x1) << SUPC_INTENCLR_BOD33RDY_Pos) 66 #define SUPC_INTENCLR_BOD33DET_Pos 1 /**< \brief (SUPC_INTENCLR) BOD33 Detection */ 67 #define SUPC_INTENCLR_BOD33DET (_U(0x1) << SUPC_INTENCLR_BOD33DET_Pos) 68 #define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */ 69 #define SUPC_INTENCLR_B33SRDY (_U(0x1) << SUPC_INTENCLR_B33SRDY_Pos) 70 #define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */ 71 #define SUPC_INTENCLR_BOD12RDY (_U(0x1) << SUPC_INTENCLR_BOD12RDY_Pos) 72 #define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */ 73 #define SUPC_INTENCLR_BOD12DET (_U(0x1) << SUPC_INTENCLR_BOD12DET_Pos) 74 #define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */ 75 #define SUPC_INTENCLR_B12SRDY (_U(0x1) << SUPC_INTENCLR_B12SRDY_Pos) 76 #define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */ 77 #define SUPC_INTENCLR_VREGRDY (_U(0x1) << SUPC_INTENCLR_VREGRDY_Pos) 78 #define SUPC_INTENCLR_APWSRDY_Pos 9 /**< \brief (SUPC_INTENCLR) Automatic Power Switch Ready */ 79 #define SUPC_INTENCLR_APWSRDY (_U(0x1) << SUPC_INTENCLR_APWSRDY_Pos) 80 #define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */ 81 #define SUPC_INTENCLR_VCORERDY (_U(0x1) << SUPC_INTENCLR_VCORERDY_Pos) 82 #define SUPC_INTENCLR_MASK _U(0x0000073F) /**< \brief (SUPC_INTENCLR) MASK Register */ 83 84 /* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 85 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 86 typedef union { 87 struct { 88 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ 89 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ 90 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ 91 uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ 92 uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ 93 uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ 94 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 95 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ 96 uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ 97 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ 98 uint32_t :21; /*!< bit: 11..31 Reserved */ 99 } bit; /*!< Structure used for bit access */ 100 uint32_t reg; /*!< Type used for register access */ 101 } SUPC_INTENSET_Type; 102 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 103 104 #define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */ 105 #define SUPC_INTENSET_RESETVALUE _U(0x00000000) /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */ 106 107 #define SUPC_INTENSET_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENSET) BOD33 Ready */ 108 #define SUPC_INTENSET_BOD33RDY (_U(0x1) << SUPC_INTENSET_BOD33RDY_Pos) 109 #define SUPC_INTENSET_BOD33DET_Pos 1 /**< \brief (SUPC_INTENSET) BOD33 Detection */ 110 #define SUPC_INTENSET_BOD33DET (_U(0x1) << SUPC_INTENSET_BOD33DET_Pos) 111 #define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */ 112 #define SUPC_INTENSET_B33SRDY (_U(0x1) << SUPC_INTENSET_B33SRDY_Pos) 113 #define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */ 114 #define SUPC_INTENSET_BOD12RDY (_U(0x1) << SUPC_INTENSET_BOD12RDY_Pos) 115 #define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */ 116 #define SUPC_INTENSET_BOD12DET (_U(0x1) << SUPC_INTENSET_BOD12DET_Pos) 117 #define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */ 118 #define SUPC_INTENSET_B12SRDY (_U(0x1) << SUPC_INTENSET_B12SRDY_Pos) 119 #define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */ 120 #define SUPC_INTENSET_VREGRDY (_U(0x1) << SUPC_INTENSET_VREGRDY_Pos) 121 #define SUPC_INTENSET_APWSRDY_Pos 9 /**< \brief (SUPC_INTENSET) Automatic Power Switch Ready */ 122 #define SUPC_INTENSET_APWSRDY (_U(0x1) << SUPC_INTENSET_APWSRDY_Pos) 123 #define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */ 124 #define SUPC_INTENSET_VCORERDY (_U(0x1) << SUPC_INTENSET_VCORERDY_Pos) 125 #define SUPC_INTENSET_MASK _U(0x0000073F) /**< \brief (SUPC_INTENSET) MASK Register */ 126 127 /* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 128 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 129 typedef union { // __I to avoid read-modify-write on write-to-clear register 130 struct { 131 __I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ 132 __I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ 133 __I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ 134 __I uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ 135 __I uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ 136 __I uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ 137 __I uint32_t :2; /*!< bit: 6.. 7 Reserved */ 138 __I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ 139 __I uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ 140 __I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ 141 __I uint32_t :21; /*!< bit: 11..31 Reserved */ 142 } bit; /*!< Structure used for bit access */ 143 uint32_t reg; /*!< Type used for register access */ 144 } SUPC_INTFLAG_Type; 145 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 146 147 #define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */ 148 #define SUPC_INTFLAG_RESETVALUE _U(0x00000000) /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 149 150 #define SUPC_INTFLAG_BOD33RDY_Pos 0 /**< \brief (SUPC_INTFLAG) BOD33 Ready */ 151 #define SUPC_INTFLAG_BOD33RDY (_U(0x1) << SUPC_INTFLAG_BOD33RDY_Pos) 152 #define SUPC_INTFLAG_BOD33DET_Pos 1 /**< \brief (SUPC_INTFLAG) BOD33 Detection */ 153 #define SUPC_INTFLAG_BOD33DET (_U(0x1) << SUPC_INTFLAG_BOD33DET_Pos) 154 #define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */ 155 #define SUPC_INTFLAG_B33SRDY (_U(0x1) << SUPC_INTFLAG_B33SRDY_Pos) 156 #define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */ 157 #define SUPC_INTFLAG_BOD12RDY (_U(0x1) << SUPC_INTFLAG_BOD12RDY_Pos) 158 #define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */ 159 #define SUPC_INTFLAG_BOD12DET (_U(0x1) << SUPC_INTFLAG_BOD12DET_Pos) 160 #define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */ 161 #define SUPC_INTFLAG_B12SRDY (_U(0x1) << SUPC_INTFLAG_B12SRDY_Pos) 162 #define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */ 163 #define SUPC_INTFLAG_VREGRDY (_U(0x1) << SUPC_INTFLAG_VREGRDY_Pos) 164 #define SUPC_INTFLAG_APWSRDY_Pos 9 /**< \brief (SUPC_INTFLAG) Automatic Power Switch Ready */ 165 #define SUPC_INTFLAG_APWSRDY (_U(0x1) << SUPC_INTFLAG_APWSRDY_Pos) 166 #define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */ 167 #define SUPC_INTFLAG_VCORERDY (_U(0x1) << SUPC_INTFLAG_VCORERDY_Pos) 168 #define SUPC_INTFLAG_MASK _U(0x0000073F) /**< \brief (SUPC_INTFLAG) MASK Register */ 169 170 /* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ 171 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 172 typedef union { 173 struct { 174 uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ 175 uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ 176 uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ 177 uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ 178 uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ 179 uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ 180 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 181 uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ 182 uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ 183 uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ 184 uint32_t BBPS:1; /*!< bit: 11 Battery Backup Power Switch */ 185 uint32_t :20; /*!< bit: 12..31 Reserved */ 186 } bit; /*!< Structure used for bit access */ 187 uint32_t reg; /*!< Type used for register access */ 188 } SUPC_STATUS_Type; 189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 190 191 #define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */ 192 #define SUPC_STATUS_RESETVALUE _U(0x00000000) /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */ 193 194 #define SUPC_STATUS_BOD33RDY_Pos 0 /**< \brief (SUPC_STATUS) BOD33 Ready */ 195 #define SUPC_STATUS_BOD33RDY (_U(0x1) << SUPC_STATUS_BOD33RDY_Pos) 196 #define SUPC_STATUS_BOD33DET_Pos 1 /**< \brief (SUPC_STATUS) BOD33 Detection */ 197 #define SUPC_STATUS_BOD33DET (_U(0x1) << SUPC_STATUS_BOD33DET_Pos) 198 #define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */ 199 #define SUPC_STATUS_B33SRDY (_U(0x1) << SUPC_STATUS_B33SRDY_Pos) 200 #define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */ 201 #define SUPC_STATUS_BOD12RDY (_U(0x1) << SUPC_STATUS_BOD12RDY_Pos) 202 #define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */ 203 #define SUPC_STATUS_BOD12DET (_U(0x1) << SUPC_STATUS_BOD12DET_Pos) 204 #define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */ 205 #define SUPC_STATUS_B12SRDY (_U(0x1) << SUPC_STATUS_B12SRDY_Pos) 206 #define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */ 207 #define SUPC_STATUS_VREGRDY (_U(0x1) << SUPC_STATUS_VREGRDY_Pos) 208 #define SUPC_STATUS_APWSRDY_Pos 9 /**< \brief (SUPC_STATUS) Automatic Power Switch Ready */ 209 #define SUPC_STATUS_APWSRDY (_U(0x1) << SUPC_STATUS_APWSRDY_Pos) 210 #define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */ 211 #define SUPC_STATUS_VCORERDY (_U(0x1) << SUPC_STATUS_VCORERDY_Pos) 212 #define SUPC_STATUS_BBPS_Pos 11 /**< \brief (SUPC_STATUS) Battery Backup Power Switch */ 213 #define SUPC_STATUS_BBPS (_U(0x1) << SUPC_STATUS_BBPS_Pos) 214 #define SUPC_STATUS_MASK _U(0x00000F3F) /**< \brief (SUPC_STATUS) MASK Register */ 215 216 /* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { 219 struct { 220 uint32_t :1; /*!< bit: 0 Reserved */ 221 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 222 uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ 223 uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ 224 uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ 225 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 226 uint32_t RUNBKUP:1; /*!< bit: 7 Configuration in Backup mode */ 227 uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ 228 uint32_t :1; /*!< bit: 9 Reserved */ 229 uint32_t VMON:1; /*!< bit: 10 Voltage Monitored in active and standby mode */ 230 uint32_t :1; /*!< bit: 11 Reserved */ 231 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ 232 uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level for VDD */ 233 uint32_t :2; /*!< bit: 22..23 Reserved */ 234 uint32_t BKUPLEVEL:6; /*!< bit: 24..29 Threshold Level in backup sleep mode or for VBAT */ 235 uint32_t :2; /*!< bit: 30..31 Reserved */ 236 } bit; /*!< Structure used for bit access */ 237 uint32_t reg; /*!< Type used for register access */ 238 } SUPC_BOD33_Type; 239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 240 241 #define SUPC_BOD33_OFFSET 0x10 /**< \brief (SUPC_BOD33 offset) BOD33 Control */ 242 #define SUPC_BOD33_RESETVALUE _U(0x00000000) /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */ 243 244 #define SUPC_BOD33_ENABLE_Pos 1 /**< \brief (SUPC_BOD33) Enable */ 245 #define SUPC_BOD33_ENABLE (_U(0x1) << SUPC_BOD33_ENABLE_Pos) 246 #define SUPC_BOD33_HYST_Pos 2 /**< \brief (SUPC_BOD33) Hysteresis Enable */ 247 #define SUPC_BOD33_HYST (_U(0x1) << SUPC_BOD33_HYST_Pos) 248 #define SUPC_BOD33_ACTION_Pos 3 /**< \brief (SUPC_BOD33) Action when Threshold Crossed */ 249 #define SUPC_BOD33_ACTION_Msk (_U(0x3) << SUPC_BOD33_ACTION_Pos) 250 #define SUPC_BOD33_ACTION(value) (SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos)) 251 #define SUPC_BOD33_ACTION_NONE_Val _U(0x0) /**< \brief (SUPC_BOD33) No action */ 252 #define SUPC_BOD33_ACTION_RESET_Val _U(0x1) /**< \brief (SUPC_BOD33) The BOD33 generates a reset */ 253 #define SUPC_BOD33_ACTION_INT_Val _U(0x2) /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */ 254 #define SUPC_BOD33_ACTION_BKUP_Val _U(0x3) /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode if VMON=0 */ 255 #define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos) 256 #define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos) 257 #define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos) 258 #define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos) 259 #define SUPC_BOD33_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD33) Configuration in Standby mode */ 260 #define SUPC_BOD33_STDBYCFG (_U(0x1) << SUPC_BOD33_STDBYCFG_Pos) 261 #define SUPC_BOD33_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD33) Run during Standby */ 262 #define SUPC_BOD33_RUNSTDBY (_U(0x1) << SUPC_BOD33_RUNSTDBY_Pos) 263 #define SUPC_BOD33_RUNBKUP_Pos 7 /**< \brief (SUPC_BOD33) Configuration in Backup mode */ 264 #define SUPC_BOD33_RUNBKUP (_U(0x1) << SUPC_BOD33_RUNBKUP_Pos) 265 #define SUPC_BOD33_ACTCFG_Pos 8 /**< \brief (SUPC_BOD33) Configuration in Active mode */ 266 #define SUPC_BOD33_ACTCFG (_U(0x1) << SUPC_BOD33_ACTCFG_Pos) 267 #define SUPC_BOD33_VMON_Pos 10 /**< \brief (SUPC_BOD33) Voltage Monitored in active and standby mode */ 268 #define SUPC_BOD33_VMON (_U(0x1) << SUPC_BOD33_VMON_Pos) 269 #define SUPC_BOD33_PSEL_Pos 12 /**< \brief (SUPC_BOD33) Prescaler Select */ 270 #define SUPC_BOD33_PSEL_Msk (_U(0xF) << SUPC_BOD33_PSEL_Pos) 271 #define SUPC_BOD33_PSEL(value) (SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos)) 272 #define SUPC_BOD33_PSEL_DIV2_Val _U(0x0) /**< \brief (SUPC_BOD33) Divide clock by 2 */ 273 #define SUPC_BOD33_PSEL_DIV4_Val _U(0x1) /**< \brief (SUPC_BOD33) Divide clock by 4 */ 274 #define SUPC_BOD33_PSEL_DIV8_Val _U(0x2) /**< \brief (SUPC_BOD33) Divide clock by 8 */ 275 #define SUPC_BOD33_PSEL_DIV16_Val _U(0x3) /**< \brief (SUPC_BOD33) Divide clock by 16 */ 276 #define SUPC_BOD33_PSEL_DIV32_Val _U(0x4) /**< \brief (SUPC_BOD33) Divide clock by 32 */ 277 #define SUPC_BOD33_PSEL_DIV64_Val _U(0x5) /**< \brief (SUPC_BOD33) Divide clock by 64 */ 278 #define SUPC_BOD33_PSEL_DIV128_Val _U(0x6) /**< \brief (SUPC_BOD33) Divide clock by 128 */ 279 #define SUPC_BOD33_PSEL_DIV256_Val _U(0x7) /**< \brief (SUPC_BOD33) Divide clock by 256 */ 280 #define SUPC_BOD33_PSEL_DIV512_Val _U(0x8) /**< \brief (SUPC_BOD33) Divide clock by 512 */ 281 #define SUPC_BOD33_PSEL_DIV1024_Val _U(0x9) /**< \brief (SUPC_BOD33) Divide clock by 1024 */ 282 #define SUPC_BOD33_PSEL_DIV2048_Val _U(0xA) /**< \brief (SUPC_BOD33) Divide clock by 2048 */ 283 #define SUPC_BOD33_PSEL_DIV4096_Val _U(0xB) /**< \brief (SUPC_BOD33) Divide clock by 4096 */ 284 #define SUPC_BOD33_PSEL_DIV8192_Val _U(0xC) /**< \brief (SUPC_BOD33) Divide clock by 8192 */ 285 #define SUPC_BOD33_PSEL_DIV16384_Val _U(0xD) /**< \brief (SUPC_BOD33) Divide clock by 16384 */ 286 #define SUPC_BOD33_PSEL_DIV32768_Val _U(0xE) /**< \brief (SUPC_BOD33) Divide clock by 32768 */ 287 #define SUPC_BOD33_PSEL_DIV65536_Val _U(0xF) /**< \brief (SUPC_BOD33) Divide clock by 65536 */ 288 #define SUPC_BOD33_PSEL_DIV2 (SUPC_BOD33_PSEL_DIV2_Val << SUPC_BOD33_PSEL_Pos) 289 #define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos) 290 #define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos) 291 #define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos) 292 #define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos) 293 #define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos) 294 #define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos) 295 #define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos) 296 #define SUPC_BOD33_PSEL_DIV512 (SUPC_BOD33_PSEL_DIV512_Val << SUPC_BOD33_PSEL_Pos) 297 #define SUPC_BOD33_PSEL_DIV1024 (SUPC_BOD33_PSEL_DIV1024_Val << SUPC_BOD33_PSEL_Pos) 298 #define SUPC_BOD33_PSEL_DIV2048 (SUPC_BOD33_PSEL_DIV2048_Val << SUPC_BOD33_PSEL_Pos) 299 #define SUPC_BOD33_PSEL_DIV4096 (SUPC_BOD33_PSEL_DIV4096_Val << SUPC_BOD33_PSEL_Pos) 300 #define SUPC_BOD33_PSEL_DIV8192 (SUPC_BOD33_PSEL_DIV8192_Val << SUPC_BOD33_PSEL_Pos) 301 #define SUPC_BOD33_PSEL_DIV16384 (SUPC_BOD33_PSEL_DIV16384_Val << SUPC_BOD33_PSEL_Pos) 302 #define SUPC_BOD33_PSEL_DIV32768 (SUPC_BOD33_PSEL_DIV32768_Val << SUPC_BOD33_PSEL_Pos) 303 #define SUPC_BOD33_PSEL_DIV65536 (SUPC_BOD33_PSEL_DIV65536_Val << SUPC_BOD33_PSEL_Pos) 304 #define SUPC_BOD33_LEVEL_Pos 16 /**< \brief (SUPC_BOD33) Threshold Level for VDD */ 305 #define SUPC_BOD33_LEVEL_Msk (_U(0x3F) << SUPC_BOD33_LEVEL_Pos) 306 #define SUPC_BOD33_LEVEL(value) (SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos)) 307 #define SUPC_BOD33_BKUPLEVEL_Pos 24 /**< \brief (SUPC_BOD33) Threshold Level in backup sleep mode or for VBAT */ 308 #define SUPC_BOD33_BKUPLEVEL_Msk (_U(0x3F) << SUPC_BOD33_BKUPLEVEL_Pos) 309 #define SUPC_BOD33_BKUPLEVEL(value) (SUPC_BOD33_BKUPLEVEL_Msk & ((value) << SUPC_BOD33_BKUPLEVEL_Pos)) 310 #define SUPC_BOD33_MASK _U(0x3F3FF5FE) /**< \brief (SUPC_BOD33) MASK Register */ 311 312 /* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */ 313 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 314 typedef union { 315 struct { 316 uint32_t :1; /*!< bit: 0 Reserved */ 317 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 318 uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ 319 uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ 320 uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ 321 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 322 uint32_t :1; /*!< bit: 7 Reserved */ 323 uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ 324 uint32_t :3; /*!< bit: 9..11 Reserved */ 325 uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ 326 uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */ 327 uint32_t :10; /*!< bit: 22..31 Reserved */ 328 } bit; /*!< Structure used for bit access */ 329 uint32_t reg; /*!< Type used for register access */ 330 } SUPC_BOD12_Type; 331 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 332 333 #define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */ 334 #define SUPC_BOD12_RESETVALUE _U(0x00000000) /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */ 335 336 #define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */ 337 #define SUPC_BOD12_ENABLE (_U(0x1) << SUPC_BOD12_ENABLE_Pos) 338 #define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */ 339 #define SUPC_BOD12_HYST (_U(0x1) << SUPC_BOD12_HYST_Pos) 340 #define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */ 341 #define SUPC_BOD12_ACTION_Msk (_U(0x3) << SUPC_BOD12_ACTION_Pos) 342 #define SUPC_BOD12_ACTION(value) (SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos)) 343 #define SUPC_BOD12_ACTION_NONE_Val _U(0x0) /**< \brief (SUPC_BOD12) No action */ 344 #define SUPC_BOD12_ACTION_RESET_Val _U(0x1) /**< \brief (SUPC_BOD12) The BOD12 generates a reset */ 345 #define SUPC_BOD12_ACTION_INT_Val _U(0x2) /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */ 346 #define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos) 347 #define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos) 348 #define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos) 349 #define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */ 350 #define SUPC_BOD12_STDBYCFG (_U(0x1) << SUPC_BOD12_STDBYCFG_Pos) 351 #define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */ 352 #define SUPC_BOD12_RUNSTDBY (_U(0x1) << SUPC_BOD12_RUNSTDBY_Pos) 353 #define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */ 354 #define SUPC_BOD12_ACTCFG (_U(0x1) << SUPC_BOD12_ACTCFG_Pos) 355 #define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */ 356 #define SUPC_BOD12_PSEL_Msk (_U(0xF) << SUPC_BOD12_PSEL_Pos) 357 #define SUPC_BOD12_PSEL(value) (SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos)) 358 #define SUPC_BOD12_PSEL_DIV2_Val _U(0x0) /**< \brief (SUPC_BOD12) Divide clock by 2 */ 359 #define SUPC_BOD12_PSEL_DIV4_Val _U(0x1) /**< \brief (SUPC_BOD12) Divide clock by 4 */ 360 #define SUPC_BOD12_PSEL_DIV8_Val _U(0x2) /**< \brief (SUPC_BOD12) Divide clock by 8 */ 361 #define SUPC_BOD12_PSEL_DIV16_Val _U(0x3) /**< \brief (SUPC_BOD12) Divide clock by 16 */ 362 #define SUPC_BOD12_PSEL_DIV32_Val _U(0x4) /**< \brief (SUPC_BOD12) Divide clock by 32 */ 363 #define SUPC_BOD12_PSEL_DIV64_Val _U(0x5) /**< \brief (SUPC_BOD12) Divide clock by 64 */ 364 #define SUPC_BOD12_PSEL_DIV128_Val _U(0x6) /**< \brief (SUPC_BOD12) Divide clock by 128 */ 365 #define SUPC_BOD12_PSEL_DIV256_Val _U(0x7) /**< \brief (SUPC_BOD12) Divide clock by 256 */ 366 #define SUPC_BOD12_PSEL_DIV512_Val _U(0x8) /**< \brief (SUPC_BOD12) Divide clock by 512 */ 367 #define SUPC_BOD12_PSEL_DIV1024_Val _U(0x9) /**< \brief (SUPC_BOD12) Divide clock by 1024 */ 368 #define SUPC_BOD12_PSEL_DIV2048_Val _U(0xA) /**< \brief (SUPC_BOD12) Divide clock by 2048 */ 369 #define SUPC_BOD12_PSEL_DIV4096_Val _U(0xB) /**< \brief (SUPC_BOD12) Divide clock by 4096 */ 370 #define SUPC_BOD12_PSEL_DIV8192_Val _U(0xC) /**< \brief (SUPC_BOD12) Divide clock by 8192 */ 371 #define SUPC_BOD12_PSEL_DIV16384_Val _U(0xD) /**< \brief (SUPC_BOD12) Divide clock by 16384 */ 372 #define SUPC_BOD12_PSEL_DIV32768_Val _U(0xE) /**< \brief (SUPC_BOD12) Divide clock by 32768 */ 373 #define SUPC_BOD12_PSEL_DIV65536_Val _U(0xF) /**< \brief (SUPC_BOD12) Divide clock by 65536 */ 374 #define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos) 375 #define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos) 376 #define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos) 377 #define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos) 378 #define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos) 379 #define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos) 380 #define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos) 381 #define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos) 382 #define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos) 383 #define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos) 384 #define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos) 385 #define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos) 386 #define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos) 387 #define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos) 388 #define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos) 389 #define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos) 390 #define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */ 391 #define SUPC_BOD12_LEVEL_Msk (_U(0x3F) << SUPC_BOD12_LEVEL_Pos) 392 #define SUPC_BOD12_LEVEL(value) (SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos)) 393 #define SUPC_BOD12_MASK _U(0x003FF17E) /**< \brief (SUPC_BOD12) MASK Register */ 394 395 /* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ 396 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 397 typedef union { 398 struct { 399 uint32_t :1; /*!< bit: 0 Reserved */ 400 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 401 uint32_t SEL:2; /*!< bit: 2.. 3 Voltage Regulator Selection in active mode */ 402 uint32_t :1; /*!< bit: 4 Reserved */ 403 uint32_t STDBYPL0:1; /*!< bit: 5 Standby in PL0 */ 404 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 405 uint32_t :1; /*!< bit: 7 Reserved */ 406 uint32_t LPEFF:1; /*!< bit: 8 Low Power Efficiency */ 407 uint32_t :7; /*!< bit: 9..15 Reserved */ 408 uint32_t VSVSTEP:4; /*!< bit: 16..19 Voltage Scaling Voltage Step */ 409 uint32_t :4; /*!< bit: 20..23 Reserved */ 410 uint32_t VSPER:8; /*!< bit: 24..31 Voltage Scaling Period */ 411 } bit; /*!< Structure used for bit access */ 412 uint32_t reg; /*!< Type used for register access */ 413 } SUPC_VREG_Type; 414 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 415 416 #define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */ 417 #define SUPC_VREG_RESETVALUE _U(0x00000000) /**< \brief (SUPC_VREG reset_value) VREG Control */ 418 419 #define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */ 420 #define SUPC_VREG_ENABLE (_U(0x1) << SUPC_VREG_ENABLE_Pos) 421 #define SUPC_VREG_SEL_Pos 2 /**< \brief (SUPC_VREG) Voltage Regulator Selection in active mode */ 422 #define SUPC_VREG_SEL_Msk (_U(0x3) << SUPC_VREG_SEL_Pos) 423 #define SUPC_VREG_SEL(value) (SUPC_VREG_SEL_Msk & ((value) << SUPC_VREG_SEL_Pos)) 424 #define SUPC_VREG_SEL_LDO_Val _U(0x0) /**< \brief (SUPC_VREG) LDO selection */ 425 #define SUPC_VREG_SEL_BUCK_Val _U(0x1) /**< \brief (SUPC_VREG) Buck selection */ 426 #define SUPC_VREG_SEL_SCVREG_Val _U(0x2) /**< \brief (SUPC_VREG) Switched Cap selection */ 427 #define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos) 428 #define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos) 429 #define SUPC_VREG_SEL_SCVREG (SUPC_VREG_SEL_SCVREG_Val << SUPC_VREG_SEL_Pos) 430 #define SUPC_VREG_STDBYPL0_Pos 5 /**< \brief (SUPC_VREG) Standby in PL0 */ 431 #define SUPC_VREG_STDBYPL0 (_U(0x1) << SUPC_VREG_STDBYPL0_Pos) 432 #define SUPC_VREG_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREG) Run during Standby */ 433 #define SUPC_VREG_RUNSTDBY (_U(0x1) << SUPC_VREG_RUNSTDBY_Pos) 434 #define SUPC_VREG_LPEFF_Pos 8 /**< \brief (SUPC_VREG) Low Power Efficiency */ 435 #define SUPC_VREG_LPEFF (_U(0x1) << SUPC_VREG_LPEFF_Pos) 436 #define SUPC_VREG_VSVSTEP_Pos 16 /**< \brief (SUPC_VREG) Voltage Scaling Voltage Step */ 437 #define SUPC_VREG_VSVSTEP_Msk (_U(0xF) << SUPC_VREG_VSVSTEP_Pos) 438 #define SUPC_VREG_VSVSTEP(value) (SUPC_VREG_VSVSTEP_Msk & ((value) << SUPC_VREG_VSVSTEP_Pos)) 439 #define SUPC_VREG_VSPER_Pos 24 /**< \brief (SUPC_VREG) Voltage Scaling Period */ 440 #define SUPC_VREG_VSPER_Msk (_U(0xFF) << SUPC_VREG_VSPER_Pos) 441 #define SUPC_VREG_VSPER(value) (SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos)) 442 #define SUPC_VREG_MASK _U(0xFF0F016E) /**< \brief (SUPC_VREG) MASK Register */ 443 444 /* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ 445 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 446 typedef union { 447 struct { 448 uint32_t :1; /*!< bit: 0 Reserved */ 449 uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */ 450 uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */ 451 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 452 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 453 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */ 454 uint32_t :8; /*!< bit: 8..15 Reserved */ 455 uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */ 456 uint32_t :12; /*!< bit: 20..31 Reserved */ 457 } bit; /*!< Structure used for bit access */ 458 uint32_t reg; /*!< Type used for register access */ 459 } SUPC_VREF_Type; 460 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 461 462 #define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */ 463 #define SUPC_VREF_RESETVALUE _U(0x00000000) /**< \brief (SUPC_VREF reset_value) VREF Control */ 464 465 #define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */ 466 #define SUPC_VREF_TSEN (_U(0x1) << SUPC_VREF_TSEN_Pos) 467 #define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */ 468 #define SUPC_VREF_VREFOE (_U(0x1) << SUPC_VREF_VREFOE_Pos) 469 #define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */ 470 #define SUPC_VREF_RUNSTDBY (_U(0x1) << SUPC_VREF_RUNSTDBY_Pos) 471 #define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */ 472 #define SUPC_VREF_ONDEMAND (_U(0x1) << SUPC_VREF_ONDEMAND_Pos) 473 #define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */ 474 #define SUPC_VREF_SEL_Msk (_U(0xF) << SUPC_VREF_SEL_Pos) 475 #define SUPC_VREF_SEL(value) (SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos)) 476 #define SUPC_VREF_SEL_1V0_Val _U(0x0) /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */ 477 #define SUPC_VREF_SEL_1V1_Val _U(0x1) /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */ 478 #define SUPC_VREF_SEL_1V2_Val _U(0x2) /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */ 479 #define SUPC_VREF_SEL_1V25_Val _U(0x3) /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */ 480 #define SUPC_VREF_SEL_2V0_Val _U(0x4) /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */ 481 #define SUPC_VREF_SEL_2V2_Val _U(0x5) /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */ 482 #define SUPC_VREF_SEL_2V4_Val _U(0x6) /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */ 483 #define SUPC_VREF_SEL_2V5_Val _U(0x7) /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */ 484 #define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos) 485 #define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos) 486 #define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos) 487 #define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos) 488 #define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos) 489 #define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos) 490 #define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos) 491 #define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos) 492 #define SUPC_VREF_MASK _U(0x000F00C6) /**< \brief (SUPC_VREF) MASK Register */ 493 494 /* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */ 495 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 496 typedef union { 497 struct { 498 uint32_t CONF:2; /*!< bit: 0.. 1 Battery Backup Configuration */ 499 uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */ 500 uint32_t PSOKEN:1; /*!< bit: 3 Power Supply OK Enable */ 501 uint32_t :28; /*!< bit: 4..31 Reserved */ 502 } bit; /*!< Structure used for bit access */ 503 uint32_t reg; /*!< Type used for register access */ 504 } SUPC_BBPS_Type; 505 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 506 507 #define SUPC_BBPS_OFFSET 0x20 /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */ 508 #define SUPC_BBPS_RESETVALUE _U(0x00000000) /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */ 509 510 #define SUPC_BBPS_CONF_Pos 0 /**< \brief (SUPC_BBPS) Battery Backup Configuration */ 511 #define SUPC_BBPS_CONF_Msk (_U(0x3) << SUPC_BBPS_CONF_Pos) 512 #define SUPC_BBPS_CONF(value) (SUPC_BBPS_CONF_Msk & ((value) << SUPC_BBPS_CONF_Pos)) 513 #define SUPC_BBPS_CONF_NONE_Val _U(0x0) /**< \brief (SUPC_BBPS) The backup domain is always supplied by main power */ 514 #define SUPC_BBPS_CONF_APWS_Val _U(0x1) /**< \brief (SUPC_BBPS) The power switch is handled by the automatic power switch */ 515 #define SUPC_BBPS_CONF_FORCED_Val _U(0x2) /**< \brief (SUPC_BBPS) The backup domain is always supplied by battery backup power */ 516 #define SUPC_BBPS_CONF_BOD33_Val _U(0x3) /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */ 517 #define SUPC_BBPS_CONF_NONE (SUPC_BBPS_CONF_NONE_Val << SUPC_BBPS_CONF_Pos) 518 #define SUPC_BBPS_CONF_APWS (SUPC_BBPS_CONF_APWS_Val << SUPC_BBPS_CONF_Pos) 519 #define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos) 520 #define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos) 521 #define SUPC_BBPS_WAKEEN_Pos 2 /**< \brief (SUPC_BBPS) Wake Enable */ 522 #define SUPC_BBPS_WAKEEN (_U(0x1) << SUPC_BBPS_WAKEEN_Pos) 523 #define SUPC_BBPS_PSOKEN_Pos 3 /**< \brief (SUPC_BBPS) Power Supply OK Enable */ 524 #define SUPC_BBPS_PSOKEN (_U(0x1) << SUPC_BBPS_PSOKEN_Pos) 525 #define SUPC_BBPS_MASK _U(0x0000000F) /**< \brief (SUPC_BBPS) MASK Register */ 526 527 /* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */ 528 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 529 typedef union { 530 struct { 531 uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */ 532 uint32_t :6; /*!< bit: 2.. 7 Reserved */ 533 uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */ 534 uint32_t :6; /*!< bit: 10..15 Reserved */ 535 uint32_t SET:2; /*!< bit: 16..17 Set Output */ 536 uint32_t :6; /*!< bit: 18..23 Reserved */ 537 uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */ 538 uint32_t :6; /*!< bit: 26..31 Reserved */ 539 } bit; /*!< Structure used for bit access */ 540 uint32_t reg; /*!< Type used for register access */ 541 } SUPC_BKOUT_Type; 542 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 543 544 #define SUPC_BKOUT_OFFSET 0x24 /**< \brief (SUPC_BKOUT offset) Backup Output Control */ 545 #define SUPC_BKOUT_RESETVALUE _U(0x00000000) /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */ 546 547 #define SUPC_BKOUT_EN_Pos 0 /**< \brief (SUPC_BKOUT) Enable Output */ 548 #define SUPC_BKOUT_EN_Msk (_U(0x3) << SUPC_BKOUT_EN_Pos) 549 #define SUPC_BKOUT_EN(value) (SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos)) 550 #define SUPC_BKOUT_CLR_Pos 8 /**< \brief (SUPC_BKOUT) Clear Output */ 551 #define SUPC_BKOUT_CLR_Msk (_U(0x3) << SUPC_BKOUT_CLR_Pos) 552 #define SUPC_BKOUT_CLR(value) (SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos)) 553 #define SUPC_BKOUT_SET_Pos 16 /**< \brief (SUPC_BKOUT) Set Output */ 554 #define SUPC_BKOUT_SET_Msk (_U(0x3) << SUPC_BKOUT_SET_Pos) 555 #define SUPC_BKOUT_SET(value) (SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos)) 556 #define SUPC_BKOUT_RTCTGL_Pos 24 /**< \brief (SUPC_BKOUT) RTC Toggle Output */ 557 #define SUPC_BKOUT_RTCTGL_Msk (_U(0x3) << SUPC_BKOUT_RTCTGL_Pos) 558 #define SUPC_BKOUT_RTCTGL(value) (SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos)) 559 #define SUPC_BKOUT_MASK _U(0x03030303) /**< \brief (SUPC_BKOUT) MASK Register */ 560 561 /* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/ 32) Backup Input Control -------- */ 562 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 563 typedef union { 564 struct { 565 uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */ 566 uint32_t :24; /*!< bit: 8..31 Reserved */ 567 } bit; /*!< Structure used for bit access */ 568 uint32_t reg; /*!< Type used for register access */ 569 } SUPC_BKIN_Type; 570 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 571 572 #define SUPC_BKIN_OFFSET 0x28 /**< \brief (SUPC_BKIN offset) Backup Input Control */ 573 #define SUPC_BKIN_RESETVALUE _U(0x00000000) /**< \brief (SUPC_BKIN reset_value) Backup Input Control */ 574 575 #define SUPC_BKIN_BKIN_Pos 0 /**< \brief (SUPC_BKIN) Backup Input Value */ 576 #define SUPC_BKIN_BKIN_Msk (_U(0xFF) << SUPC_BKIN_BKIN_Pos) 577 #define SUPC_BKIN_BKIN(value) (SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos)) 578 #define SUPC_BKIN_MASK _U(0x000000FF) /**< \brief (SUPC_BKIN) MASK Register */ 579 580 /** \brief SUPC hardware registers */ 581 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 582 typedef struct { 583 __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 584 __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 585 __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 586 __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 587 __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */ 588 __IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */ 589 __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ 590 __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ 591 __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */ 592 __IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */ 593 __I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */ 594 } Supc; 595 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 596 597 /*@}*/ 598 599 #endif /* _SAML21_SUPC_COMPONENT_ */ 600