1
2 /**
3 * \file
4 *
5 * \brief RTC Driver
6 *
7 * Copyright (C) 2014 - 2017 Atmel Corporation. All rights reserved.
8 *
9 * \asf_license_start
10 *
11 * \page License
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions are met:
15 *
16 * 1. Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * 2. Redistributions in binary form must reproduce the above copyright notice,
20 * this list of conditions and the following disclaimer in the documentation
21 * and/or other materials provided with the distribution.
22 *
23 * 3. The name of Atmel may not be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * 4. This software may only be redistributed and used in connection with an
27 * Atmel microcontroller product.
28 *
29 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
30 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
31 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
32 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
33 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
34 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
35 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
40 *
41 * \asf_license_stop
42 *
43 */
44
45 #include <hpl_calendar.h>
46 #include <hpl_timer.h>
47 #include <utils_assert.h>
48 #include <hpl_rtc_config.h>
49
50 /*!< Pointer to hpl device */
51
52 static struct _timer_device *_rtc_dev = NULL;
53
54 /**
55 * \brief Initialize Timer
56 */
_timer_init(struct _timer_device * const dev,void * const hw)57 int32_t _timer_init(struct _timer_device *const dev, void *const hw)
58 {
59 ASSERT(dev);
60
61 dev->hw = hw;
62
63 hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_SWRST);
64 hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_SWRST);
65
66 #if CONF_RTC_EVENT_CONTROL_ENABLE == 1
67 hri_rtcmode0_write_EVCTRL_reg(dev->hw,
68 (CONF_RTC_PEREO0 << RTC_MODE0_EVCTRL_PEREO0_Pos)
69 | (CONF_RTC_PEREO1 << RTC_MODE0_EVCTRL_PEREO1_Pos)
70 | (CONF_RTC_PEREO2 << RTC_MODE0_EVCTRL_PEREO2_Pos)
71 | (CONF_RTC_PEREO3 << RTC_MODE0_EVCTRL_PEREO3_Pos)
72 | (CONF_RTC_PEREO4 << RTC_MODE0_EVCTRL_PEREO4_Pos)
73 | (CONF_RTC_PEREO5 << RTC_MODE0_EVCTRL_PEREO5_Pos)
74 | (CONF_RTC_PEREO6 << RTC_MODE0_EVCTRL_PEREO6_Pos)
75 | (CONF_RTC_PEREO7 << RTC_MODE0_EVCTRL_PEREO7_Pos)
76 | (CONF_RTC_COMPE0 << RTC_MODE0_EVCTRL_CMPEO_Pos)
77 | (CONF_RTC_OVFEO << RTC_MODE0_EVCTRL_OVFEO_Pos));
78 #endif
79
80 hri_rtcmode0_write_CTRLA_reg(
81 dev->hw, RTC_MODE0_CTRLA_PRESCALER(CONF_RTC_PRESCALER) | RTC_MODE0_CTRLA_COUNTSYNC | RTC_MODE0_CTRLA_MATCHCLR);
82 hri_rtcmode0_write_COMP_reg(dev->hw, 0, CONF_RTC_COMP_VAL);
83 hri_rtcmode0_set_INTEN_CMP0_bit(dev->hw);
84
85 _rtc_dev = dev;
86
87 return ERR_NONE;
88 }
89
90 /**
91 * \brief De-initialize Timer
92 */
_timer_deinit(struct _timer_device * const dev)93 void _timer_deinit(struct _timer_device *const dev)
94 {
95 ASSERT(dev && dev->hw);
96
97 NVIC_DisableIRQ(RTC_IRQn);
98
99 hri_rtcmode0_write_CTRLA_reg(dev->hw, RTC_MODE0_CTRLA_SWRST);
100 }
101
102 /**
103 * \brief Start hardware timer
104 */
_timer_start(struct _timer_device * const dev)105 void _timer_start(struct _timer_device *const dev)
106 {
107 ASSERT(dev && dev->hw);
108
109 NVIC_EnableIRQ(RTC_IRQn);
110 hri_rtcmode0_write_COUNT_reg(dev->hw, 0);
111 hri_rtcmode0_wait_for_sync(dev->hw, RTC_MODE0_SYNCBUSY_COUNT);
112 hri_rtcmode0_set_CTRLA_ENABLE_bit(dev->hw);
113 }
114
115 /**
116 * \brief Stop hardware timer
117 */
_timer_stop(struct _timer_device * const dev)118 void _timer_stop(struct _timer_device *const dev)
119 {
120 ASSERT(dev && dev->hw);
121
122 hri_rtcmode0_clear_CTRLA_ENABLE_bit(dev->hw);
123 }
124
125 /**
126 * \brief Set timer period
127 */
_timer_set_period(struct _timer_device * const dev,const uint32_t clock_cycles)128 void _timer_set_period(struct _timer_device *const dev, const uint32_t clock_cycles)
129 {
130 hri_rtcmode0_write_COMP_reg(dev->hw, 0, clock_cycles);
131 }
132
133 /**
134 * \brief Retrieve timer period
135 */
_timer_get_period(const struct _timer_device * const dev)136 uint32_t _timer_get_period(const struct _timer_device *const dev)
137 {
138 return hri_rtcmode0_read_COMP_reg(dev->hw, 0);
139 }
140
141 /**
142 * \brief Check if timer is running
143 */
_timer_is_started(const struct _timer_device * const dev)144 bool _timer_is_started(const struct _timer_device *const dev)
145 {
146 return hri_rtcmode0_get_CTRLA_ENABLE_bit(dev->hw);
147 }
148
149 /**
150 * \brief Set timer IRQ
151 */
_timer_set_irq(struct _timer_device * const dev)152 void _timer_set_irq(struct _timer_device *const dev)
153 {
154 (void)dev;
155 }
156
157 /**
158 * \brief RTC Timer interrupt handler
159 *
160 * \param[in] p The pointer to calendar device struct
161 */
_rtc_timer_interrupt_handler(struct _timer_device * dev)162 static void _rtc_timer_interrupt_handler(struct _timer_device *dev)
163 {
164 /* Read and mask interrupt flag register */
165 uint16_t flag = hri_rtcmode0_read_INTFLAG_reg(dev->hw);
166
167 if (flag & RTC_MODE0_INTFLAG_CMP0) {
168 if (dev->timer_cb.period_expired) {
169 dev->timer_cb.period_expired(dev);
170 }
171 /* Clear interrupt flag */
172 hri_rtcmode0_clear_interrupt_CMP0_bit(dev->hw);
173 }
174 }
175
176 /**
177 * \brief Retrieve timer helper functions
178 */
_rtc_get_timer(void)179 struct _timer_hpl_interface *_rtc_get_timer(void)
180 {
181 return NULL;
182 }
183
184 /**
185 * \brief Rtc interrupt handler
186 */
RTC_Handler(void)187 void RTC_Handler(void)
188 {
189 _rtc_timer_interrupt_handler(_rtc_dev);
190 }
191
