1 /* 2 * Copyright (c) 2015, Xilinx Inc. and Contributors. All rights reserved. 3 * Copyright (c) 2023 Advanced Micro Devices, Inc. All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /* 9 * @file freertos/xlnx/sys.h 10 * @brief freertos Xilinx common system primitives for libmetal. 11 */ 12 13 #ifndef __METAL_FREERTOS_SYS__H__ 14 #error "Include metal/sys.h instead of metal/freertos/@PROJECT_MACHINE@/sys.h" 15 #endif 16 17 #ifndef __METAL_FREERTOS_XLNX_SYS__H__ 18 #define __METAL_FREERTOS_XLNX_SYS__H__ 19 20 #include <metal/cpu.h> 21 22 #include "xscugic.h" 23 #include "FreeRTOS.h" 24 25 #ifdef __cplusplus 26 extern "C" { 27 #endif 28 29 #define metal_yield() metal_cpu_yield() 30 31 #if defined(SDT) && defined(PLATFORM_ZYNQ) 32 #define XPAR_SCUGIC_0_DIST_BASEADDR XPAR_SCUGIC_DIST_BASEADDR 33 #endif 34 35 #ifndef XLNX_MAXIRQS 36 #define XLNX_MAXIRQS XSCUGIC_MAX_NUM_INTR_INPUTS 37 #endif 38 39 /** 40 * @brief metal_xlnx_irq_isr 41 * 42 * Xilinx interrupt ISR can be registered to the Xilinx embeddedsw 43 * IRQ controller driver. 44 * 45 * @param[in] arg input argument, interrupt vector id. 46 */ 47 void metal_xlnx_irq_isr(void *arg); 48 49 /** 50 * @brief metal_xlnx_irq_int 51 * 52 * Xilinx interrupt controller initialization. It will initialize 53 * the metal Xilinx IRQ controller data structure. 54 * 55 * @return 0 for success, or negative value for failure 56 */ 57 int metal_xlnx_irq_init(void); 58 sys_irq_enable(unsigned int vector)59static inline void sys_irq_enable(unsigned int vector) 60 { 61 #ifdef PLATFORM_ZYNQ 62 XScuGic_EnableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector); 63 #else 64 vPortEnableInterrupt(vector); 65 #endif 66 } 67 sys_irq_disable(unsigned int vector)68static inline void sys_irq_disable(unsigned int vector) 69 { 70 #ifdef PLATFORM_ZYNQ 71 XScuGic_DisableIntr(XPAR_SCUGIC_0_DIST_BASEADDR, vector); 72 #else 73 vPortDisableInterrupt(vector); 74 #endif 75 } 76 77 #ifdef __cplusplus 78 } 79 #endif 80 81 #endif /* __METAL_FREERTOS_XLNX_SYS__H__ */ 82
