1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Homewood/ib.2/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ 6 7 /* Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #ifndef XTENSA_SPECREG_H 29 #define XTENSA_SPECREG_H 30 31 /* Include these special register bitfield definitions, for historical reasons: */ 32 #include <xtensa/corebits.h> 33 34 35 /* Special registers: */ 36 #define SAR 3 37 #define WINDOWBASE 72 38 #define WINDOWSTART 73 39 #define MPUENB 90 40 #define IBREAKENABLE 96 41 #define MEMCTL 97 42 #define CACHEADRDIS 98 43 #define DDR 104 44 #define IBREAKA_0 128 45 #define IBREAKA_1 129 46 #define DBREAKA_0 144 47 #define DBREAKA_1 145 48 #define DBREAKC_0 160 49 #define DBREAKC_1 161 50 #define EPC_1 177 51 #define EPC_2 178 52 #define EPC_3 179 53 #define EPC_4 180 54 #define EPC_5 181 55 #define EPC_6 182 56 #define EPC_7 183 57 #define DEPC 192 58 #define EPS_2 194 59 #define EPS_3 195 60 #define EPS_4 196 61 #define EPS_5 197 62 #define EPS_6 198 63 #define EPS_7 199 64 #define EXCSAVE_1 209 65 #define EXCSAVE_2 210 66 #define EXCSAVE_3 211 67 #define EXCSAVE_4 212 68 #define EXCSAVE_5 213 69 #define EXCSAVE_6 214 70 #define EXCSAVE_7 215 71 #define INTERRUPT 226 72 #define INTENABLE 228 73 #define PS 230 74 #define VECBASE 231 75 #define EXCCAUSE 232 76 #define DEBUGCAUSE 233 77 #define CCOUNT 234 78 #define PRID 235 79 #define ICOUNT 236 80 #define ICOUNTLEVEL 237 81 #define EXCVADDR 238 82 #define CCOMPARE_0 240 83 #define CCOMPARE_1 241 84 #define CCOMPARE_2 242 85 #define MISC_REG_0 244 86 #define MISC_REG_1 245 87 88 89 /* Special cases (bases of special register series): */ 90 #define IBREAKA 128 91 #define DBREAKA 144 92 #define DBREAKC 160 93 #define EPC 176 94 #define EPS 192 95 #define EXCSAVE 208 96 #define CCOMPARE 240 97 98 /* Special names for read-only and write-only interrupt registers: */ 99 #define INTREAD 226 100 #define INTSET 226 101 #define INTCLEAR 227 102 103 #endif /* XTENSA_SPECREG_H */ 104 105
