1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Foxhill/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ 6 7 /* Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #ifndef XTENSA_SPECREG_H 29 #define XTENSA_SPECREG_H 30 31 /* Include these special register bitfield definitions, for historical reasons: */ 32 #include <xtensa/corebits.h> 33 34 35 /* Special registers: */ 36 #define SAR 3 37 #define SCOMPARE1 12 38 #define WINDOWBASE 72 39 #define WINDOWSTART 73 40 #define IBREAKENABLE 96 41 #define ATOMCTL 99 42 #define DDR 104 43 #define IBREAKA_0 128 44 #define IBREAKA_1 129 45 #define DBREAKA_0 144 46 #define DBREAKA_1 145 47 #define DBREAKC_0 160 48 #define DBREAKC_1 161 49 #define EPC_1 177 50 #define EPC_2 178 51 #define EPC_3 179 52 #define EPC_4 180 53 #define EPC_5 181 54 #define EPC_6 182 55 #define EPC_7 183 56 #define DEPC 192 57 #define EPS_2 194 58 #define EPS_3 195 59 #define EPS_4 196 60 #define EPS_5 197 61 #define EPS_6 198 62 #define EPS_7 199 63 #define EXCSAVE_1 209 64 #define EXCSAVE_2 210 65 #define EXCSAVE_3 211 66 #define EXCSAVE_4 212 67 #define EXCSAVE_5 213 68 #define EXCSAVE_6 214 69 #define EXCSAVE_7 215 70 #define INTERRUPT 226 71 #define INTENABLE 228 72 #define PS 230 73 #define VECBASE 231 74 #define EXCCAUSE 232 75 #define DEBUGCAUSE 233 76 #define CCOUNT 234 77 #define PRID 235 78 #define ICOUNT 236 79 #define ICOUNTLEVEL 237 80 #define EXCVADDR 238 81 #define CCOMPARE_0 240 82 #define CCOMPARE_1 241 83 #define CCOMPARE_2 242 84 #define MISC_REG_0 244 85 #define MISC_REG_1 245 86 87 /* Special cases (bases of special register series): */ 88 #define IBREAKA 128 89 #define DBREAKA 144 90 #define DBREAKC 160 91 #define EPC 176 92 #define EPS 192 93 #define EXCSAVE 208 94 #define CCOMPARE 240 95 96 /* Special names for read-only and write-only interrupt registers: */ 97 #define INTREAD 226 98 #define INTSET 226 99 #define INTCLEAR 227 100 101 #endif /* XTENSA_SPECREG_H */ 102 103
