1 2 /* Secure Mode defines. */ 3 4 /* Copyright (c) 2020 Cadence Design Systems, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining 7 * a copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sublicense, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included 15 * in all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 20 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 21 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef XTENSA_SECURE_H 27 #define XTENSA_SECURE_H 28 29 30 /* SRAM */ 31 #define XCHAL_HAVE_SECURE_SRAM 0 32 33 /* INSTRAM0 */ 34 #define XCHAL_HAVE_SECURE_INSTRAM0 0 35 36 /* DATARAM0 */ 37 #define XCHAL_HAVE_SECURE_DATARAM0 0 38 39 /* Array of all secure regions' start/size */ 40 #define XCHAL_SECURE_MEM_LIST \ 41 { \ 42 } 43 44 #endif /* XTENSA_SECURE_H */ 45 46
