1 /* 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file contains assembly-language definitions (assembly 8 macros, etc.) for this specific Xtensa processor's TIE extensions 9 and options. It is customized to this Xtensa processor configuration. 10 11 Customer ID=13270; Build=0x92cb6; Copyright (c) 1999-2021 Cadence Design Systems Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #ifndef _XTENSA_CORE_TIE_ASM_H 33 #define _XTENSA_CORE_TIE_ASM_H 34 35 /* Selection parameter values for save-area save/restore macros: */ 36 /* Option vs. TIE: */ 37 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 38 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 39 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 40 /* Whether used automatically by compiler: */ 41 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 42 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 43 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 44 /* ABI handling across function calls: */ 45 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 46 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 47 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 48 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 49 /* Misc */ 50 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 51 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 52 | ((ccuse) & XTHAL_SAS_ANYCC) \ 53 | ((abi) & XTHAL_SAS_ANYABI) ) 54 55 56 /* 57 * Macro to store all non-coprocessor (extra) custom TIE and optional state 58 * (not including zero-overhead loop registers). 59 * Required parameters: 60 * ptr Save area pointer address register (clobbered) 61 * (register must contain a 4 byte aligned address). 62 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 63 * registers are clobbered, the remaining are unused). 64 * Optional parameters: 65 * continue If macro invoked as part of a larger store sequence, set to 1 66 * if this is not the first in the sequence. Defaults to 0. 67 * ofs Offset from start of larger sequence (from value of first ptr 68 * in sequence) at which to store. Defaults to next available space 69 * (or 0 if <continue> is 0). 70 * select Select what category(ies) of registers to store, as a bitmask 71 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 72 * alloc Select what category(ies) of registers to allocate; if any 73 * category is selected here that is not in <select>, space for 74 * the corresponding registers is skipped without doing any store. 75 */ 76 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 77 xchal_sa_start \continue, \ofs 78 // Optional global registers used by default by the compiler: 79 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 80 xchal_sa_align \ptr, 0, 1016, 4, 4 81 rur.THREADPTR \at1 // threadptr option 82 s32i \at1, \ptr, .Lxchal_ofs_+0 83 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 84 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 85 xchal_sa_align \ptr, 0, 1016, 4, 4 86 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 87 .endif 88 // Optional caller-saved registers used by default by the compiler: 89 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 90 xchal_sa_align \ptr, 0, 1012, 4, 4 91 rsr.ACCLO \at1 // MAC16 option 92 s32i \at1, \ptr, .Lxchal_ofs_+0 93 rsr.ACCHI \at1 // MAC16 option 94 s32i \at1, \ptr, .Lxchal_ofs_+4 95 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 96 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 97 xchal_sa_align \ptr, 0, 1012, 4, 4 98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 99 .endif 100 // Optional caller-saved registers not used by default by the compiler: 101 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 102 xchal_sa_align \ptr, 0, 996, 4, 4 103 rsr.BR \at1 // boolean option 104 s32i \at1, \ptr, .Lxchal_ofs_+0 105 rsr.SCOMPARE1 \at1 // conditional store option 106 s32i \at1, \ptr, .Lxchal_ofs_+4 107 rsr.M0 \at1 // MAC16 option 108 s32i \at1, \ptr, .Lxchal_ofs_+8 109 rsr.M1 \at1 // MAC16 option 110 s32i \at1, \ptr, .Lxchal_ofs_+12 111 rsr.M2 \at1 // MAC16 option 112 s32i \at1, \ptr, .Lxchal_ofs_+16 113 rsr.M3 \at1 // MAC16 option 114 s32i \at1, \ptr, .Lxchal_ofs_+20 115 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 116 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 117 xchal_sa_align \ptr, 0, 996, 4, 4 118 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 119 .endif 120 // Custom caller-saved registers not used by default by the compiler: 121 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 122 xchal_sa_align \ptr, 0, 1008, 4, 4 123 rur.F64R_LO \at1 // ureg 234 124 s32i \at1, \ptr, .Lxchal_ofs_+0 125 rur.F64R_HI \at1 // ureg 235 126 s32i \at1, \ptr, .Lxchal_ofs_+4 127 rur.F64S \at1 // ureg 236 128 s32i \at1, \ptr, .Lxchal_ofs_+8 129 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 130 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 131 xchal_sa_align \ptr, 0, 1008, 4, 4 132 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 133 .endif 134 .endm // xchal_ncp_store 135 136 /* 137 * Macro to load all non-coprocessor (extra) custom TIE and optional state 138 * (not including zero-overhead loop registers). 139 * Required parameters: 140 * ptr Save area pointer address register (clobbered) 141 * (register must contain a 4 byte aligned address). 142 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 143 * registers are clobbered, the remaining are unused). 144 * Optional parameters: 145 * continue If macro invoked as part of a larger load sequence, set to 1 146 * if this is not the first in the sequence. Defaults to 0. 147 * ofs Offset from start of larger sequence (from value of first ptr 148 * in sequence) at which to load. Defaults to next available space 149 * (or 0 if <continue> is 0). 150 * select Select what category(ies) of registers to load, as a bitmask 151 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 152 * alloc Select what category(ies) of registers to allocate; if any 153 * category is selected here that is not in <select>, space for 154 * the corresponding registers is skipped without doing any load. 155 */ 156 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 157 xchal_sa_start \continue, \ofs 158 // Optional global registers used by default by the compiler: 159 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 160 xchal_sa_align \ptr, 0, 1016, 4, 4 161 l32i \at1, \ptr, .Lxchal_ofs_+0 162 wur.THREADPTR \at1 // threadptr option 163 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 164 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 165 xchal_sa_align \ptr, 0, 1016, 4, 4 166 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 167 .endif 168 // Optional caller-saved registers used by default by the compiler: 169 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 170 xchal_sa_align \ptr, 0, 1012, 4, 4 171 l32i \at1, \ptr, .Lxchal_ofs_+0 172 wsr.ACCLO \at1 // MAC16 option 173 l32i \at1, \ptr, .Lxchal_ofs_+4 174 wsr.ACCHI \at1 // MAC16 option 175 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 176 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 177 xchal_sa_align \ptr, 0, 1012, 4, 4 178 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 179 .endif 180 // Optional caller-saved registers not used by default by the compiler: 181 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 182 xchal_sa_align \ptr, 0, 996, 4, 4 183 l32i \at1, \ptr, .Lxchal_ofs_+0 184 wsr.BR \at1 // boolean option 185 l32i \at1, \ptr, .Lxchal_ofs_+4 186 wsr.SCOMPARE1 \at1 // conditional store option 187 l32i \at1, \ptr, .Lxchal_ofs_+8 188 wsr.M0 \at1 // MAC16 option 189 l32i \at1, \ptr, .Lxchal_ofs_+12 190 wsr.M1 \at1 // MAC16 option 191 l32i \at1, \ptr, .Lxchal_ofs_+16 192 wsr.M2 \at1 // MAC16 option 193 l32i \at1, \ptr, .Lxchal_ofs_+20 194 wsr.M3 \at1 // MAC16 option 195 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 196 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 197 xchal_sa_align \ptr, 0, 996, 4, 4 198 .set .Lxchal_ofs_, .Lxchal_ofs_ + 24 199 .endif 200 // Custom caller-saved registers not used by default by the compiler: 201 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 202 xchal_sa_align \ptr, 0, 1008, 4, 4 203 l32i \at1, \ptr, .Lxchal_ofs_+0 204 wur.F64R_LO \at1 // ureg 234 205 l32i \at1, \ptr, .Lxchal_ofs_+4 206 wur.F64R_HI \at1 // ureg 235 207 l32i \at1, \ptr, .Lxchal_ofs_+8 208 wur.F64S \at1 // ureg 236 209 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 210 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 211 xchal_sa_align \ptr, 0, 1008, 4, 4 212 .set .Lxchal_ofs_, .Lxchal_ofs_ + 12 213 .endif 214 .endm // xchal_ncp_load 215 216 217 #define XCHAL_NCP_NUM_ATMPS 1 218 219 /* 220 * Macro to store the state of TIE coprocessor AudioEngineLX. 221 * Required parameters: 222 * ptr Save area pointer address register (clobbered) 223 * (register must contain a 8 byte aligned address). 224 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 225 * registers are clobbered, the remaining are unused). 226 * Optional parameters are the same as for xchal_ncp_store. 227 */ 228 #define xchal_cp_AudioEngineLX_store xchal_cp1_store 229 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 230 xchal_sa_start \continue, \ofs 231 // Custom caller-saved registers not used by default by the compiler: 232 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 233 xchal_sa_align \ptr, 0, 0, 8, 8 234 ae_s64.i aed0, \ptr, .Lxchal_ofs_+40 235 ae_s64.i aed1, \ptr, .Lxchal_ofs_+48 236 ae_s64.i aed2, \ptr, .Lxchal_ofs_+56 237 addi \ptr, \ptr, 64 238 ae_s64.i aed3, \ptr, .Lxchal_ofs_+0 239 ae_s64.i aed4, \ptr, .Lxchal_ofs_+8 240 ae_s64.i aed5, \ptr, .Lxchal_ofs_+16 241 ae_s64.i aed6, \ptr, .Lxchal_ofs_+24 242 ae_s64.i aed7, \ptr, .Lxchal_ofs_+32 243 ae_s64.i aed8, \ptr, .Lxchal_ofs_+40 244 ae_s64.i aed9, \ptr, .Lxchal_ofs_+48 245 ae_s64.i aed10, \ptr, .Lxchal_ofs_+56 246 addi \ptr, \ptr, 64 247 ae_s64.i aed11, \ptr, .Lxchal_ofs_+0 248 ae_s64.i aed12, \ptr, .Lxchal_ofs_+8 249 ae_s64.i aed13, \ptr, .Lxchal_ofs_+16 250 ae_s64.i aed14, \ptr, .Lxchal_ofs_+24 251 ae_s64.i aed15, \ptr, .Lxchal_ofs_+32 252 ae_movae \at1, aep0 253 s8i \at1, \ptr, .Lxchal_ofs_+40 254 ae_movae \at1, aep1 255 s8i \at1, \ptr, .Lxchal_ofs_+41 256 ae_movae \at1, aep2 257 s8i \at1, \ptr, .Lxchal_ofs_+42 258 ae_movae \at1, aep3 259 s8i \at1, \ptr, .Lxchal_ofs_+43 260 ae_salign64.i u0, \ptr, .Lxchal_ofs_+48 261 ae_salign64.i u1, \ptr, .Lxchal_ofs_+56 262 addi \ptr, \ptr, 64 263 ae_salign64.i u2, \ptr, .Lxchal_ofs_+0 264 ae_salign64.i u3, \ptr, .Lxchal_ofs_+8 265 addi \ptr, \ptr, -192 266 ae_movvfcrfsr aed0 // ureg FCR_FSR 267 ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 268 rur.AE_OVF_SAR \at1 // ureg 240 269 s32i \at1, \ptr, .Lxchal_ofs_+8 270 rur.AE_BITHEAD \at1 // ureg 241 271 s32i \at1, \ptr, .Lxchal_ofs_+12 272 rur.AE_TS_FTS_BU_BP \at1 // ureg 242 273 s32i \at1, \ptr, .Lxchal_ofs_+16 274 rur.AE_CW_SD_NO \at1 // ureg 243 275 s32i \at1, \ptr, .Lxchal_ofs_+20 276 rur.AE_CBEGIN0 \at1 // ureg 246 277 s32i \at1, \ptr, .Lxchal_ofs_+24 278 rur.AE_CEND0 \at1 // ureg 247 279 s32i \at1, \ptr, .Lxchal_ofs_+28 280 rur.AE_CBEGIN1 \at1 // ureg 248 281 s32i \at1, \ptr, .Lxchal_ofs_+32 282 rur.AE_CEND1 \at1 // ureg 249 283 s32i \at1, \ptr, .Lxchal_ofs_+36 284 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 285 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 286 xchal_sa_align \ptr, 0, 0, 8, 8 287 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 288 .endif 289 .endm // xchal_cp1_store 290 291 /* 292 * Macro to load the state of TIE coprocessor AudioEngineLX. 293 * Required parameters: 294 * ptr Save area pointer address register (clobbered) 295 * (register must contain a 8 byte aligned address). 296 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 297 * registers are clobbered, the remaining are unused). 298 * Optional parameters are the same as for xchal_ncp_load. 299 */ 300 #define xchal_cp_AudioEngineLX_load xchal_cp1_load 301 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 302 xchal_sa_start \continue, \ofs 303 // Custom caller-saved registers not used by default by the compiler: 304 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 305 xchal_sa_align \ptr, 0, 0, 8, 8 306 ae_l64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 // ureg FCR_FSR 307 ae_movfcrfsrv aed0 308 l32i \at1, \ptr, .Lxchal_ofs_+8 309 wur.AE_OVF_SAR \at1 // ureg 240 310 l32i \at1, \ptr, .Lxchal_ofs_+12 311 wur.AE_BITHEAD \at1 // ureg 241 312 l32i \at1, \ptr, .Lxchal_ofs_+16 313 wur.AE_TS_FTS_BU_BP \at1 // ureg 242 314 l32i \at1, \ptr, .Lxchal_ofs_+20 315 wur.AE_CW_SD_NO \at1 // ureg 243 316 l32i \at1, \ptr, .Lxchal_ofs_+24 317 wur.AE_CBEGIN0 \at1 // ureg 246 318 l32i \at1, \ptr, .Lxchal_ofs_+28 319 wur.AE_CEND0 \at1 // ureg 247 320 l32i \at1, \ptr, .Lxchal_ofs_+32 321 wur.AE_CBEGIN1 \at1 // ureg 248 322 l32i \at1, \ptr, .Lxchal_ofs_+36 323 wur.AE_CEND1 \at1 // ureg 249 324 ae_l64.i aed0, \ptr, .Lxchal_ofs_+40 325 ae_l64.i aed1, \ptr, .Lxchal_ofs_+48 326 ae_l64.i aed2, \ptr, .Lxchal_ofs_+56 327 addi \ptr, \ptr, 64 328 ae_l64.i aed3, \ptr, .Lxchal_ofs_+0 329 ae_l64.i aed4, \ptr, .Lxchal_ofs_+8 330 ae_l64.i aed5, \ptr, .Lxchal_ofs_+16 331 ae_l64.i aed6, \ptr, .Lxchal_ofs_+24 332 ae_l64.i aed7, \ptr, .Lxchal_ofs_+32 333 ae_l64.i aed8, \ptr, .Lxchal_ofs_+40 334 ae_l64.i aed9, \ptr, .Lxchal_ofs_+48 335 ae_l64.i aed10, \ptr, .Lxchal_ofs_+56 336 addi \ptr, \ptr, 64 337 ae_l64.i aed11, \ptr, .Lxchal_ofs_+0 338 ae_l64.i aed12, \ptr, .Lxchal_ofs_+8 339 ae_l64.i aed13, \ptr, .Lxchal_ofs_+16 340 ae_l64.i aed14, \ptr, .Lxchal_ofs_+24 341 ae_l64.i aed15, \ptr, .Lxchal_ofs_+32 342 addi \ptr, \ptr, 40 343 l8ui \at1, \ptr, .Lxchal_ofs_+0 344 ae_movea aep0, \at1 345 l8ui \at1, \ptr, .Lxchal_ofs_+1 346 ae_movea aep1, \at1 347 l8ui \at1, \ptr, .Lxchal_ofs_+2 348 ae_movea aep2, \at1 349 l8ui \at1, \ptr, .Lxchal_ofs_+3 350 ae_movea aep3, \at1 351 addi \ptr, \ptr, 8 352 ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 353 ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 354 ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 355 ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 356 .set .Lxchal_pofs_, .Lxchal_pofs_ + 176 357 .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 358 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 359 xchal_sa_align \ptr, 0, 0, 8, 8 360 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 361 .endif 362 .endm // xchal_cp1_load 363 364 #define XCHAL_CP1_NUM_ATMPS 1 365 #define XCHAL_SA_NUM_ATMPS 1 366 367 /* Empty macros for unconfigured coprocessors: */ 368 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 369 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 370 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 371 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 372 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 373 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 374 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 375 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 376 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 377 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 378 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 379 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 380 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 381 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 382 383 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 384 385
