1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Foxhill/dot.8/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ 6 7 /* Customer ID=13270; Build=0x92cb6; Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #ifndef XTENSA_SPECREG_H 29 #define XTENSA_SPECREG_H 30 31 /* Include these special register bitfield definitions, for historical reasons: */ 32 #include <xtensa/corebits.h> 33 34 35 /* Special registers: */ 36 #define LBEG 0 37 #define LEND 1 38 #define LCOUNT 2 39 #define SAR 3 40 #define BR 4 41 #define SCOMPARE1 12 42 #define ACCLO 16 43 #define ACCHI 17 44 #define MR_0 32 45 #define MR_1 33 46 #define MR_2 34 47 #define MR_3 35 48 #define PREFCTL 40 49 #define WINDOWBASE 72 50 #define WINDOWSTART 73 51 #define IBREAKENABLE 96 52 #define MEMCTL 97 53 #define ATOMCTL 99 54 #define DDR 104 55 #define IBREAKA_0 128 56 #define IBREAKA_1 129 57 #define DBREAKA_0 144 58 #define DBREAKA_1 145 59 #define DBREAKC_0 160 60 #define DBREAKC_1 161 61 #define EPC_1 177 62 #define EPC_2 178 63 #define EPC_3 179 64 #define EPC_4 180 65 #define EPC_5 181 66 #define DEPC 192 67 #define EPS_2 194 68 #define EPS_3 195 69 #define EPS_4 196 70 #define EPS_5 197 71 #define EXCSAVE_1 209 72 #define EXCSAVE_2 210 73 #define EXCSAVE_3 211 74 #define EXCSAVE_4 212 75 #define EXCSAVE_5 213 76 #define CPENABLE 224 77 #define INTERRUPT 226 78 #define INTENABLE 228 79 #define PS 230 80 #define VECBASE 231 81 #define EXCCAUSE 232 82 #define DEBUGCAUSE 233 83 #define CCOUNT 234 84 #define PRID 235 85 #define ICOUNT 236 86 #define ICOUNTLEVEL 237 87 #define EXCVADDR 238 88 #define CCOMPARE_0 240 89 #define CCOMPARE_1 241 90 #define MISC_REG_0 244 91 #define MISC_REG_1 245 92 93 /* Special cases (bases of special register series): */ 94 #define MR 32 95 #define IBREAKA 128 96 #define DBREAKA 144 97 #define DBREAKC 160 98 #define EPC 176 99 #define EPS 192 100 #define EXCSAVE 208 101 #define CCOMPARE 240 102 103 /* Special names for read-only and write-only interrupt registers: */ 104 #define INTREAD 226 105 #define INTSET 226 106 #define INTCLEAR 227 107 108 #endif /* XTENSA_SPECREG_H */ 109 110
