1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Homewood/ib.10/Xtensa/SWConfig/hal/specreg.h.tpp#1 $ */ 6 7 /* Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #ifndef XTENSA_SPECREG_H 29 #define XTENSA_SPECREG_H 30 31 /* Include these special register bitfield definitions, for historical reasons: */ 32 #include <xtensa/corebits.h> 33 34 35 /* Special registers: */ 36 #define LBEG 0 37 #define LEND 1 38 #define LCOUNT 2 39 #define SAR 3 40 #define BR 4 41 #define SCOMPARE1 12 42 #define PREFCTL 40 43 #define WINDOWBASE 72 44 #define WINDOWSTART 73 45 #define PTEVADDR 83 46 #define RASID 90 47 #define ITLBCFG 91 48 #define DTLBCFG 92 49 #define ERACCESS 95 50 #define IBREAKENABLE 96 51 #define MEMCTL 97 52 #define ATOMCTL 99 53 #define DDR 104 54 #define IBREAKA_0 128 55 #define IBREAKA_1 129 56 #define DBREAKA_0 144 57 #define DBREAKA_1 145 58 #define DBREAKC_0 160 59 #define DBREAKC_1 161 60 #define EPC_1 177 61 #define EPC_2 178 62 #define EPC_3 179 63 #define EPC_4 180 64 #define EPC_5 181 65 #define DEPC 192 66 #define EPS_2 194 67 #define EPS_3 195 68 #define EPS_4 196 69 #define EPS_5 197 70 #define EXCSAVE_1 209 71 #define EXCSAVE_2 210 72 #define EXCSAVE_3 211 73 #define EXCSAVE_4 212 74 #define EXCSAVE_5 213 75 #define CPENABLE 224 76 #define INTERRUPT 226 77 #define INTENABLE 228 78 #define PS 230 79 #define VECBASE 231 80 #define EXCCAUSE 232 81 #define DEBUGCAUSE 233 82 #define CCOUNT 234 83 #define PRID 235 84 #define ICOUNT 236 85 #define ICOUNTLEVEL 237 86 #define EXCVADDR 238 87 #define CCOMPARE_0 240 88 #define CCOMPARE_1 241 89 #define MISC_REG_0 244 90 #define MISC_REG_1 245 91 92 93 /* Special cases (bases of special register series): */ 94 #define IBREAKA 128 95 #define DBREAKA 144 96 #define DBREAKC 160 97 #define EPC 176 98 #define EPS 192 99 #define EXCSAVE 208 100 #define CCOMPARE 240 101 102 /* Special names for read-only and write-only interrupt registers: */ 103 #define INTREAD 226 104 #define INTSET 226 105 #define INTCLEAR 227 106 107 #endif /* XTENSA_SPECREG_H */ 108 109
