1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Boreal/Xtensa/SWConfig/hal/specreg.h.tpp#2 $ */ 6 7 /* Copyright (c) 1998-2002 Tensilica Inc. 8 9 Permission is hereby granted, free of charge, to any person obtaining 10 a copy of this software and associated documentation files (the 11 "Software"), to deal in the Software without restriction, including 12 without limitation the rights to use, copy, modify, merge, publish, 13 distribute, sublicense, and/or sell copies of the Software, and to 14 permit persons to whom the Software is furnished to do so, subject to 15 the following conditions: 16 17 The above copyright notice and this permission notice shall be included 18 in all copies or substantial portions of the Software. 19 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 21 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 22 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 23 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 24 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 25 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 26 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 27 28 #ifndef XTENSA_SPECREG_H 29 #define XTENSA_SPECREG_H 30 31 /* Include these special register bitfield definitions, for historical reasons: */ 32 #include <xtensa/corebits.h> 33 34 35 /* Special registers: */ 36 #define LBEG 0 37 #define LEND 1 38 #define LCOUNT 2 39 #define SAR 3 40 #define LITBASE 5 41 #define SCOMPARE1 12 42 #define ACCLO 16 43 #define ACCHI 17 44 #define MR_0 32 45 #define MR_1 33 46 #define MR_2 34 47 #define MR_3 35 48 #define WINDOWBASE 72 49 #define WINDOWSTART 73 50 #define PTEVADDR 83 51 #define RASID 90 52 #define ITLBCFG 91 53 #define DTLBCFG 92 54 #define IBREAKENABLE 96 55 #define ATOMCTL 99 56 #define DDR 104 57 #define IBREAKA_0 128 58 #define IBREAKA_1 129 59 #define DBREAKA_0 144 60 #define DBREAKA_1 145 61 #define DBREAKC_0 160 62 #define DBREAKC_1 161 63 #define EPC_1 177 64 #define EPC_2 178 65 #define EPC_3 179 66 #define EPC_4 180 67 #define EPC_5 181 68 #define EPC_6 182 69 #define EPC_7 183 70 #define DEPC 192 71 #define EPS_2 194 72 #define EPS_3 195 73 #define EPS_4 196 74 #define EPS_5 197 75 #define EPS_6 198 76 #define EPS_7 199 77 #define EXCSAVE_1 209 78 #define EXCSAVE_2 210 79 #define EXCSAVE_3 211 80 #define EXCSAVE_4 212 81 #define EXCSAVE_5 213 82 #define EXCSAVE_6 214 83 #define EXCSAVE_7 215 84 #define CPENABLE 224 85 #define INTERRUPT 226 86 #define INTENABLE 228 87 #define PS 230 88 #define VECBASE 231 89 #define EXCCAUSE 232 90 #define DEBUGCAUSE 233 91 #define CCOUNT 234 92 #define PRID 235 93 #define ICOUNT 236 94 #define ICOUNTLEVEL 237 95 #define EXCVADDR 238 96 #define CCOMPARE_0 240 97 #define CCOMPARE_1 241 98 #define CCOMPARE_2 242 99 #define MISC_REG_0 244 100 #define MISC_REG_1 245 101 102 /* Special cases (bases of special register series): */ 103 #define MR 32 104 #define IBREAKA 128 105 #define DBREAKA 144 106 #define DBREAKC 160 107 #define EPC 176 108 #define EPS 192 109 #define EXCSAVE 208 110 #define CCOMPARE 240 111 112 /* Special names for read-only and write-only interrupt registers: */ 113 #define INTREAD 226 114 #define INTSET 226 115 #define INTCLEAR 227 116 117 #endif /* XTENSA_SPECREG_H */ 118 119
