1 /* 2 * Xtensa Special Register symbolic names 3 */ 4 5 /* $Id: //depot/rel/Foxhill/dot.8/Xtensa/OS/include/xtensa/specreg.h#1 $ */ 6 7 /* 8 * Copyright (c) 2005-2011 Tensilica Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining 11 * a copy of this software and associated documentation files (the 12 * "Software"), to deal in the Software without restriction, including 13 * without limitation the rights to use, copy, modify, merge, publish, 14 * distribute, sublicense, and/or sell copies of the Software, and to 15 * permit persons to whom the Software is furnished to do so, subject to 16 * the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included 19 * in all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 22 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 23 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 24 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 25 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 26 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 27 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 28 */ 29 30 #ifndef XTENSA_SPECREG_H 31 #define XTENSA_SPECREG_H 32 33 /* Special registers: */ 34 #define LBEG 0 35 #define LEND 1 36 #define LCOUNT 2 37 #define SAR 3 38 #define BR 4 39 #define LITBASE 5 40 #define SCOMPARE1 12 41 #define ACCLO 16 42 #define ACCHI 17 43 #define MR_0 32 44 #define MR_1 33 45 #define MR_2 34 46 #define MR_3 35 47 #define PREFCTL 40 48 #define WINDOWBASE 72 49 #define WINDOWSTART 73 50 #define PTEVADDR 83 51 #define RASID 90 52 #define ITLBCFG 91 53 #define DTLBCFG 92 54 #define IBREAKENABLE 96 55 #define MEMCTL 97 56 #define CACHEATTR 98 /* until T1050, XEA1 */ 57 #define CACHEADRDIS 98 /* LX7+ */ 58 #define ATOMCTL 99 59 #define DDR 104 60 #define MECR 110 61 #define IBREAKA_0 128 62 #define IBREAKA_1 129 63 #define DBREAKA_0 144 64 #define DBREAKA_1 145 65 #define DBREAKC_0 160 66 #define DBREAKC_1 161 67 #define CONFIGID0 176 68 #define EPC_1 177 69 #define EPC_2 178 70 #define EPC_3 179 71 #define EPC_4 180 72 #define EPC_5 181 73 #define EPC_6 182 74 #define EPC_7 183 75 #define DEPC 192 76 #define EPS_2 194 77 #define EPS_3 195 78 #define EPS_4 196 79 #define EPS_5 197 80 #define EPS_6 198 81 #define EPS_7 199 82 #define CONFIGID1 208 83 #define EXCSAVE_1 209 84 #define EXCSAVE_2 210 85 #define EXCSAVE_3 211 86 #define EXCSAVE_4 212 87 #define EXCSAVE_5 213 88 #define EXCSAVE_6 214 89 #define EXCSAVE_7 215 90 #define CPENABLE 224 91 #define INTERRUPT 226 92 #define INTREAD INTERRUPT /* alternate name for backward compatibility */ 93 #define INTSET INTERRUPT /* alternate name for backward compatibility */ 94 #define INTCLEAR 227 95 #define INTENABLE 228 96 #define PS 230 97 #define VECBASE 231 98 #define EXCCAUSE 232 99 #define DEBUGCAUSE 233 100 #define CCOUNT 234 101 #define PRID 235 102 #define ICOUNT 236 103 #define ICOUNTLEVEL 237 104 #define EXCVADDR 238 105 #define CCOMPARE_0 240 106 #define CCOMPARE_1 241 107 #define CCOMPARE_2 242 108 #define MISC_REG_0 244 109 #define MISC_REG_1 245 110 #define MISC_REG_2 246 111 #define MISC_REG_3 247 112 113 /* Special cases (bases of special register series): */ 114 #define MR 32 115 #define IBREAKA 128 116 #define DBREAKA 144 117 #define DBREAKC 160 118 #define EPC 176 119 #define EPS 192 120 #define EXCSAVE 208 121 #define CCOMPARE 240 122 #define MISC_REG 244 123 124 /* Tensilica-defined user registers: */ 125 #if 0 126 /*#define ... 21..24 */ /* (545CK) */ 127 /*#define ... 140..143 */ /* (545CK) */ 128 #define EXPSTATE 230 /* Diamond */ 129 #define THREADPTR 231 /* threadptr option */ 130 #define FCR 232 /* FPU */ 131 #define FSR 233 /* FPU */ 132 #define AE_OVF_SAR 240 /* HiFi2 */ 133 #define AE_BITHEAD 241 /* HiFi2 */ 134 #define AE_TS_FTS_BU_BP 242 /* HiFi2 */ 135 #define AE_SD_NO 243 /* HiFi2 */ 136 #define VSAR 240 /* VectraLX */ 137 #define ROUND_LO 242 /* VectraLX */ 138 #define ROUND_HI 243 /* VectraLX */ 139 #define CBEGIN 246 /* VectraLX */ 140 #define CEND 247 /* VectraLX */ 141 #endif 142 143 #endif /* XTENSA_SPECREG_H */ 144 145
