1 /* Definitions for Xtensa processor config info needed for TRAX. 2 3 Copyright (c) 2005-2011 Tensilica Inc. 4 5 Permission is hereby granted, free of charge, to any person obtaining 6 a copy of this software and associated documentation files (the 7 "Software"), to deal in the Software without restriction, including 8 without limitation the rights to use, copy, modify, merge, publish, 9 distribute, sublicense, and/or sell copies of the Software, and to 10 permit persons to whom the Software is furnished to do so, subject to 11 the following conditions: 12 13 The above copyright notice and this permission notice shall be included 14 in all copies or substantial portions of the Software. 15 16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 17 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24 #ifndef TRAX_CORE_CONFIG_H 25 #define TRAX_CORE_CONFIG_H 26 27 #include "xtensa-params.h" 28 29 /* 30 * Vector Enumerations. 31 */ 32 33 /* These must match the LX2.0 and later traceport spec: */ 34 #define VEC_NO_VECTOR 0 35 #define VEC_FIRST VEC_RESET /* first valid vector */ 36 #define VEC_RESET 1 37 #define VEC_DEBUG 2 38 #define VEC_NMI 3 39 #define VEC_USER 4 40 #define VEC_KERNEL 5 41 #define VEC_DOUBLE 6 42 #define VEC_MEMERR 7 43 #define VEC_RESERVED8 8 44 #define VEC_RESERVED9 9 45 #define VEC_WINO4 10 46 #define VEC_WINU4 11 47 #define VEC_WINO8 12 48 #define VEC_WINU8 13 49 #define VEC_WINO12 14 50 #define VEC_WINU12 15 51 #define VEC_INTLEVEL2 16 52 #define VEC_INTLEVEL3 17 53 #define VEC_INTLEVEL4 18 54 #define VEC_INTLEVEL5 19 55 #define VEC_INTLEVEL6 20 56 /* These are internal, i.e. don't appear like this on traceport: */ 57 #define VEC_DEBUG_OCD 21 58 #define VEC_UNKNOWN 22 59 /* Enumerations 23 through 31 are also reserved, but putting */ 60 /* placeholders here seems wasteful and unnecessary. */ 61 #define VEC_COUNT 23 62 63 /* Other branch (change-of-PC-flow) type encodings; 64 * if PC changes due to an exception or interrupt vector, 65 * one of the VEC_* values above is used, otherwise 66 * (or if it's unknown whether it's due to an exception/interrupt) 67 * one of the following is used: */ 68 69 #define BRANCH_IS_VEC(n) ((n) < VEC_COUNT) /* is known to be except/interrupt? */ 70 #define BRANCH_OR_VEC 24 /* unknown type of branch (branch/exception/interrupt/etc) */ 71 #define BRANCH_UNKNOWN 25 /* unknown type of branch (anything but except/interrupt) */ 72 #define BRANCH_UNKNOWN_ERR 26 /* like BRANCH_UNKNOWN with known error (non-branch instr) */ 73 #define BRANCH_LOOPBACK 28 /* zero-overhead loopback (from LEND to LBEG) */ 74 #define BRANCH_CONDTAKEN 29 /* conditional branch taken (or LOOP{NEZ,GTZ} loop skip) */ 75 #define BRANCH_JUMP 30 /* jump (unconditional branch, i.e. J or JX) */ 76 #define BRANCH_IS_CALL(n) (((n) & ~3) == 32) /* is a function call? */ 77 #define BRANCH_CALL0 32 /* non-windowed function call (CALL0, CALLX0) */ 78 #define BRANCH_CALL4 33 /* windowed function call (CALL4, CALLX4) */ 79 #define BRANCH_CALL8 34 /* windowed function call (CALL8, CALLX8) */ 80 #define BRANCH_CALL12 35 /* windowed function call (CALL12, CALLX12) */ 81 #define BRANCH_IS_RETURN(n) ((n) >= 36) /* is any kind of return? */ 82 #define BRANCH_IS_CALLRETURN(n) (((n) & ~1) == 36) /* is a function return? */ 83 #define BRANCH_RET 36 /* non-windowed function return (RET or RET.N) */ 84 #define BRANCH_RETW 37 /* windowed function return (RETW or RETW.N) */ 85 #define BRANCH_IS_EIRETURN(n) ((n) >= 38) /* is an except/inter. return? */ 86 #define BRANCH_RFE 38 /* RFE or RFUE */ 87 #define BRANCH_RFDE 39 /* RFDE */ 88 #define BRANCH_RFWO 40 /* RFWO */ 89 #define BRANCH_RFWU 41 /* RFWU */ 90 #define BRANCH_RFI_2 42 /* RFI 2 */ 91 #define BRANCH_RFI_3 43 /* RFI 3 */ 92 #define BRANCH_RFI_4 44 /* RFI 4 */ 93 #define BRANCH_RFI_5 45 /* RFI 5 */ 94 #define BRANCH_RFI_6 46 /* RFI 6 */ 95 #define BRANCH_RFI_NMI 47 /* RFI NMILEVEL */ 96 #define BRANCH_RFI_DEBUG 48 /* RFI DEBUGLEVEL */ 97 #define BRANCH_RFME 49 /* RFME */ 98 #define BRANCH_COUNT 50 /* (number of defined BRANCH_xxx values) */ 99 100 101 102 typedef struct { 103 unsigned vaddr; 104 unsigned vaddr2; /* for static vectors only (reloc vectors option) */ 105 int is_configured; 106 } trax_vector_t; 107 108 109 /* 110 * This structure describes those portion of a Tensilica processor's 111 * configuration that are useful for trace. 112 */ 113 typedef struct { 114 char ** isa_dlls; 115 char * core_name; /* (XPG core name, not necessarily same as XTENSA_CORE) */ 116 int big_endian; /* 0 = little-endian, 1 = big-endian */ 117 int has_loops; /* 1 = zero overhead loops configured */ 118 int has_autorefill; /* 1 = TLB autorefill (MMU) configured */ 119 unsigned max_instr_size; /* in bytes (eg. 3, 4, 8, ...) */ 120 unsigned int_level_max; /* number of interrupt levels configured (without NMI) */ 121 int debug_level; /* debug intlevel, 0 if debug not configured */ 122 int nmi_level; /* NMI intlevel, 0 if NMI not configured */ 123 unsigned targethw_min; /* min. targeted hardware version (XTENSA_HWVERSION_<rel>) */ 124 unsigned targethw_max; /* max. targeted hardware version (XTENSA_HWVERSION_<rel>) */ 125 int reloc_vectors; /* 0 = fixed vectors, 1 = relocatable vectors */ 126 int statvec_select; /* 0 = stat vec base 0, 1 = stat vec base 1 (SW default) */ 127 int vecbase_align; /* number of bits to align VECBASE (32 - bits in VECBASE) */ 128 unsigned statvec_base0; /* static vector base 0 */ 129 unsigned statvec_base1; /* static vector base 1 */ 130 unsigned vecbase_reset; /* reset value of VECBASE */ 131 trax_vector_t vectors[VEC_COUNT]; /* all vectors... */ 132 } trax_core_config_t; 133 134 135 /* Globals: */ 136 //extern const char * const trax_vector_short_names[/*VEC_COUNT*/]; // nobody uses this one 137 extern const char * const trax_vector_names[/*VEC_COUNT*/]; 138 139 /* Prototypes: */ 140 extern int trax_read_params (trax_core_config_t *c, xtensa_params p); 141 extern int trax_vector_from_address(trax_core_config_t *config, unsigned long vaddr, unsigned long *vecbases); 142 143 #endif /* TRAX_CORE_CONFIG_H */ 144 145
