1 /* 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file contains assembly-language definitions (assembly 8 macros, etc.) for this specific Xtensa processor's TIE extensions 9 and options. It is customized to this Xtensa processor configuration. 10 11 Customer ID=15837; Build=0xa1536; Copyright (c) 1999-2022 Cadence Design Systems Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #ifndef _XTENSA_CORE_TIE_ASM_H 33 #define _XTENSA_CORE_TIE_ASM_H 34 35 #include <xtensa/coreasm.h> 36 37 /* Selection parameter values for save-area save/restore macros: */ 38 /* Option vs. TIE: */ 39 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 40 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 41 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 42 /* Whether used automatically by compiler: */ 43 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 44 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 45 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 46 /* ABI handling across function calls: */ 47 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 48 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 49 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 50 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 51 /* Misc */ 52 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 53 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 54 | ((ccuse) & XTHAL_SAS_ANYCC) \ 55 | ((abi) & XTHAL_SAS_ANYABI) ) 56 57 58 /* 59 * Macro to store all non-coprocessor (extra) custom TIE and optional state 60 * (not including zero-overhead loop registers). 61 * Required parameters: 62 * ptr Save area pointer address register (clobbered) 63 * (register must contain a 4 byte aligned address). 64 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 65 * registers are clobbered, the remaining are unused). 66 * Optional parameters: 67 * continue If macro invoked as part of a larger store sequence, set to 1 68 * if this is not the first in the sequence. Defaults to 0. 69 * ofs Offset from start of larger sequence (from value of first ptr 70 * in sequence) at which to store. Defaults to next available space 71 * (or 0 if <continue> is 0). 72 * select Select what category(ies) of registers to store, as a bitmask 73 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 74 * alloc Select what category(ies) of registers to allocate; if any 75 * category is selected here that is not in <select>, space for 76 * the corresponding registers is skipped without doing any store. 77 */ 78 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 79 xchal_sa_start \continue, \ofs 80 // Optional global registers used by default by the compiler: 81 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 82 xchal_sa_align \ptr, 0, 1016, 4, 4 83 rur.threadptr \at1 // threadptr option 84 s32i \at1, \ptr, .Lxchal_ofs_+0 85 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 86 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 87 xchal_sa_align \ptr, 0, 1016, 4, 4 88 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 89 .endif 90 // Optional caller-saved registers not used by default by the compiler: 91 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 92 xchal_sa_align \ptr, 0, 1016, 4, 4 93 rsr.br \at1 // boolean option 94 s32i \at1, \ptr, .Lxchal_ofs_+0 95 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 96 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 97 xchal_sa_align \ptr, 0, 1016, 4, 4 98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 99 .endif 100 .endm // xchal_ncp_store 101 102 /* 103 * Macro to load all non-coprocessor (extra) custom TIE and optional state 104 * (not including zero-overhead loop registers). 105 * Required parameters: 106 * ptr Save area pointer address register (clobbered) 107 * (register must contain a 4 byte aligned address). 108 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 109 * registers are clobbered, the remaining are unused). 110 * Optional parameters: 111 * continue If macro invoked as part of a larger load sequence, set to 1 112 * if this is not the first in the sequence. Defaults to 0. 113 * ofs Offset from start of larger sequence (from value of first ptr 114 * in sequence) at which to load. Defaults to next available space 115 * (or 0 if <continue> is 0). 116 * select Select what category(ies) of registers to load, as a bitmask 117 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 118 * alloc Select what category(ies) of registers to allocate; if any 119 * category is selected here that is not in <select>, space for 120 * the corresponding registers is skipped without doing any load. 121 */ 122 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 123 xchal_sa_start \continue, \ofs 124 // Optional global registers used by default by the compiler: 125 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 126 xchal_sa_align \ptr, 0, 1016, 4, 4 127 l32i \at1, \ptr, .Lxchal_ofs_+0 128 wur.threadptr \at1 // threadptr option 129 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 130 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 131 xchal_sa_align \ptr, 0, 1016, 4, 4 132 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 133 .endif 134 // Optional caller-saved registers not used by default by the compiler: 135 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 136 xchal_sa_align \ptr, 0, 1016, 4, 4 137 l32i \at1, \ptr, .Lxchal_ofs_+0 138 wsr.br \at1 // boolean option 139 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 140 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 141 xchal_sa_align \ptr, 0, 1016, 4, 4 142 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 143 .endif 144 .endm // xchal_ncp_load 145 146 147 #define XCHAL_NCP_NUM_ATMPS 1 148 149 /* 150 * Macro to store the state of TIE coprocessor AudioEngineLX. 151 * Required parameters: 152 * ptr Save area pointer address register (clobbered) 153 * (register must contain a 8 byte aligned address). 154 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 155 * registers are clobbered, the remaining are unused). 156 * Optional parameters are the same as for xchal_ncp_store. 157 */ 158 #define xchal_cp_AudioEngineLX_store xchal_cp1_store 159 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 160 xchal_sa_start \continue, \ofs 161 // Custom caller-saved registers not used by default by the compiler: 162 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 163 xchal_sa_align \ptr, 0, 0, 8, 8 164 ae_s64.i aed0, \ptr, .Lxchal_ofs_+40 165 ae_s64.i aed1, \ptr, .Lxchal_ofs_+48 166 ae_s64.i aed2, \ptr, .Lxchal_ofs_+56 167 addi \ptr, \ptr, 64 168 ae_s64.i aed3, \ptr, .Lxchal_ofs_+0 169 ae_s64.i aed4, \ptr, .Lxchal_ofs_+8 170 ae_s64.i aed5, \ptr, .Lxchal_ofs_+16 171 ae_s64.i aed6, \ptr, .Lxchal_ofs_+24 172 ae_s64.i aed7, \ptr, .Lxchal_ofs_+32 173 ae_s64.i aed8, \ptr, .Lxchal_ofs_+40 174 ae_s64.i aed9, \ptr, .Lxchal_ofs_+48 175 ae_s64.i aed10, \ptr, .Lxchal_ofs_+56 176 addi \ptr, \ptr, 64 177 ae_s64.i aed11, \ptr, .Lxchal_ofs_+0 178 ae_s64.i aed12, \ptr, .Lxchal_ofs_+8 179 ae_s64.i aed13, \ptr, .Lxchal_ofs_+16 180 ae_s64.i aed14, \ptr, .Lxchal_ofs_+24 181 ae_s64.i aed15, \ptr, .Lxchal_ofs_+32 182 ae_movae \at1, aep0 183 s8i \at1, \ptr, .Lxchal_ofs_+40 184 ae_movae \at1, aep1 185 s8i \at1, \ptr, .Lxchal_ofs_+41 186 ae_movae \at1, aep2 187 s8i \at1, \ptr, .Lxchal_ofs_+42 188 ae_movae \at1, aep3 189 s8i \at1, \ptr, .Lxchal_ofs_+43 190 ae_salign64.i u0, \ptr, .Lxchal_ofs_+48 191 ae_salign64.i u1, \ptr, .Lxchal_ofs_+56 192 addi \ptr, \ptr, 64 193 ae_salign64.i u2, \ptr, .Lxchal_ofs_+0 194 ae_salign64.i u3, \ptr, .Lxchal_ofs_+8 195 addi \ptr, \ptr, -192 196 ae_movvfcrfsr aed0 // ureg FCR_FSR 197 ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 198 rur.ae_ovf_sar \at1 // ureg 240 199 s32i \at1, \ptr, .Lxchal_ofs_+8 200 rur.ae_bithead \at1 // ureg 241 201 s32i \at1, \ptr, .Lxchal_ofs_+12 202 rur.ae_ts_fts_bu_bp \at1 // ureg 242 203 s32i \at1, \ptr, .Lxchal_ofs_+16 204 rur.ae_cw_sd_no \at1 // ureg 243 205 s32i \at1, \ptr, .Lxchal_ofs_+20 206 rur.ae_cbegin0 \at1 // ureg 246 207 s32i \at1, \ptr, .Lxchal_ofs_+24 208 rur.ae_cend0 \at1 // ureg 247 209 s32i \at1, \ptr, .Lxchal_ofs_+28 210 rur.ae_cbegin1 \at1 // ureg 248 211 s32i \at1, \ptr, .Lxchal_ofs_+32 212 rur.ae_cend1 \at1 // ureg 249 213 s32i \at1, \ptr, .Lxchal_ofs_+36 214 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 215 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 216 xchal_sa_align \ptr, 0, 0, 8, 8 217 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 218 .endif 219 .endm // xchal_cp1_store 220 221 /* 222 * Macro to load the state of TIE coprocessor AudioEngineLX. 223 * Required parameters: 224 * ptr Save area pointer address register (clobbered) 225 * (register must contain a 8 byte aligned address). 226 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 227 * registers are clobbered, the remaining are unused). 228 * Optional parameters are the same as for xchal_ncp_load. 229 */ 230 #define xchal_cp_AudioEngineLX_load xchal_cp1_load 231 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 232 xchal_sa_start \continue, \ofs 233 // Custom caller-saved registers not used by default by the compiler: 234 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 235 xchal_sa_align \ptr, 0, 0, 8, 8 236 ae_l64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 // ureg FCR_FSR 237 ae_movfcrfsrv aed0 238 l32i \at1, \ptr, .Lxchal_ofs_+8 239 wur.ae_ovf_sar \at1 // ureg 240 240 l32i \at1, \ptr, .Lxchal_ofs_+12 241 wur.ae_bithead \at1 // ureg 241 242 l32i \at1, \ptr, .Lxchal_ofs_+16 243 wur.ae_ts_fts_bu_bp \at1 // ureg 242 244 l32i \at1, \ptr, .Lxchal_ofs_+20 245 wur.ae_cw_sd_no \at1 // ureg 243 246 l32i \at1, \ptr, .Lxchal_ofs_+24 247 wur.ae_cbegin0 \at1 // ureg 246 248 l32i \at1, \ptr, .Lxchal_ofs_+28 249 wur.ae_cend0 \at1 // ureg 247 250 l32i \at1, \ptr, .Lxchal_ofs_+32 251 wur.ae_cbegin1 \at1 // ureg 248 252 l32i \at1, \ptr, .Lxchal_ofs_+36 253 wur.ae_cend1 \at1 // ureg 249 254 ae_l64.i aed0, \ptr, .Lxchal_ofs_+40 255 ae_l64.i aed1, \ptr, .Lxchal_ofs_+48 256 ae_l64.i aed2, \ptr, .Lxchal_ofs_+56 257 addi \ptr, \ptr, 64 258 ae_l64.i aed3, \ptr, .Lxchal_ofs_+0 259 ae_l64.i aed4, \ptr, .Lxchal_ofs_+8 260 ae_l64.i aed5, \ptr, .Lxchal_ofs_+16 261 ae_l64.i aed6, \ptr, .Lxchal_ofs_+24 262 ae_l64.i aed7, \ptr, .Lxchal_ofs_+32 263 ae_l64.i aed8, \ptr, .Lxchal_ofs_+40 264 ae_l64.i aed9, \ptr, .Lxchal_ofs_+48 265 ae_l64.i aed10, \ptr, .Lxchal_ofs_+56 266 addi \ptr, \ptr, 64 267 ae_l64.i aed11, \ptr, .Lxchal_ofs_+0 268 ae_l64.i aed12, \ptr, .Lxchal_ofs_+8 269 ae_l64.i aed13, \ptr, .Lxchal_ofs_+16 270 ae_l64.i aed14, \ptr, .Lxchal_ofs_+24 271 ae_l64.i aed15, \ptr, .Lxchal_ofs_+32 272 addi \ptr, \ptr, 40 273 l8ui \at1, \ptr, .Lxchal_ofs_+0 274 ae_movea aep0, \at1 275 l8ui \at1, \ptr, .Lxchal_ofs_+1 276 ae_movea aep1, \at1 277 l8ui \at1, \ptr, .Lxchal_ofs_+2 278 ae_movea aep2, \at1 279 l8ui \at1, \ptr, .Lxchal_ofs_+3 280 ae_movea aep3, \at1 281 addi \ptr, \ptr, 8 282 ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 283 ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 284 ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 285 ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 286 .set .Lxchal_pofs_, .Lxchal_pofs_ + 176 287 .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 288 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 289 xchal_sa_align \ptr, 0, 0, 8, 8 290 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 291 .endif 292 .endm // xchal_cp1_load 293 294 #define XCHAL_CP1_NUM_ATMPS 1 295 #define XCHAL_SA_NUM_ATMPS 1 296 297 /* Empty macros for unconfigured coprocessors: */ 298 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 299 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 300 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 301 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 302 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 303 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 304 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 305 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 306 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 307 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 308 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 309 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 310 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 311 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 312 313 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 314 315
