1 /* 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file contains assembly-language definitions (assembly 8 macros, etc.) for this specific Xtensa processor's TIE extensions 9 and options. It is customized to this Xtensa processor configuration. 10 11 Copyright (c) 1999-2018 Cadence Design Systems Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #if !defined __XCC__ 33 34 #ifndef _XTENSA_CORE_TIE_ASM_H 35 #define _XTENSA_CORE_TIE_ASM_H 36 37 /* Selection parameter values for save-area save/restore macros: */ 38 /* Option vs. TIE: */ 39 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 40 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 41 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 42 /* Whether used automatically by compiler: */ 43 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 44 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 45 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 46 /* ABI handling across function calls: */ 47 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 48 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 49 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 50 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 51 /* Misc */ 52 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 53 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 54 | ((ccuse) & XTHAL_SAS_ANYCC) \ 55 | ((abi) & XTHAL_SAS_ANYABI) ) 56 57 58 /* 59 * Macro to store all non-coprocessor (extra) custom TIE and optional state 60 * (not including zero-overhead loop registers). 61 * Required parameters: 62 * ptr Save area pointer address register (clobbered) 63 * (register must contain a 4 byte aligned address). 64 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 65 * registers are clobbered, the remaining are unused). 66 * Optional parameters: 67 * continue If macro invoked as part of a larger store sequence, set to 1 68 * if this is not the first in the sequence. Defaults to 0. 69 * ofs Offset from start of larger sequence (from value of first ptr 70 * in sequence) at which to store. Defaults to next available space 71 * (or 0 if <continue> is 0). 72 * select Select what category(ies) of registers to store, as a bitmask 73 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 74 * alloc Select what category(ies) of registers to allocate; if any 75 * category is selected here that is not in <select>, space for 76 * the corresponding registers is skipped without doing any store. 77 */ 78 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 79 xchal_sa_start \continue, \ofs 80 // Optional global registers used by default by the compiler: 81 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 82 xchal_sa_align \ptr, 0, 1016, 4, 4 83 rur.THREADPTR \at1 // threadptr option 84 s32i \at1, \ptr, .Lxchal_ofs_+0 85 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 86 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 87 xchal_sa_align \ptr, 0, 1016, 4, 4 88 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 89 .endif 90 // Optional caller-saved registers not used by default by the compiler: 91 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 92 xchal_sa_align \ptr, 0, 1012, 4, 4 93 rsr.BR \at1 // boolean option 94 s32i \at1, \ptr, .Lxchal_ofs_+0 95 rsr.SCOMPARE1 \at1 // conditional store option 96 s32i \at1, \ptr, .Lxchal_ofs_+4 97 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 98 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 99 xchal_sa_align \ptr, 0, 1012, 4, 4 100 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 101 .endif 102 .endm // xchal_ncp_store 103 104 /* 105 * Macro to load all non-coprocessor (extra) custom TIE and optional state 106 * (not including zero-overhead loop registers). 107 * Required parameters: 108 * ptr Save area pointer address register (clobbered) 109 * (register must contain a 4 byte aligned address). 110 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 111 * registers are clobbered, the remaining are unused). 112 * Optional parameters: 113 * continue If macro invoked as part of a larger load sequence, set to 1 114 * if this is not the first in the sequence. Defaults to 0. 115 * ofs Offset from start of larger sequence (from value of first ptr 116 * in sequence) at which to load. Defaults to next available space 117 * (or 0 if <continue> is 0). 118 * select Select what category(ies) of registers to load, as a bitmask 119 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 120 * alloc Select what category(ies) of registers to allocate; if any 121 * category is selected here that is not in <select>, space for 122 * the corresponding registers is skipped without doing any load. 123 */ 124 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 125 xchal_sa_start \continue, \ofs 126 // Optional global registers used by default by the compiler: 127 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 128 xchal_sa_align \ptr, 0, 1016, 4, 4 129 l32i \at1, \ptr, .Lxchal_ofs_+0 130 wur.THREADPTR \at1 // threadptr option 131 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 132 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 133 xchal_sa_align \ptr, 0, 1016, 4, 4 134 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 135 .endif 136 // Optional caller-saved registers not used by default by the compiler: 137 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 138 xchal_sa_align \ptr, 0, 1012, 4, 4 139 l32i \at1, \ptr, .Lxchal_ofs_+0 140 wsr.BR \at1 // boolean option 141 l32i \at1, \ptr, .Lxchal_ofs_+4 142 wsr.SCOMPARE1 \at1 // conditional store option 143 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 144 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 145 xchal_sa_align \ptr, 0, 1012, 4, 4 146 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 147 .endif 148 .endm // xchal_ncp_load 149 150 151 #define XCHAL_NCP_NUM_ATMPS 1 152 153 /* 154 * Macro to store the state of TIE coprocessor FPU. 155 * Required parameters: 156 * ptr Save area pointer address register (clobbered) 157 * (register must contain a 4 byte aligned address). 158 * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS 159 * registers are clobbered, the remaining are unused). 160 * Optional parameters are the same as for xchal_ncp_store. 161 */ 162 #define xchal_cp_FPU_store xchal_cp0_store 163 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 164 xchal_sa_start \continue, \ofs 165 // Custom caller-saved registers not used by default by the compiler: 166 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 167 xchal_sa_align \ptr, 0, 948, 4, 4 168 rur.FCR \at1 // ureg 232 169 s32i \at1, \ptr, .Lxchal_ofs_+0 170 rur.FSR \at1 // ureg 233 171 s32i \at1, \ptr, .Lxchal_ofs_+4 172 ssi f0, \ptr, .Lxchal_ofs_+8 173 ssi f1, \ptr, .Lxchal_ofs_+12 174 ssi f2, \ptr, .Lxchal_ofs_+16 175 ssi f3, \ptr, .Lxchal_ofs_+20 176 ssi f4, \ptr, .Lxchal_ofs_+24 177 ssi f5, \ptr, .Lxchal_ofs_+28 178 ssi f6, \ptr, .Lxchal_ofs_+32 179 ssi f7, \ptr, .Lxchal_ofs_+36 180 ssi f8, \ptr, .Lxchal_ofs_+40 181 ssi f9, \ptr, .Lxchal_ofs_+44 182 ssi f10, \ptr, .Lxchal_ofs_+48 183 ssi f11, \ptr, .Lxchal_ofs_+52 184 ssi f12, \ptr, .Lxchal_ofs_+56 185 ssi f13, \ptr, .Lxchal_ofs_+60 186 ssi f14, \ptr, .Lxchal_ofs_+64 187 ssi f15, \ptr, .Lxchal_ofs_+68 188 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 189 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 190 xchal_sa_align \ptr, 0, 948, 4, 4 191 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 192 .endif 193 .endm // xchal_cp0_store 194 195 /* 196 * Macro to load the state of TIE coprocessor FPU. 197 * Required parameters: 198 * ptr Save area pointer address register (clobbered) 199 * (register must contain a 4 byte aligned address). 200 * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS 201 * registers are clobbered, the remaining are unused). 202 * Optional parameters are the same as for xchal_ncp_load. 203 */ 204 #define xchal_cp_FPU_load xchal_cp0_load 205 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 206 xchal_sa_start \continue, \ofs 207 // Custom caller-saved registers not used by default by the compiler: 208 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 209 xchal_sa_align \ptr, 0, 948, 4, 4 210 l32i \at1, \ptr, .Lxchal_ofs_+0 211 wur.FCR \at1 // ureg 232 212 l32i \at1, \ptr, .Lxchal_ofs_+4 213 wur.FSR \at1 // ureg 233 214 lsi f0, \ptr, .Lxchal_ofs_+8 215 lsi f1, \ptr, .Lxchal_ofs_+12 216 lsi f2, \ptr, .Lxchal_ofs_+16 217 lsi f3, \ptr, .Lxchal_ofs_+20 218 lsi f4, \ptr, .Lxchal_ofs_+24 219 lsi f5, \ptr, .Lxchal_ofs_+28 220 lsi f6, \ptr, .Lxchal_ofs_+32 221 lsi f7, \ptr, .Lxchal_ofs_+36 222 lsi f8, \ptr, .Lxchal_ofs_+40 223 lsi f9, \ptr, .Lxchal_ofs_+44 224 lsi f10, \ptr, .Lxchal_ofs_+48 225 lsi f11, \ptr, .Lxchal_ofs_+52 226 lsi f12, \ptr, .Lxchal_ofs_+56 227 lsi f13, \ptr, .Lxchal_ofs_+60 228 lsi f14, \ptr, .Lxchal_ofs_+64 229 lsi f15, \ptr, .Lxchal_ofs_+68 230 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 231 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 232 xchal_sa_align \ptr, 0, 948, 4, 4 233 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 234 .endif 235 .endm // xchal_cp0_load 236 237 #define XCHAL_CP0_NUM_ATMPS 1 238 /* 239 * Macro to store the state of TIE coprocessor AudioEngineLX. 240 * Required parameters: 241 * ptr Save area pointer address register (clobbered) 242 * (register must contain a 8 byte aligned address). 243 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 244 * registers are clobbered, the remaining are unused). 245 * Optional parameters are the same as for xchal_ncp_store. 246 */ 247 #define xchal_cp_AudioEngineLX_store xchal_cp1_store 248 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 249 xchal_sa_start \continue, \ofs 250 // Custom caller-saved registers not used by default by the compiler: 251 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 252 xchal_sa_align \ptr, 0, 0, 8, 8 253 rur.AE_OVF_SAR \at1 // ureg 240 254 s32i \at1, \ptr, .Lxchal_ofs_+0 255 rur.AE_BITHEAD \at1 // ureg 241 256 s32i \at1, \ptr, .Lxchal_ofs_+4 257 rur.AE_TS_FTS_BU_BP \at1 // ureg 242 258 s32i \at1, \ptr, .Lxchal_ofs_+8 259 rur.AE_CW_SD_NO \at1 // ureg 243 260 s32i \at1, \ptr, .Lxchal_ofs_+12 261 rur.AE_CBEGIN0 \at1 // ureg 246 262 s32i \at1, \ptr, .Lxchal_ofs_+16 263 rur.AE_CEND0 \at1 // ureg 247 264 s32i \at1, \ptr, .Lxchal_ofs_+20 265 ae_s64.i aed0, \ptr, .Lxchal_ofs_+24 266 ae_s64.i aed1, \ptr, .Lxchal_ofs_+32 267 ae_s64.i aed2, \ptr, .Lxchal_ofs_+40 268 ae_s64.i aed3, \ptr, .Lxchal_ofs_+48 269 ae_s64.i aed4, \ptr, .Lxchal_ofs_+56 270 addi \ptr, \ptr, 64 271 ae_s64.i aed5, \ptr, .Lxchal_ofs_+0 272 ae_s64.i aed6, \ptr, .Lxchal_ofs_+8 273 ae_s64.i aed7, \ptr, .Lxchal_ofs_+16 274 ae_s64.i aed8, \ptr, .Lxchal_ofs_+24 275 ae_s64.i aed9, \ptr, .Lxchal_ofs_+32 276 ae_s64.i aed10, \ptr, .Lxchal_ofs_+40 277 ae_s64.i aed11, \ptr, .Lxchal_ofs_+48 278 ae_s64.i aed12, \ptr, .Lxchal_ofs_+56 279 addi \ptr, \ptr, 64 280 ae_s64.i aed13, \ptr, .Lxchal_ofs_+0 281 ae_s64.i aed14, \ptr, .Lxchal_ofs_+8 282 ae_s64.i aed15, \ptr, .Lxchal_ofs_+16 283 ae_salign64.i u0, \ptr, .Lxchal_ofs_+24 284 ae_salign64.i u1, \ptr, .Lxchal_ofs_+32 285 ae_salign64.i u2, \ptr, .Lxchal_ofs_+40 286 ae_salign64.i u3, \ptr, .Lxchal_ofs_+48 287 .set .Lxchal_pofs_, .Lxchal_pofs_ + 128 288 .set .Lxchal_ofs_, .Lxchal_ofs_ + 56 289 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 290 xchal_sa_align \ptr, 0, 0, 8, 8 291 .set .Lxchal_ofs_, .Lxchal_ofs_ + 184 292 .endif 293 .endm // xchal_cp1_store 294 295 /* 296 * Macro to load the state of TIE coprocessor AudioEngineLX. 297 * Required parameters: 298 * ptr Save area pointer address register (clobbered) 299 * (register must contain a 8 byte aligned address). 300 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 301 * registers are clobbered, the remaining are unused). 302 * Optional parameters are the same as for xchal_ncp_load. 303 */ 304 #define xchal_cp_AudioEngineLX_load xchal_cp1_load 305 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 306 xchal_sa_start \continue, \ofs 307 // Custom caller-saved registers not used by default by the compiler: 308 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 309 xchal_sa_align \ptr, 0, 0, 8, 8 310 l32i \at1, \ptr, .Lxchal_ofs_+0 311 wur.AE_OVF_SAR \at1 // ureg 240 312 l32i \at1, \ptr, .Lxchal_ofs_+4 313 wur.AE_BITHEAD \at1 // ureg 241 314 l32i \at1, \ptr, .Lxchal_ofs_+8 315 wur.AE_TS_FTS_BU_BP \at1 // ureg 242 316 l32i \at1, \ptr, .Lxchal_ofs_+12 317 wur.AE_CW_SD_NO \at1 // ureg 243 318 l32i \at1, \ptr, .Lxchal_ofs_+16 319 wur.AE_CBEGIN0 \at1 // ureg 246 320 l32i \at1, \ptr, .Lxchal_ofs_+20 321 wur.AE_CEND0 \at1 // ureg 247 322 ae_l64.i aed0, \ptr, .Lxchal_ofs_+24 323 ae_l64.i aed1, \ptr, .Lxchal_ofs_+32 324 ae_l64.i aed2, \ptr, .Lxchal_ofs_+40 325 ae_l64.i aed3, \ptr, .Lxchal_ofs_+48 326 ae_l64.i aed4, \ptr, .Lxchal_ofs_+56 327 addi \ptr, \ptr, 64 328 ae_l64.i aed5, \ptr, .Lxchal_ofs_+0 329 ae_l64.i aed6, \ptr, .Lxchal_ofs_+8 330 ae_l64.i aed7, \ptr, .Lxchal_ofs_+16 331 ae_l64.i aed8, \ptr, .Lxchal_ofs_+24 332 ae_l64.i aed9, \ptr, .Lxchal_ofs_+32 333 ae_l64.i aed10, \ptr, .Lxchal_ofs_+40 334 ae_l64.i aed11, \ptr, .Lxchal_ofs_+48 335 ae_l64.i aed12, \ptr, .Lxchal_ofs_+56 336 addi \ptr, \ptr, 64 337 ae_l64.i aed13, \ptr, .Lxchal_ofs_+0 338 ae_l64.i aed14, \ptr, .Lxchal_ofs_+8 339 ae_l64.i aed15, \ptr, .Lxchal_ofs_+16 340 addi \ptr, \ptr, 24 341 ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 342 ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 343 ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 344 ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 345 .set .Lxchal_pofs_, .Lxchal_pofs_ + 152 346 .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 347 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 348 xchal_sa_align \ptr, 0, 0, 8, 8 349 .set .Lxchal_ofs_, .Lxchal_ofs_ + 184 350 .endif 351 .endm // xchal_cp1_load 352 353 #define XCHAL_CP1_NUM_ATMPS 1 354 #define XCHAL_SA_NUM_ATMPS 1 355 356 /* Empty macros for unconfigured coprocessors: */ 357 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 358 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 359 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 360 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 361 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 362 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 363 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 364 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 365 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 366 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 367 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 368 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 369 370 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 371 372 #else 373 374 #error "xcc should not use this header" 375 376 #endif /* __XCC__ */ 377
