1 /* 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file contains assembly-language definitions (assembly 8 macros, etc.) for this specific Xtensa processor's TIE extensions 9 and options. It is customized to this Xtensa processor configuration. 10 11 Copyright (c) 1999-2022 Cadence Design Systems Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #ifndef _XTENSA_CORE_TIE_ASM_H 33 #define _XTENSA_CORE_TIE_ASM_H 34 35 #include <xtensa/coreasm.h> 36 37 /* Selection parameter values for save-area save/restore macros: */ 38 /* Option vs. TIE: */ 39 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 40 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 41 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 42 /* Whether used automatically by compiler: */ 43 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 44 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 45 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 46 /* ABI handling across function calls: */ 47 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 48 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 49 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 50 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 51 /* Misc */ 52 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 53 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 54 | ((ccuse) & XTHAL_SAS_ANYCC) \ 55 | ((abi) & XTHAL_SAS_ANYABI) ) 56 57 58 /* 59 * Macro to store all non-coprocessor (extra) custom TIE and optional state 60 * (not including zero-overhead loop registers). 61 * Required parameters: 62 * ptr Save area pointer address register (clobbered) 63 * (register must contain a 4 byte aligned address). 64 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 65 * registers are clobbered, the remaining are unused). 66 * Optional parameters: 67 * continue If macro invoked as part of a larger store sequence, set to 1 68 * if this is not the first in the sequence. Defaults to 0. 69 * ofs Offset from start of larger sequence (from value of first ptr 70 * in sequence) at which to store. Defaults to next available space 71 * (or 0 if <continue> is 0). 72 * select Select what category(ies) of registers to store, as a bitmask 73 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 74 * alloc Select what category(ies) of registers to allocate; if any 75 * category is selected here that is not in <select>, space for 76 * the corresponding registers is skipped without doing any store. 77 */ 78 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 79 xchal_sa_start \continue, \ofs 80 // Optional global registers used by default by the compiler: 81 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 82 xchal_sa_align \ptr, 0, 1016, 4, 4 83 rur.threadptr \at1 // threadptr option 84 s32i \at1, \ptr, .Lxchal_ofs_+0 85 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 86 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 87 xchal_sa_align \ptr, 0, 1016, 4, 4 88 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 89 .endif 90 // Optional caller-saved registers not used by default by the compiler: 91 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 92 xchal_sa_align \ptr, 0, 1012, 4, 4 93 rsr.br \at1 // boolean option 94 s32i \at1, \ptr, .Lxchal_ofs_+0 95 rsr.scompare1 \at1 // conditional store option 96 s32i \at1, \ptr, .Lxchal_ofs_+4 97 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 98 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 99 xchal_sa_align \ptr, 0, 1012, 4, 4 100 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 101 .endif 102 .endm // xchal_ncp_store 103 104 /* 105 * Macro to load all non-coprocessor (extra) custom TIE and optional state 106 * (not including zero-overhead loop registers). 107 * Required parameters: 108 * ptr Save area pointer address register (clobbered) 109 * (register must contain a 4 byte aligned address). 110 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 111 * registers are clobbered, the remaining are unused). 112 * Optional parameters: 113 * continue If macro invoked as part of a larger load sequence, set to 1 114 * if this is not the first in the sequence. Defaults to 0. 115 * ofs Offset from start of larger sequence (from value of first ptr 116 * in sequence) at which to load. Defaults to next available space 117 * (or 0 if <continue> is 0). 118 * select Select what category(ies) of registers to load, as a bitmask 119 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 120 * alloc Select what category(ies) of registers to allocate; if any 121 * category is selected here that is not in <select>, space for 122 * the corresponding registers is skipped without doing any load. 123 */ 124 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 125 xchal_sa_start \continue, \ofs 126 // Optional global registers used by default by the compiler: 127 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 128 xchal_sa_align \ptr, 0, 1016, 4, 4 129 l32i \at1, \ptr, .Lxchal_ofs_+0 130 wur.threadptr \at1 // threadptr option 131 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 132 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 133 xchal_sa_align \ptr, 0, 1016, 4, 4 134 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 135 .endif 136 // Optional caller-saved registers not used by default by the compiler: 137 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 138 xchal_sa_align \ptr, 0, 1012, 4, 4 139 l32i \at1, \ptr, .Lxchal_ofs_+0 140 wsr.br \at1 // boolean option 141 l32i \at1, \ptr, .Lxchal_ofs_+4 142 wsr.scompare1 \at1 // conditional store option 143 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 144 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 145 xchal_sa_align \ptr, 0, 1012, 4, 4 146 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 147 .endif 148 .endm // xchal_ncp_load 149 150 151 #define XCHAL_NCP_NUM_ATMPS 1 152 153 /* 154 * Macro to store the state of TIE coprocessor AudioEngineLX. 155 * Required parameters: 156 * ptr Save area pointer address register (clobbered) 157 * (register must contain a 8 byte aligned address). 158 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 159 * registers are clobbered, the remaining are unused). 160 * Optional parameters are the same as for xchal_ncp_store. 161 */ 162 #define xchal_cp_AudioEngineLX_store xchal_cp1_store 163 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 164 xchal_sa_start \continue, \ofs 165 // Custom caller-saved registers not used by default by the compiler: 166 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 167 xchal_sa_align \ptr, 0, 0, 8, 8 168 ae_s64.i aed0, \ptr, .Lxchal_ofs_+40 169 ae_s64.i aed1, \ptr, .Lxchal_ofs_+48 170 ae_s64.i aed2, \ptr, .Lxchal_ofs_+56 171 addi \ptr, \ptr, 64 172 ae_s64.i aed3, \ptr, .Lxchal_ofs_+0 173 ae_s64.i aed4, \ptr, .Lxchal_ofs_+8 174 ae_s64.i aed5, \ptr, .Lxchal_ofs_+16 175 ae_s64.i aed6, \ptr, .Lxchal_ofs_+24 176 ae_s64.i aed7, \ptr, .Lxchal_ofs_+32 177 ae_s64.i aed8, \ptr, .Lxchal_ofs_+40 178 ae_s64.i aed9, \ptr, .Lxchal_ofs_+48 179 ae_s64.i aed10, \ptr, .Lxchal_ofs_+56 180 addi \ptr, \ptr, 64 181 ae_s64.i aed11, \ptr, .Lxchal_ofs_+0 182 ae_s64.i aed12, \ptr, .Lxchal_ofs_+8 183 ae_s64.i aed13, \ptr, .Lxchal_ofs_+16 184 ae_s64.i aed14, \ptr, .Lxchal_ofs_+24 185 ae_s64.i aed15, \ptr, .Lxchal_ofs_+32 186 ae_movae \at1, aep0 187 s8i \at1, \ptr, .Lxchal_ofs_+40 188 ae_movae \at1, aep1 189 s8i \at1, \ptr, .Lxchal_ofs_+41 190 ae_movae \at1, aep2 191 s8i \at1, \ptr, .Lxchal_ofs_+42 192 ae_movae \at1, aep3 193 s8i \at1, \ptr, .Lxchal_ofs_+43 194 ae_salign64.i u0, \ptr, .Lxchal_ofs_+48 195 ae_salign64.i u1, \ptr, .Lxchal_ofs_+56 196 addi \ptr, \ptr, 64 197 ae_salign64.i u2, \ptr, .Lxchal_ofs_+0 198 ae_salign64.i u3, \ptr, .Lxchal_ofs_+8 199 addi \ptr, \ptr, -192 200 ae_movvfcrfsr aed0 // ureg FCR_FSR 201 ae_s64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 202 rur.ae_ovf_sar \at1 // ureg 240 203 s32i \at1, \ptr, .Lxchal_ofs_+8 204 rur.ae_bithead \at1 // ureg 241 205 s32i \at1, \ptr, .Lxchal_ofs_+12 206 rur.ae_ts_fts_bu_bp \at1 // ureg 242 207 s32i \at1, \ptr, .Lxchal_ofs_+16 208 rur.ae_cw_sd_no \at1 // ureg 243 209 s32i \at1, \ptr, .Lxchal_ofs_+20 210 rur.ae_cbegin0 \at1 // ureg 246 211 s32i \at1, \ptr, .Lxchal_ofs_+24 212 rur.ae_cend0 \at1 // ureg 247 213 s32i \at1, \ptr, .Lxchal_ofs_+28 214 rur.ae_cbegin1 \at1 // ureg 248 215 s32i \at1, \ptr, .Lxchal_ofs_+32 216 rur.ae_cend1 \at1 // ureg 249 217 s32i \at1, \ptr, .Lxchal_ofs_+36 218 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 219 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 220 xchal_sa_align \ptr, 0, 0, 8, 8 221 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 222 .endif 223 .endm // xchal_cp1_store 224 225 /* 226 * Macro to load the state of TIE coprocessor AudioEngineLX. 227 * Required parameters: 228 * ptr Save area pointer address register (clobbered) 229 * (register must contain a 8 byte aligned address). 230 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 231 * registers are clobbered, the remaining are unused). 232 * Optional parameters are the same as for xchal_ncp_load. 233 */ 234 #define xchal_cp_AudioEngineLX_load xchal_cp1_load 235 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 236 xchal_sa_start \continue, \ofs 237 // Custom caller-saved registers not used by default by the compiler: 238 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 239 xchal_sa_align \ptr, 0, 0, 8, 8 240 ae_l64.i aed0, \ptr, .Lxchal_ofs_+0 + 0 // ureg FCR_FSR 241 ae_movfcrfsrv aed0 242 l32i \at1, \ptr, .Lxchal_ofs_+8 243 wur.ae_ovf_sar \at1 // ureg 240 244 l32i \at1, \ptr, .Lxchal_ofs_+12 245 wur.ae_bithead \at1 // ureg 241 246 l32i \at1, \ptr, .Lxchal_ofs_+16 247 wur.ae_ts_fts_bu_bp \at1 // ureg 242 248 l32i \at1, \ptr, .Lxchal_ofs_+20 249 wur.ae_cw_sd_no \at1 // ureg 243 250 l32i \at1, \ptr, .Lxchal_ofs_+24 251 wur.ae_cbegin0 \at1 // ureg 246 252 l32i \at1, \ptr, .Lxchal_ofs_+28 253 wur.ae_cend0 \at1 // ureg 247 254 l32i \at1, \ptr, .Lxchal_ofs_+32 255 wur.ae_cbegin1 \at1 // ureg 248 256 l32i \at1, \ptr, .Lxchal_ofs_+36 257 wur.ae_cend1 \at1 // ureg 249 258 ae_l64.i aed0, \ptr, .Lxchal_ofs_+40 259 ae_l64.i aed1, \ptr, .Lxchal_ofs_+48 260 ae_l64.i aed2, \ptr, .Lxchal_ofs_+56 261 addi \ptr, \ptr, 64 262 ae_l64.i aed3, \ptr, .Lxchal_ofs_+0 263 ae_l64.i aed4, \ptr, .Lxchal_ofs_+8 264 ae_l64.i aed5, \ptr, .Lxchal_ofs_+16 265 ae_l64.i aed6, \ptr, .Lxchal_ofs_+24 266 ae_l64.i aed7, \ptr, .Lxchal_ofs_+32 267 ae_l64.i aed8, \ptr, .Lxchal_ofs_+40 268 ae_l64.i aed9, \ptr, .Lxchal_ofs_+48 269 ae_l64.i aed10, \ptr, .Lxchal_ofs_+56 270 addi \ptr, \ptr, 64 271 ae_l64.i aed11, \ptr, .Lxchal_ofs_+0 272 ae_l64.i aed12, \ptr, .Lxchal_ofs_+8 273 ae_l64.i aed13, \ptr, .Lxchal_ofs_+16 274 ae_l64.i aed14, \ptr, .Lxchal_ofs_+24 275 ae_l64.i aed15, \ptr, .Lxchal_ofs_+32 276 addi \ptr, \ptr, 40 277 l8ui \at1, \ptr, .Lxchal_ofs_+0 278 ae_movea aep0, \at1 279 l8ui \at1, \ptr, .Lxchal_ofs_+1 280 ae_movea aep1, \at1 281 l8ui \at1, \ptr, .Lxchal_ofs_+2 282 ae_movea aep2, \at1 283 l8ui \at1, \ptr, .Lxchal_ofs_+3 284 ae_movea aep3, \at1 285 addi \ptr, \ptr, 8 286 ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 287 ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 288 ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 289 ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 290 .set .Lxchal_pofs_, .Lxchal_pofs_ + 176 291 .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 292 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 293 xchal_sa_align \ptr, 0, 0, 8, 8 294 .set .Lxchal_ofs_, .Lxchal_ofs_ + 208 295 .endif 296 .endm // xchal_cp1_load 297 298 #define XCHAL_CP1_NUM_ATMPS 1 299 #define XCHAL_SA_NUM_ATMPS 1 300 301 /* Empty macros for unconfigured coprocessors: */ 302 .macro xchal_cp0_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 303 .macro xchal_cp0_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 304 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 305 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 306 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 307 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 308 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 309 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 310 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 311 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 312 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 313 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 314 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 315 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 316 317 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 318 319
