1 /* 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file contains assembly-language definitions (assembly 8 macros, etc.) for this specific Xtensa processor's TIE extensions 9 and options. It is customized to this Xtensa processor configuration. 10 11 Copyright (c) 1999-2010 Tensilica Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #ifndef _XTENSA_CORE_TIE_ASM_H 33 #define _XTENSA_CORE_TIE_ASM_H 34 35 /* Selection parameter values for save-area save/restore macros: */ 36 /* Option vs. TIE: */ 37 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 38 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 39 /* Whether used automatically by compiler: */ 40 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 41 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 42 /* ABI handling across function calls: */ 43 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 44 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 45 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 46 /* Misc */ 47 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 48 49 50 51 /* Macro to save all non-coprocessor (extra) custom TIE and optional state 52 * (not including zero-overhead loop registers). 53 * Save area ptr (clobbered): ptr (4 byte aligned) 54 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 55 */ 56 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 57 xchal_sa_start \continue, \ofs 58 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 59 xchal_sa_align \ptr, 0, 1024-8, 4, 4 60 rsr \at1, ACCLO // MAC16 accumulator 61 rsr \at2, ACCHI 62 s32i \at1, \ptr, .Lxchal_ofs_ + 0 63 s32i \at2, \ptr, .Lxchal_ofs_ + 4 64 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 65 .endif 66 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 67 xchal_sa_align \ptr, 0, 1024-16, 4, 4 68 rsr \at1, M0 // MAC16 registers 69 rsr \at2, M1 70 s32i \at1, \ptr, .Lxchal_ofs_ + 0 71 s32i \at2, \ptr, .Lxchal_ofs_ + 4 72 rsr \at1, M2 73 rsr \at2, M3 74 s32i \at1, \ptr, .Lxchal_ofs_ + 8 75 s32i \at2, \ptr, .Lxchal_ofs_ + 12 76 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 77 .endif 78 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 79 xchal_sa_align \ptr, 0, 1024-4, 4, 4 80 rsr \at1, SCOMPARE1 // conditional store option 81 s32i \at1, \ptr, .Lxchal_ofs_ + 0 82 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 83 .endif 84 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 85 xchal_sa_align \ptr, 0, 1024-4, 4, 4 86 rur \at1, THREADPTR // threadptr option 87 s32i \at1, \ptr, .Lxchal_ofs_ + 0 88 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 89 .endif 90 .endm // xchal_ncp_store 91 92 /* Macro to save all non-coprocessor (extra) custom TIE and optional state 93 * (not including zero-overhead loop registers). 94 * Save area ptr (clobbered): ptr (4 byte aligned) 95 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 96 */ 97 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 98 xchal_sa_start \continue, \ofs 99 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~\select 100 xchal_sa_align \ptr, 0, 1024-8, 4, 4 101 l32i \at1, \ptr, .Lxchal_ofs_ + 0 102 l32i \at2, \ptr, .Lxchal_ofs_ + 4 103 wsr \at1, ACCLO // MAC16 accumulator 104 wsr \at2, ACCHI 105 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 106 .endif 107 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 108 xchal_sa_align \ptr, 0, 1024-16, 4, 4 109 l32i \at1, \ptr, .Lxchal_ofs_ + 0 110 l32i \at2, \ptr, .Lxchal_ofs_ + 4 111 wsr \at1, M0 // MAC16 registers 112 wsr \at2, M1 113 l32i \at1, \ptr, .Lxchal_ofs_ + 8 114 l32i \at2, \ptr, .Lxchal_ofs_ + 12 115 wsr \at1, M2 116 wsr \at2, M3 117 .set .Lxchal_ofs_, .Lxchal_ofs_ + 16 118 .endif 119 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select 120 xchal_sa_align \ptr, 0, 1024-4, 4, 4 121 l32i \at1, \ptr, .Lxchal_ofs_ + 0 122 wsr \at1, SCOMPARE1 // conditional store option 123 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 124 .endif 125 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 126 xchal_sa_align \ptr, 0, 1024-4, 4, 4 127 l32i \at1, \ptr, .Lxchal_ofs_ + 0 128 wur \at1, THREADPTR // threadptr option 129 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 130 .endif 131 .endm // xchal_ncp_load 132 133 134 135 #define XCHAL_NCP_NUM_ATMPS 2 136 137 138 #define XCHAL_SA_NUM_ATMPS 2 139 140 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 141 142
