1 /* 2 * xtensa/config/core-isa.h -- HAL definitions that are dependent on Xtensa 3 * processor CORE configuration 4 * 5 * See <xtensa/config/core.h>, which includes this file, for more details. 6 */ 7 8 /* Xtensa processor core configuration information. 9 10 Customer ID=12445; Build=0x700c0; Copyright (c) 1999-2017 Tensilica Inc. 11 12 Permission is hereby granted, free of charge, to any person obtaining 13 a copy of this software and associated documentation files (the 14 "Software"), to deal in the Software without restriction, including 15 without limitation the rights to use, copy, modify, merge, publish, 16 distribute, sublicense, and/or sell copies of the Software, and to 17 permit persons to whom the Software is furnished to do so, subject to 18 the following conditions: 19 20 The above copyright notice and this permission notice shall be included 21 in all copies or substantial portions of the Software. 22 23 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 26 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 27 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 28 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 29 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 30 31 #if !defined __XCC__ 32 33 #ifndef _XTENSA_CORE_CONFIGURATION_H 34 #define _XTENSA_CORE_CONFIGURATION_H 35 36 37 /**************************************************************************** 38 Parameters Useful for Any Code, USER or PRIVILEGED 39 ****************************************************************************/ 40 41 /* 42 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is 43 * configured, and a value of 0 otherwise. These macros are always defined. 44 */ 45 46 47 /*---------------------------------------------------------------------- 48 ISA 49 ----------------------------------------------------------------------*/ 50 51 #define XCHAL_HAVE_BE 0 /* big-endian byte ordering */ 52 #define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */ 53 #define XCHAL_NUM_AREGS 32 /* num of physical addr regs */ 54 #define XCHAL_NUM_AREGS_LOG2 5 /* log2(XCHAL_NUM_AREGS) */ 55 #define XCHAL_MAX_INSTRUCTION_SIZE 11 /* max instr bytes (3..8) */ 56 #define XCHAL_HAVE_DEBUG 1 /* debug option */ 57 #define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */ 58 #define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */ 59 #define XCHAL_LOOP_BUFFER_SIZE 0 /* zero-ov. loop instr buffer size */ 60 #define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */ 61 #define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */ 62 #define XCHAL_HAVE_SEXT 1 /* SEXT instruction */ 63 #define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */ 64 #define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */ 65 #define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */ 66 #define XCHAL_HAVE_MUL32 1 /* MULL instruction */ 67 #define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */ 68 #define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */ 69 #define XCHAL_HAVE_L32R 1 /* L32R instruction */ 70 #define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */ 71 #define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */ 72 #define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */ 73 #define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */ 74 #define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */ 75 #define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */ 76 #define XCHAL_HAVE_ABS 1 /* ABS instruction */ 77 /*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */ 78 /*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */ 79 #define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */ 80 #define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */ 81 #define XCHAL_HAVE_SPECULATION 0 /* speculation */ 82 #define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */ 83 #define XCHAL_NUM_CONTEXTS 1 /* */ 84 #define XCHAL_NUM_MISC_REGS 2 /* num of scratch regs (0..4) */ 85 #define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */ 86 #define XCHAL_HAVE_PRID 1 /* processor ID register */ 87 #define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */ 88 #define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */ 89 #define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */ 90 #define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */ 91 #define XCHAL_HAVE_PSO 0 /* Power Shut-Off */ 92 #define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */ 93 #define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */ 94 #define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */ 95 #define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */ 96 #define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */ 97 #define XCHAL_CP_MAXCFG 2 /* max allowed cp id plus one */ 98 #define XCHAL_HAVE_MAC16 0 /* MAC16 package */ 99 100 #define XCHAL_HAVE_FUSION 0 /* Fusion*/ 101 #define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */ 102 #define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */ 103 #define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */ 104 #define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */ 105 #define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */ 106 #define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */ 107 #define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */ 108 #define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */ 109 #define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */ 110 #define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */ 111 #define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */ 112 #define XCHAL_HAVE_HIFI4 1 /* HiFi4 Audio Engine pkg */ 113 #define XCHAL_HAVE_HIFI4_VFPU 1 /* HiFi4 Audio Engine VFPU option */ 114 #define XCHAL_HAVE_HIFI3 1 /* HiFi3 Audio Engine pkg */ 115 #define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */ 116 #define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */ 117 #define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */ 118 #define XCHAL_HAVE_HIFI_MINI 0 119 120 121 #define XCHAL_HAVE_VECTORFPU2005 1 /* vector or user floating-point pkg */ 122 #define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */ 123 #define XCHAL_HAVE_USER_SPFPU 1 /* user DP floating-point pkg */ 124 #define XCHAL_HAVE_FP 1 /* single prec floating point */ 125 #define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */ 126 #define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */ 127 #define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */ 128 #define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */ 129 #define XCHAL_HAVE_DFP 0 /* double precision FP pkg */ 130 #define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */ 131 #define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/ 132 #define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */ 133 #define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/ 134 #define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */ 135 #define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */ 136 137 #define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 /* DFPU Coprocessor, single precision only */ 138 #define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */ 139 #define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */ 140 #define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */ 141 #define XCHAL_HAVE_PDX4 0 /* PDX4 */ 142 #define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */ 143 #define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 & Dual LoadStore Flix */ 144 #define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */ 145 #define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 & vector recip sqrt */ 146 #define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 & vector divide */ 147 #define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 & despread */ 148 #define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */ 149 #define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */ 150 #define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 & transpose32x32 */ 151 #define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */ 152 #define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 & viterbi */ 153 #define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */ 154 #define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */ 155 #define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */ 156 #define XCHAL_HAVE_GRIVPEP 0 /* GRIVPEP is General Release of IVPEP */ 157 #define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */ 158 159 160 /*---------------------------------------------------------------------- 161 MISC 162 ----------------------------------------------------------------------*/ 163 164 #define XCHAL_NUM_LOADSTORE_UNITS 2 /* load/store units */ 165 #define XCHAL_NUM_WRITEBUFFER_ENTRIES 16 /* size of write buffer */ 166 #define XCHAL_INST_FETCH_WIDTH 16 /* instr-fetch width in bytes */ 167 #define XCHAL_DATA_WIDTH 16 /* data width in bytes */ 168 #define XCHAL_DATA_PIPE_DELAY 2 /* d-side pipeline delay 169 (1 = 5-stage, 2 = 7-stage) */ 170 #define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */ 171 #define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */ 172 /* In T1050, applies to selected core load and store instructions (see ISA): */ 173 #define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */ 174 #define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/ 175 #define XCHAL_UNALIGNED_LOAD_HW 0 /* unaligned loads work in hw */ 176 #define XCHAL_UNALIGNED_STORE_HW 0 /* unaligned stores work in hw*/ 177 178 #define XCHAL_SW_VERSION 1100004 /* sw version of this header */ 179 180 #define XCHAL_CORE_ID "hifi4_nxp_v3_3_1_2_dev" /* alphanum core name 181 (CoreID) set in the Xtensa 182 Processor Generator */ 183 184 #define XCHAL_BUILD_UNIQUE_ID 0x000700C0 /* 22-bit sw build ID */ 185 186 /* 187 * These definitions describe the hardware targeted by this software. 188 */ 189 #define XCHAL_HW_CONFIGID0 0xC2B3FBFE /* ConfigID hi 32 bits*/ 190 #define XCHAL_HW_CONFIGID1 0x1D0700C0 /* ConfigID lo 32 bits*/ 191 #define XCHAL_HW_VERSION_NAME "LX6.0.4" /* full version name */ 192 #define XCHAL_HW_VERSION_MAJOR 2600 /* major ver# of targeted hw */ 193 #define XCHAL_HW_VERSION_MINOR 4 /* minor ver# of targeted hw */ 194 #define XCHAL_HW_VERSION 260004 /* major*100+minor */ 195 #define XCHAL_HW_REL_LX6 1 196 #define XCHAL_HW_REL_LX6_0 1 197 #define XCHAL_HW_REL_LX6_0_4 1 198 #define XCHAL_HW_CONFIGID_RELIABLE 1 199 /* If software targets a *range* of hardware versions, these are the bounds: */ 200 #define XCHAL_HW_MIN_VERSION_MAJOR 2600 /* major v of earliest tgt hw */ 201 #define XCHAL_HW_MIN_VERSION_MINOR 4 /* minor v of earliest tgt hw */ 202 #define XCHAL_HW_MIN_VERSION 260004 /* earliest targeted hw */ 203 #define XCHAL_HW_MAX_VERSION_MAJOR 2600 /* major v of latest tgt hw */ 204 #define XCHAL_HW_MAX_VERSION_MINOR 4 /* minor v of latest tgt hw */ 205 #define XCHAL_HW_MAX_VERSION 260004 /* latest targeted hw */ 206 207 208 /*---------------------------------------------------------------------- 209 CACHE 210 ----------------------------------------------------------------------*/ 211 212 #define XCHAL_ICACHE_LINESIZE 128 /* I-cache line size in bytes */ 213 #define XCHAL_DCACHE_LINESIZE 128 /* D-cache line size in bytes */ 214 #define XCHAL_ICACHE_LINEWIDTH 7 /* log2(I line size in bytes) */ 215 #define XCHAL_DCACHE_LINEWIDTH 7 /* log2(D line size in bytes) */ 216 217 #define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */ 218 #define XCHAL_DCACHE_SIZE 49152 /* D-cache size in bytes or 0 */ 219 220 #define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */ 221 #define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */ 222 223 #define XCHAL_HAVE_PREFETCH 1 /* PREFCTL register */ 224 #define XCHAL_HAVE_PREFETCH_L1 1 /* prefetch to L1 dcache */ 225 #define XCHAL_PREFETCH_CASTOUT_LINES 1 /* dcache pref. castout bufsz */ 226 #define XCHAL_PREFETCH_ENTRIES 16 /* cache prefetch entries */ 227 #define XCHAL_PREFETCH_BLOCK_ENTRIES 8 /* prefetch block streams */ 228 #define XCHAL_HAVE_CACHE_BLOCKOPS 1 /* block prefetch for caches */ 229 #define XCHAL_HAVE_ICACHE_TEST 1 /* Icache test instructions */ 230 #define XCHAL_HAVE_DCACHE_TEST 1 /* Dcache test instructions */ 231 #define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */ 232 #define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */ 233 234 235 236 237 /**************************************************************************** 238 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code 239 ****************************************************************************/ 240 241 242 #ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY 243 244 /*---------------------------------------------------------------------- 245 CACHE 246 ----------------------------------------------------------------------*/ 247 248 #define XCHAL_HAVE_PIF 1 /* any outbound PIF present */ 249 #define XCHAL_HAVE_AXI 1 /* AXI bus */ 250 251 #define XCHAL_HAVE_PIF_WR_RESP 1 /* pif write response */ 252 #define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */ 253 254 /* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */ 255 256 /* Number of cache sets in log2(lines per way): */ 257 #define XCHAL_ICACHE_SETWIDTH 7 258 #define XCHAL_DCACHE_SETWIDTH 7 259 260 /* Cache set associativity (number of ways): */ 261 #define XCHAL_ICACHE_WAYS 2 262 #define XCHAL_DCACHE_WAYS 3 263 264 /* Cache features: */ 265 #define XCHAL_ICACHE_LINE_LOCKABLE 1 266 #define XCHAL_DCACHE_LINE_LOCKABLE 1 267 #define XCHAL_ICACHE_ECC_PARITY 0 268 #define XCHAL_DCACHE_ECC_PARITY 0 269 270 /* Cache access size in bytes (affects operation of SICW instruction): */ 271 #define XCHAL_ICACHE_ACCESS_SIZE 16 272 #define XCHAL_DCACHE_ACCESS_SIZE 16 273 274 #define XCHAL_DCACHE_BANKS 2 /* number of banks */ 275 276 /* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */ 277 #define XCHAL_CA_BITS 4 278 279 280 /*---------------------------------------------------------------------- 281 INTERNAL I/D RAM/ROMs and XLMI 282 ----------------------------------------------------------------------*/ 283 284 #define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */ 285 #define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */ 286 #define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */ 287 #define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */ 288 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/ 289 #define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */ 290 291 /* Instruction RAM 0: */ 292 #define XCHAL_INSTRAM0_VADDR 0x596F8000 /* virtual address */ 293 #define XCHAL_INSTRAM0_PADDR 0x596F8000 /* physical address */ 294 #define XCHAL_INSTRAM0_SIZE 2048 /* size in bytes */ 295 #define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 296 297 /* Data RAM 0: */ 298 #define XCHAL_DATARAM0_VADDR 0x596E8000 /* virtual address */ 299 #define XCHAL_DATARAM0_PADDR 0x596E8000 /* physical address */ 300 #define XCHAL_DATARAM0_SIZE 32768 /* size in bytes */ 301 #define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */ 302 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ 303 304 /* Data RAM 1: */ 305 #define XCHAL_DATARAM1_VADDR 0x596F0000 /* virtual address */ 306 #define XCHAL_DATARAM1_PADDR 0x596F0000 /* physical address */ 307 #define XCHAL_DATARAM1_SIZE 32768 /* size in bytes */ 308 #define XCHAL_DATARAM1_ECC_PARITY 0 /* ECC/parity type, 0=none */ 309 #define XCHAL_DATARAM1_BANKS 1 /* number of banks */ 310 311 #define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM*/ 312 313 314 /*---------------------------------------------------------------------- 315 INTERRUPTS and TIMERS 316 ----------------------------------------------------------------------*/ 317 318 #define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */ 319 #define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */ 320 #define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */ 321 #define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */ 322 #define XCHAL_NUM_TIMERS 2 /* number of CCOMPAREn regs */ 323 #define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */ 324 #define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */ 325 #define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */ 326 #define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels 327 (not including level zero) */ 328 #define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */ 329 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */ 330 331 /* Masks of interrupts at each interrupt level: */ 332 #define XCHAL_INTLEVEL1_MASK 0x00000100 333 #define XCHAL_INTLEVEL2_MASK 0x7FFFFEF4 334 #define XCHAL_INTLEVEL3_MASK 0x8000000A 335 #define XCHAL_INTLEVEL4_MASK 0x00000000 336 #define XCHAL_INTLEVEL5_MASK 0x00000001 337 #define XCHAL_INTLEVEL6_MASK 0x00000000 338 #define XCHAL_INTLEVEL7_MASK 0x00000000 339 340 /* Masks of interrupts at each range 1..n of interrupt levels: */ 341 #define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x00000100 342 #define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x7FFFFFF4 343 #define XCHAL_INTLEVEL3_ANDBELOW_MASK 0xFFFFFFFE 344 #define XCHAL_INTLEVEL4_ANDBELOW_MASK 0xFFFFFFFE 345 #define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFFFFF 346 #define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFFFFF 347 #define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF 348 349 /* Level of each interrupt: */ 350 #define XCHAL_INT0_LEVEL 5 351 #define XCHAL_INT1_LEVEL 3 352 #define XCHAL_INT2_LEVEL 2 353 #define XCHAL_INT3_LEVEL 3 354 #define XCHAL_INT4_LEVEL 2 355 #define XCHAL_INT5_LEVEL 2 356 #define XCHAL_INT6_LEVEL 2 357 #define XCHAL_INT7_LEVEL 2 358 #define XCHAL_INT8_LEVEL 1 359 #define XCHAL_INT9_LEVEL 2 360 #define XCHAL_INT10_LEVEL 2 361 #define XCHAL_INT11_LEVEL 2 362 #define XCHAL_INT12_LEVEL 2 363 #define XCHAL_INT13_LEVEL 2 364 #define XCHAL_INT14_LEVEL 2 365 #define XCHAL_INT15_LEVEL 2 366 #define XCHAL_INT16_LEVEL 2 367 #define XCHAL_INT17_LEVEL 2 368 #define XCHAL_INT18_LEVEL 2 369 #define XCHAL_INT19_LEVEL 2 370 #define XCHAL_INT20_LEVEL 2 371 #define XCHAL_INT21_LEVEL 2 372 #define XCHAL_INT22_LEVEL 2 373 #define XCHAL_INT23_LEVEL 2 374 #define XCHAL_INT24_LEVEL 2 375 #define XCHAL_INT25_LEVEL 2 376 #define XCHAL_INT26_LEVEL 2 377 #define XCHAL_INT27_LEVEL 2 378 #define XCHAL_INT28_LEVEL 2 379 #define XCHAL_INT29_LEVEL 2 380 #define XCHAL_INT30_LEVEL 2 381 #define XCHAL_INT31_LEVEL 3 382 #define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */ 383 #define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */ 384 #define XCHAL_NMILEVEL 5 /* NMI "level" (for use with 385 EXCSAVE/EPS/EPC_n, RFI n) */ 386 387 /* Type of each interrupt: */ 388 #define XCHAL_INT0_TYPE XTHAL_INTTYPE_NMI 389 #define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_EDGE 390 #define XCHAL_INT2_TYPE XTHAL_INTTYPE_TIMER 391 #define XCHAL_INT3_TYPE XTHAL_INTTYPE_TIMER 392 #define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_EDGE 393 #define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_EDGE 394 #define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_EDGE 395 #define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 396 #define XCHAL_INT8_TYPE XTHAL_INTTYPE_SOFTWARE 397 #define XCHAL_INT9_TYPE XTHAL_INTTYPE_SOFTWARE 398 #define XCHAL_INT10_TYPE XTHAL_INTTYPE_WRITE_ERROR 399 #define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 400 #define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 401 #define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 402 #define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 403 #define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 404 #define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 405 #define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 406 #define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 407 #define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 408 #define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 409 #define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 410 #define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 411 #define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 412 #define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 413 #define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 414 #define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 415 #define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 416 #define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 417 #define XCHAL_INT29_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 418 #define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_LEVEL 419 #define XCHAL_INT31_TYPE XTHAL_INTTYPE_PROFILING 420 421 /* Masks of interrupts for each type of interrupt: */ 422 #define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000 423 #define XCHAL_INTTYPE_MASK_SOFTWARE 0x00000300 424 #define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000072 425 #define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x7FFFF880 426 #define XCHAL_INTTYPE_MASK_TIMER 0x0000000C 427 #define XCHAL_INTTYPE_MASK_NMI 0x00000001 428 #define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000400 429 #define XCHAL_INTTYPE_MASK_PROFILING 0x80000000 430 431 #define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000 432 #define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000 433 #define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000 434 435 /* Interrupt numbers assigned to specific interrupt sources: */ 436 #define XCHAL_TIMER0_INTERRUPT 2 /* CCOMPARE0 */ 437 #define XCHAL_TIMER1_INTERRUPT 3 /* CCOMPARE1 */ 438 #define XCHAL_TIMER2_INTERRUPT XTHAL_TIMER_UNCONFIGURED 439 #define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED 440 #define XCHAL_NMI_INTERRUPT 0 /* non-maskable interrupt */ 441 #define XCHAL_WRITE_ERROR_INTERRUPT 10 /* write-error interrupt */ 442 #define XCHAL_PROFILING_INTERRUPT 31 /* profiling interrupt */ 443 444 /* Interrupt numbers for levels at which only one interrupt is configured: */ 445 #define XCHAL_INTLEVEL1_NUM 8 446 #define XCHAL_INTLEVEL5_NUM 0 447 /* (There are many interrupts each at level(s) 2, 3.) */ 448 449 450 /* 451 * External interrupt mapping. 452 * These macros describe how Xtensa processor interrupt numbers 453 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers) 454 * map to external BInterrupt<n> pins, for those interrupts 455 * configured as external (level-triggered, edge-triggered, or NMI). 456 * See the Xtensa processor databook for more details. 457 */ 458 459 /* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */ 460 #define XCHAL_EXTINT0_NUM 0 /* (intlevel 5) */ 461 #define XCHAL_EXTINT1_NUM 1 /* (intlevel 3) */ 462 #define XCHAL_EXTINT2_NUM 4 /* (intlevel 2) */ 463 #define XCHAL_EXTINT3_NUM 5 /* (intlevel 2) */ 464 #define XCHAL_EXTINT4_NUM 6 /* (intlevel 2) */ 465 #define XCHAL_EXTINT5_NUM 7 /* (intlevel 2) */ 466 #define XCHAL_EXTINT6_NUM 11 /* (intlevel 2) */ 467 #define XCHAL_EXTINT7_NUM 12 /* (intlevel 2) */ 468 #define XCHAL_EXTINT8_NUM 13 /* (intlevel 2) */ 469 #define XCHAL_EXTINT9_NUM 14 /* (intlevel 2) */ 470 #define XCHAL_EXTINT10_NUM 15 /* (intlevel 2) */ 471 #define XCHAL_EXTINT11_NUM 16 /* (intlevel 2) */ 472 #define XCHAL_EXTINT12_NUM 17 /* (intlevel 2) */ 473 #define XCHAL_EXTINT13_NUM 18 /* (intlevel 2) */ 474 #define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */ 475 #define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */ 476 #define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */ 477 #define XCHAL_EXTINT17_NUM 22 /* (intlevel 2) */ 478 #define XCHAL_EXTINT18_NUM 23 /* (intlevel 2) */ 479 #define XCHAL_EXTINT19_NUM 24 /* (intlevel 2) */ 480 #define XCHAL_EXTINT20_NUM 25 /* (intlevel 2) */ 481 #define XCHAL_EXTINT21_NUM 26 /* (intlevel 2) */ 482 #define XCHAL_EXTINT22_NUM 27 /* (intlevel 2) */ 483 #define XCHAL_EXTINT23_NUM 28 /* (intlevel 2) */ 484 #define XCHAL_EXTINT24_NUM 29 /* (intlevel 2) */ 485 #define XCHAL_EXTINT25_NUM 30 /* (intlevel 2) */ 486 /* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */ 487 #define XCHAL_INT0_EXTNUM 0 /* (intlevel 5) */ 488 #define XCHAL_INT1_EXTNUM 1 /* (intlevel 3) */ 489 #define XCHAL_INT4_EXTNUM 2 /* (intlevel 2) */ 490 #define XCHAL_INT5_EXTNUM 3 /* (intlevel 2) */ 491 #define XCHAL_INT6_EXTNUM 4 /* (intlevel 2) */ 492 #define XCHAL_INT7_EXTNUM 5 /* (intlevel 2) */ 493 #define XCHAL_INT11_EXTNUM 6 /* (intlevel 2) */ 494 #define XCHAL_INT12_EXTNUM 7 /* (intlevel 2) */ 495 #define XCHAL_INT13_EXTNUM 8 /* (intlevel 2) */ 496 #define XCHAL_INT14_EXTNUM 9 /* (intlevel 2) */ 497 #define XCHAL_INT15_EXTNUM 10 /* (intlevel 2) */ 498 #define XCHAL_INT16_EXTNUM 11 /* (intlevel 2) */ 499 #define XCHAL_INT17_EXTNUM 12 /* (intlevel 2) */ 500 #define XCHAL_INT18_EXTNUM 13 /* (intlevel 2) */ 501 #define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */ 502 #define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */ 503 #define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */ 504 #define XCHAL_INT22_EXTNUM 17 /* (intlevel 2) */ 505 #define XCHAL_INT23_EXTNUM 18 /* (intlevel 2) */ 506 #define XCHAL_INT24_EXTNUM 19 /* (intlevel 2) */ 507 #define XCHAL_INT25_EXTNUM 20 /* (intlevel 2) */ 508 #define XCHAL_INT26_EXTNUM 21 /* (intlevel 2) */ 509 #define XCHAL_INT27_EXTNUM 22 /* (intlevel 2) */ 510 #define XCHAL_INT28_EXTNUM 23 /* (intlevel 2) */ 511 #define XCHAL_INT29_EXTNUM 24 /* (intlevel 2) */ 512 #define XCHAL_INT30_EXTNUM 25 /* (intlevel 2) */ 513 514 515 /*---------------------------------------------------------------------- 516 EXCEPTIONS and VECTORS 517 ----------------------------------------------------------------------*/ 518 519 #define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture 520 number: 1 == XEA1 (old) 521 2 == XEA2 (new) 522 0 == XEAX (extern) or TX */ 523 #define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */ 524 #define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */ 525 #define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */ 526 #define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */ 527 #define XCHAL_HAVE_HALT 0 /* halt architecture option */ 528 #define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */ 529 #define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */ 530 #define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */ 531 #define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */ 532 #define XCHAL_VECBASE_RESET_VADDR 0x596F8400 /* VECBASE reset value */ 533 #define XCHAL_VECBASE_RESET_PADDR 0x596F8400 534 #define XCHAL_RESET_VECBASE_OVERLAP 0 535 536 #define XCHAL_RESET_VECTOR0_VADDR 0x596F8000 537 #define XCHAL_RESET_VECTOR0_PADDR 0x596F8000 538 #define XCHAL_RESET_VECTOR1_VADDR 0x596F8660 539 #define XCHAL_RESET_VECTOR1_PADDR 0x596F8660 540 #define XCHAL_RESET_VECTOR_VADDR 0x596F8000 541 #define XCHAL_RESET_VECTOR_PADDR 0x596F8000 542 #define XCHAL_USER_VECOFS 0x0000021C 543 #define XCHAL_USER_VECTOR_VADDR 0x596F861C 544 #define XCHAL_USER_VECTOR_PADDR 0x596F861C 545 #define XCHAL_KERNEL_VECOFS 0x000001FC 546 #define XCHAL_KERNEL_VECTOR_VADDR 0x596F85FC 547 #define XCHAL_KERNEL_VECTOR_PADDR 0x596F85FC 548 #define XCHAL_DOUBLEEXC_VECOFS 0x0000023C 549 #define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x596F863C 550 #define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x596F863C 551 #define XCHAL_WINDOW_OF4_VECOFS 0x00000000 552 #define XCHAL_WINDOW_UF4_VECOFS 0x00000040 553 #define XCHAL_WINDOW_OF8_VECOFS 0x00000080 554 #define XCHAL_WINDOW_UF8_VECOFS 0x000000C0 555 #define XCHAL_WINDOW_OF12_VECOFS 0x00000100 556 #define XCHAL_WINDOW_UF12_VECOFS 0x00000140 557 #define XCHAL_WINDOW_VECTORS_VADDR 0x596F8400 558 #define XCHAL_WINDOW_VECTORS_PADDR 0x596F8400 559 #define XCHAL_INTLEVEL2_VECOFS 0x0000017C 560 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0x596F857C 561 #define XCHAL_INTLEVEL2_VECTOR_PADDR 0x596F857C 562 #define XCHAL_INTLEVEL3_VECOFS 0x0000019C 563 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0x596F859C 564 #define XCHAL_INTLEVEL3_VECTOR_PADDR 0x596F859C 565 #define XCHAL_INTLEVEL4_VECOFS 0x000001BC 566 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0x596F85BC 567 #define XCHAL_INTLEVEL4_VECTOR_PADDR 0x596F85BC 568 #define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS 569 #define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR 570 #define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR 571 #define XCHAL_NMI_VECOFS 0x000001DC 572 #define XCHAL_NMI_VECTOR_VADDR 0x596F85DC 573 #define XCHAL_NMI_VECTOR_PADDR 0x596F85DC 574 #define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS 575 #define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR 576 #define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR 577 578 579 /*---------------------------------------------------------------------- 580 DEBUG MODULE 581 ----------------------------------------------------------------------*/ 582 583 /* Misc */ 584 #define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */ 585 #define XCHAL_HAVE_DEBUG_APB 1 /* APB to debug module */ 586 #define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */ 587 588 /* On-Chip Debug (OCD) */ 589 #define XCHAL_HAVE_OCD 1 /* OnChipDebug option */ 590 #define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */ 591 #define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */ 592 #define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */ 593 #define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */ 594 595 /* TRAX (in core) */ 596 #define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */ 597 #define XCHAL_TRAX_MEM_SIZE 512 /* TRAX memory size in bytes */ 598 #define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */ 599 #define XCHAL_TRAX_ATB_WIDTH 32 /* ATB width (bits), 0=no ATB */ 600 #define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */ 601 602 /* Perf counters */ 603 #define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */ 604 605 606 /*---------------------------------------------------------------------- 607 MMU 608 ----------------------------------------------------------------------*/ 609 610 /* See core-matmap.h header file for more details. */ 611 612 #define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */ 613 #define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */ 614 #define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */ 615 #define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */ 616 #define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */ 617 #define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */ 618 #define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */ 619 #define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table 620 [autorefill] and protection) 621 usable for an MMU-based OS */ 622 /* If none of the above last 4 are set, it's a custom TLB configuration. */ 623 624 #define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */ 625 #define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */ 626 #define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */ 627 628 #endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */ 629 630 631 #endif /* _XTENSA_CORE_CONFIGURATION_H */ 632 633 #else 634 635 #error "xcc should not use this header" 636 637 #endif /* __XCC__ */ 638
