1 /* 2 * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file describes this specific Xtensa processor's TIE extensions 8 that extend basic Xtensa core functionality. It is customized to this 9 Xtensa processor configuration. 10 11 Copyright (c) 1999-2018 Cadence Design Systems Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #if !defined __XCC__ 33 34 #ifndef _XTENSA_CORE_TIE_H 35 #define _XTENSA_CORE_TIE_H 36 37 #define XCHAL_CP_NUM 2 /* number of coprocessors */ 38 #define XCHAL_CP_MAX 2 /* max CP ID + 1 (0 if none) */ 39 #define XCHAL_CP_MASK 0x03 /* bitmask of all CPs by ID */ 40 #define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */ 41 42 /* Basic parameters of each coprocessor: */ 43 #define XCHAL_CP0_NAME "FPU" 44 #define XCHAL_CP0_IDENT FPU 45 #define XCHAL_CP0_SA_SIZE 72 /* size of state save area */ 46 #define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */ 47 #define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */ 48 #define XCHAL_CP1_NAME "AudioEngineLX" 49 #define XCHAL_CP1_IDENT AudioEngineLX 50 #define XCHAL_CP1_SA_SIZE 184 /* size of state save area */ 51 #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ 52 #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ 53 54 /* Filler info for unassigned coprocessors, to simplify arrays etc: */ 55 #define XCHAL_CP2_SA_SIZE 0 56 #define XCHAL_CP2_SA_ALIGN 1 57 #define XCHAL_CP3_SA_SIZE 0 58 #define XCHAL_CP3_SA_ALIGN 1 59 #define XCHAL_CP4_SA_SIZE 0 60 #define XCHAL_CP4_SA_ALIGN 1 61 #define XCHAL_CP5_SA_SIZE 0 62 #define XCHAL_CP5_SA_ALIGN 1 63 #define XCHAL_CP6_SA_SIZE 0 64 #define XCHAL_CP6_SA_ALIGN 1 65 #define XCHAL_CP7_SA_SIZE 0 66 #define XCHAL_CP7_SA_ALIGN 1 67 68 /* Save area for non-coprocessor optional and custom (TIE) state: */ 69 #define XCHAL_NCP_SA_SIZE 12 70 #define XCHAL_NCP_SA_ALIGN 4 71 72 /* Total save area for optional and custom state (NCP + CPn): */ 73 #define XCHAL_TOTAL_SA_SIZE 272 /* with 16-byte align padding */ 74 #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ 75 76 /* 77 * Detailed contents of save areas. 78 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) 79 * before expanding the XCHAL_xxx_SA_LIST() macros. 80 * 81 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, 82 * dbnum,base,regnum,bitsz,gapsz,reset,x...) 83 * 84 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand 85 * ccused = set if used by compiler without special options or code 86 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) 87 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) 88 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) 89 * name = lowercase reg name (no quotes) 90 * galign = group byte alignment (power of 2) (galign >= align) 91 * align = register byte alignment (power of 2) 92 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) 93 * (not including any pad bytes required to galign this or next reg) 94 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) 95 * base = reg shortname w/o index (or sr=special, ur=TIE user reg) 96 * regnum = reg index in regfile, or special/TIE-user reg number 97 * bitsz = number of significant bits (regfile width, or ur/sr mask bits) 98 * gapsz = intervening bits, if bitsz bits not stored contiguously 99 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) 100 * reset = register reset value (or 0 if undefined at reset) 101 * x = reserved for future use (0 until then) 102 * 103 * To filter out certain registers, e.g. to expand only the non-global 104 * registers used by the compiler, you can do something like this: 105 * 106 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) 107 * #define SELCC0(p...) 108 * #define SELCC1(abikind,p...) SELAK##abikind(p) 109 * #define SELAK0(p...) REG(p) 110 * #define SELAK1(p...) REG(p) 111 * #define SELAK2(p...) 112 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ 113 * ...what you want to expand... 114 */ 115 116 #define XCHAL_NCP_SA_NUM 3 117 #define XCHAL_NCP_SA_LIST(s) \ 118 XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ 119 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ 120 XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) 121 122 #define XCHAL_CP0_SA_NUM 18 123 #define XCHAL_CP0_SA_LIST(s) \ 124 XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \ 125 XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \ 126 XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \ 127 XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \ 128 XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \ 129 XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \ 130 XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \ 131 XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \ 132 XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \ 133 XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \ 134 XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \ 135 XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \ 136 XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \ 137 XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \ 138 XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \ 139 XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \ 140 XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \ 141 XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0) 142 143 #define XCHAL_CP1_SA_NUM 26 144 #define XCHAL_CP1_SA_LIST(s) \ 145 XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 8,0,0,0) \ 146 XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ 147 XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ 148 XCHAL_SA_REG(s,0,0,1,0, ae_cw_sd_no, 4, 4, 4,0x03F3, ur,243, 29,0,0,0) \ 149 XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \ 150 XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \ 151 XCHAL_SA_REG(s,0,0,2,0, aed0, 8, 8, 8,0x1000, aed,0 , 64,0,0,0) \ 152 XCHAL_SA_REG(s,0,0,2,0, aed1, 8, 8, 8,0x1001, aed,1 , 64,0,0,0) \ 153 XCHAL_SA_REG(s,0,0,2,0, aed2, 8, 8, 8,0x1002, aed,2 , 64,0,0,0) \ 154 XCHAL_SA_REG(s,0,0,2,0, aed3, 8, 8, 8,0x1003, aed,3 , 64,0,0,0) \ 155 XCHAL_SA_REG(s,0,0,2,0, aed4, 8, 8, 8,0x1004, aed,4 , 64,0,0,0) \ 156 XCHAL_SA_REG(s,0,0,2,0, aed5, 8, 8, 8,0x1005, aed,5 , 64,0,0,0) \ 157 XCHAL_SA_REG(s,0,0,2,0, aed6, 8, 8, 8,0x1006, aed,6 , 64,0,0,0) \ 158 XCHAL_SA_REG(s,0,0,2,0, aed7, 8, 8, 8,0x1007, aed,7 , 64,0,0,0) \ 159 XCHAL_SA_REG(s,0,0,2,0, aed8, 8, 8, 8,0x1008, aed,8 , 64,0,0,0) \ 160 XCHAL_SA_REG(s,0,0,2,0, aed9, 8, 8, 8,0x1009, aed,9 , 64,0,0,0) \ 161 XCHAL_SA_REG(s,0,0,2,0, aed10, 8, 8, 8,0x100A, aed,10 , 64,0,0,0) \ 162 XCHAL_SA_REG(s,0,0,2,0, aed11, 8, 8, 8,0x100B, aed,11 , 64,0,0,0) \ 163 XCHAL_SA_REG(s,0,0,2,0, aed12, 8, 8, 8,0x100C, aed,12 , 64,0,0,0) \ 164 XCHAL_SA_REG(s,0,0,2,0, aed13, 8, 8, 8,0x100D, aed,13 , 64,0,0,0) \ 165 XCHAL_SA_REG(s,0,0,2,0, aed14, 8, 8, 8,0x100E, aed,14 , 64,0,0,0) \ 166 XCHAL_SA_REG(s,0,0,2,0, aed15, 8, 8, 8,0x100F, aed,15 , 64,0,0,0) \ 167 XCHAL_SA_REG(s,0,0,2,0, u0, 8, 8, 8,0x1010, u,0 , 64,0,0,0) \ 168 XCHAL_SA_REG(s,0,0,2,0, u1, 8, 8, 8,0x1011, u,1 , 64,0,0,0) \ 169 XCHAL_SA_REG(s,0,0,2,0, u2, 8, 8, 8,0x1012, u,2 , 64,0,0,0) \ 170 XCHAL_SA_REG(s,0,0,2,0, u3, 8, 8, 8,0x1013, u,3 , 64,0,0,0) 171 172 #define XCHAL_CP2_SA_NUM 0 173 #define XCHAL_CP2_SA_LIST(s) /* empty */ 174 175 #define XCHAL_CP3_SA_NUM 0 176 #define XCHAL_CP3_SA_LIST(s) /* empty */ 177 178 #define XCHAL_CP4_SA_NUM 0 179 #define XCHAL_CP4_SA_LIST(s) /* empty */ 180 181 #define XCHAL_CP5_SA_NUM 0 182 #define XCHAL_CP5_SA_LIST(s) /* empty */ 183 184 #define XCHAL_CP6_SA_NUM 0 185 #define XCHAL_CP6_SA_LIST(s) /* empty */ 186 187 #define XCHAL_CP7_SA_NUM 0 188 #define XCHAL_CP7_SA_LIST(s) /* empty */ 189 190 /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ 191 #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8 192 /* Byte length of instruction from its first byte, per FLIX. */ 193 #define XCHAL_BYTE0_FORMAT_LENGTHS \ 194 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 195 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 196 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 197 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 198 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 199 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 200 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8,\ 201 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8 202 203 #endif /*_XTENSA_CORE_TIE_H*/ 204 205 #else 206 207 #error "xcc should not use this header" 208 209 #endif /* __XCC__ */ 210
