1 /* 2 * Copyright (c) 2001 Tensilica Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sublicense, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included 13 * in all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 18 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 19 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 20 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 21 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 24 /* simboard.h - Xtensa ISS "Board" specific definitions */ 25 26 #ifndef _INC_SIMBOARD_H_ 27 #define _INC_SIMBOARD_H_ 28 29 #include <xtensa/config/core.h> 30 #include <xtensa/config/system.h> 31 32 33 /* 34 * Device addresses. 35 */ 36 37 /* System ROM: */ 38 #define XTBOARD_ROM_SIZE XSHAL_ROM_SIZE 39 #ifdef XSHAL_ROM_VADDR 40 #define XTBOARD_ROM_VADDR XSHAL_ROM_VADDR 41 #endif 42 #ifdef XSHAL_ROM_PADDR 43 #define XTBOARD_ROM_PADDR XSHAL_ROM_PADDR 44 #endif 45 46 /* System RAM: */ 47 #define XTBOARD_RAM_SIZE XSHAL_RAM_SIZE 48 #ifdef XSHAL_RAM_VADDR 49 #define XTBOARD_RAM_VADDR XSHAL_RAM_VADDR 50 #endif 51 #ifdef XSHAL_RAM_PADDR 52 #define XTBOARD_RAM_PADDR XSHAL_RAM_PADDR 53 #endif 54 55 56 /* 57 * Things that depend on device addresses. 58 */ 59 60 #define XTBOARD_CACHEATTR_WRITEBACK XSHAL_ISS_CACHEATTR_WRITEBACK 61 #define XTBOARD_CACHEATTR_WRITEALLOC XSHAL_ISS_CACHEATTR_WRITEALLOC 62 #define XTBOARD_CACHEATTR_WRITETHRU XSHAL_ISS_CACHEATTR_WRITETHRU 63 #define XTBOARD_CACHEATTR_BYPASS XSHAL_ISS_CACHEATTR_BYPASS 64 #define XTBOARD_CACHEATTR_DEFAULT XSHAL_ISS_CACHEATTR_DEFAULT 65 66 #define XTBOARD_BUSINT_PIPE_REGIONS 0 67 #define XTBOARD_BUSINT_SDRAM_REGIONS 0 68 69 70 #endif /*_INC_SIMBOARD_H_*/ 71 72
