1 /* 2 * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3 * 4 * NOTE: This header file is not meant to be included directly. 5 */ 6 7 /* This header file contains assembly-language definitions (assembly 8 macros, etc.) for this specific Xtensa processor's TIE extensions 9 and options. It is customized to this Xtensa processor configuration. 10 11 Copyright (c) 1999-2019 Cadence Design Systems Inc. 12 13 Permission is hereby granted, free of charge, to any person obtaining 14 a copy of this software and associated documentation files (the 15 "Software"), to deal in the Software without restriction, including 16 without limitation the rights to use, copy, modify, merge, publish, 17 distribute, sublicense, and/or sell copies of the Software, and to 18 permit persons to whom the Software is furnished to do so, subject to 19 the following conditions: 20 21 The above copyright notice and this permission notice shall be included 22 in all copies or substantial portions of the Software. 23 24 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31 32 #ifndef _XTENSA_CORE_TIE_ASM_H 33 #define _XTENSA_CORE_TIE_ASM_H 34 35 #include <xtensa/coreasm.h> 36 37 /* Selection parameter values for save-area save/restore macros: */ 38 /* Option vs. TIE: */ 39 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 40 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 41 #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 42 /* Whether used automatically by compiler: */ 43 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 44 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 45 #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 46 /* ABI handling across function calls: */ 47 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 48 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 49 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 50 #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 51 /* Misc */ 52 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 53 #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 54 | ((ccuse) & XTHAL_SAS_ANYCC) \ 55 | ((abi) & XTHAL_SAS_ANYABI) ) 56 57 58 /* 59 * Macro to store all non-coprocessor (extra) custom TIE and optional state 60 * (not including zero-overhead loop registers). 61 * Required parameters: 62 * ptr Save area pointer address register (clobbered) 63 * (register must contain a 4 byte aligned address). 64 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 65 * registers are clobbered, the remaining are unused). 66 * Optional parameters: 67 * continue If macro invoked as part of a larger store sequence, set to 1 68 * if this is not the first in the sequence. Defaults to 0. 69 * ofs Offset from start of larger sequence (from value of first ptr 70 * in sequence) at which to store. Defaults to next available space 71 * (or 0 if <continue> is 0). 72 * select Select what category(ies) of registers to store, as a bitmask 73 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 74 * alloc Select what category(ies) of registers to allocate; if any 75 * category is selected here that is not in <select>, space for 76 * the corresponding registers is skipped without doing any store. 77 */ 78 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 79 xchal_sa_start \continue, \ofs 80 // Optional global registers used by default by the compiler: 81 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 82 xchal_sa_align \ptr, 0, 1016, 4, 4 83 rur.threadptr \at1 // threadptr option 84 s32i \at1, \ptr, .Lxchal_ofs_+0 85 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 86 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 87 xchal_sa_align \ptr, 0, 1016, 4, 4 88 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 89 .endif 90 // Optional caller-saved registers not used by default by the compiler: 91 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 92 xchal_sa_align \ptr, 0, 1012, 4, 4 93 rsr.br \at1 // boolean option 94 s32i \at1, \ptr, .Lxchal_ofs_+0 95 rsr.scompare1 \at1 // conditional store option 96 s32i \at1, \ptr, .Lxchal_ofs_+4 97 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 98 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 99 xchal_sa_align \ptr, 0, 1012, 4, 4 100 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 101 .endif 102 .endm // xchal_ncp_store 103 104 /* 105 * Macro to load all non-coprocessor (extra) custom TIE and optional state 106 * (not including zero-overhead loop registers). 107 * Required parameters: 108 * ptr Save area pointer address register (clobbered) 109 * (register must contain a 4 byte aligned address). 110 * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 111 * registers are clobbered, the remaining are unused). 112 * Optional parameters: 113 * continue If macro invoked as part of a larger load sequence, set to 1 114 * if this is not the first in the sequence. Defaults to 0. 115 * ofs Offset from start of larger sequence (from value of first ptr 116 * in sequence) at which to load. Defaults to next available space 117 * (or 0 if <continue> is 0). 118 * select Select what category(ies) of registers to load, as a bitmask 119 * (see XTHAL_SAS_xxx constants). Defaults to all registers. 120 * alloc Select what category(ies) of registers to allocate; if any 121 * category is selected here that is not in <select>, space for 122 * the corresponding registers is skipped without doing any load. 123 */ 124 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 125 xchal_sa_start \continue, \ofs 126 // Optional global registers used by default by the compiler: 127 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select) 128 xchal_sa_align \ptr, 0, 1016, 4, 4 129 l32i \at1, \ptr, .Lxchal_ofs_+0 130 wur.threadptr \at1 // threadptr option 131 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 132 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0 133 xchal_sa_align \ptr, 0, 1016, 4, 4 134 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 135 .endif 136 // Optional caller-saved registers not used by default by the compiler: 137 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 138 xchal_sa_align \ptr, 0, 1012, 4, 4 139 l32i \at1, \ptr, .Lxchal_ofs_+0 140 wsr.br \at1 // boolean option 141 l32i \at1, \ptr, .Lxchal_ofs_+4 142 wsr.scompare1 \at1 // conditional store option 143 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 144 .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 145 xchal_sa_align \ptr, 0, 1012, 4, 4 146 .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 147 .endif 148 .endm // xchal_ncp_load 149 150 151 #define XCHAL_NCP_NUM_ATMPS 1 152 153 #if 0 154 155 /* 156 * Macro to store the state of TIE coprocessor FPU. 157 * Required parameters: 158 * ptr Save area pointer address register (clobbered) 159 * (register must contain a 4 byte aligned address). 160 * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS 161 * registers are clobbered, the remaining are unused). 162 * Optional parameters are the same as for xchal_ncp_store. 163 */ 164 #define xchal_cp_FPU_store xchal_cp0_store 165 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 166 xchal_sa_start \continue, \ofs 167 // Custom caller-saved registers not used by default by the compiler: 168 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 169 xchal_sa_align \ptr, 0, 948, 4, 4 170 rur.fcr \at1 // ureg 232 171 s32i \at1, \ptr, .Lxchal_ofs_+0 172 rur.fsr \at1 // ureg 233 173 s32i \at1, \ptr, .Lxchal_ofs_+4 174 ssi f0, \ptr, .Lxchal_ofs_+8 175 ssi f1, \ptr, .Lxchal_ofs_+12 176 ssi f2, \ptr, .Lxchal_ofs_+16 177 ssi f3, \ptr, .Lxchal_ofs_+20 178 ssi f4, \ptr, .Lxchal_ofs_+24 179 ssi f5, \ptr, .Lxchal_ofs_+28 180 ssi f6, \ptr, .Lxchal_ofs_+32 181 ssi f7, \ptr, .Lxchal_ofs_+36 182 ssi f8, \ptr, .Lxchal_ofs_+40 183 ssi f9, \ptr, .Lxchal_ofs_+44 184 ssi f10, \ptr, .Lxchal_ofs_+48 185 ssi f11, \ptr, .Lxchal_ofs_+52 186 ssi f12, \ptr, .Lxchal_ofs_+56 187 ssi f13, \ptr, .Lxchal_ofs_+60 188 ssi f14, \ptr, .Lxchal_ofs_+64 189 ssi f15, \ptr, .Lxchal_ofs_+68 190 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 191 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 192 xchal_sa_align \ptr, 0, 948, 4, 4 193 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 194 .endif 195 .endm // xchal_cp0_store 196 197 /* 198 * Macro to load the state of TIE coprocessor FPU. 199 * Required parameters: 200 * ptr Save area pointer address register (clobbered) 201 * (register must contain a 4 byte aligned address). 202 * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS 203 * registers are clobbered, the remaining are unused). 204 * Optional parameters are the same as for xchal_ncp_load. 205 */ 206 #define xchal_cp_FPU_load xchal_cp0_load 207 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 208 xchal_sa_start \continue, \ofs 209 // Custom caller-saved registers not used by default by the compiler: 210 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 211 xchal_sa_align \ptr, 0, 948, 4, 4 212 l32i \at1, \ptr, .Lxchal_ofs_+0 213 wur.fcr \at1 // ureg 232 214 l32i \at1, \ptr, .Lxchal_ofs_+4 215 wur.fsr \at1 // ureg 233 216 lsi f0, \ptr, .Lxchal_ofs_+8 217 lsi f1, \ptr, .Lxchal_ofs_+12 218 lsi f2, \ptr, .Lxchal_ofs_+16 219 lsi f3, \ptr, .Lxchal_ofs_+20 220 lsi f4, \ptr, .Lxchal_ofs_+24 221 lsi f5, \ptr, .Lxchal_ofs_+28 222 lsi f6, \ptr, .Lxchal_ofs_+32 223 lsi f7, \ptr, .Lxchal_ofs_+36 224 lsi f8, \ptr, .Lxchal_ofs_+40 225 lsi f9, \ptr, .Lxchal_ofs_+44 226 lsi f10, \ptr, .Lxchal_ofs_+48 227 lsi f11, \ptr, .Lxchal_ofs_+52 228 lsi f12, \ptr, .Lxchal_ofs_+56 229 lsi f13, \ptr, .Lxchal_ofs_+60 230 lsi f14, \ptr, .Lxchal_ofs_+64 231 lsi f15, \ptr, .Lxchal_ofs_+68 232 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 233 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 234 xchal_sa_align \ptr, 0, 948, 4, 4 235 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72 236 .endif 237 .endm // xchal_cp0_load 238 239 #define XCHAL_CP0_NUM_ATMPS 1 240 /* 241 * Macro to store the state of TIE coprocessor AudioEngineLX. 242 * Required parameters: 243 * ptr Save area pointer address register (clobbered) 244 * (register must contain a 8 byte aligned address). 245 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 246 * registers are clobbered, the remaining are unused). 247 * Optional parameters are the same as for xchal_ncp_store. 248 */ 249 #define xchal_cp_AudioEngineLX_store xchal_cp1_store 250 .macro xchal_cp1_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 251 xchal_sa_start \continue, \ofs 252 // Custom caller-saved registers not used by default by the compiler: 253 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 254 xchal_sa_align \ptr, 0, 0, 8, 8 255 rur.ae_ovf_sar \at1 // ureg 240 256 s32i \at1, \ptr, .Lxchal_ofs_+0 257 rur.ae_bithead \at1 // ureg 241 258 s32i \at1, \ptr, .Lxchal_ofs_+4 259 rur.ae_ts_fts_bu_bp \at1 // ureg 242 260 s32i \at1, \ptr, .Lxchal_ofs_+8 261 rur.ae_cw_sd_no \at1 // ureg 243 262 s32i \at1, \ptr, .Lxchal_ofs_+12 263 rur.ae_cbegin0 \at1 // ureg 246 264 s32i \at1, \ptr, .Lxchal_ofs_+16 265 rur.ae_cend0 \at1 // ureg 247 266 s32i \at1, \ptr, .Lxchal_ofs_+20 267 ae_s64.i aed0, \ptr, .Lxchal_ofs_+24 268 ae_s64.i aed1, \ptr, .Lxchal_ofs_+32 269 ae_s64.i aed2, \ptr, .Lxchal_ofs_+40 270 ae_s64.i aed3, \ptr, .Lxchal_ofs_+48 271 ae_s64.i aed4, \ptr, .Lxchal_ofs_+56 272 addi.a \ptr, \ptr, 64 273 ae_s64.i aed5, \ptr, .Lxchal_ofs_+0 274 ae_s64.i aed6, \ptr, .Lxchal_ofs_+8 275 ae_s64.i aed7, \ptr, .Lxchal_ofs_+16 276 ae_s64.i aed8, \ptr, .Lxchal_ofs_+24 277 ae_s64.i aed9, \ptr, .Lxchal_ofs_+32 278 ae_s64.i aed10, \ptr, .Lxchal_ofs_+40 279 ae_s64.i aed11, \ptr, .Lxchal_ofs_+48 280 ae_s64.i aed12, \ptr, .Lxchal_ofs_+56 281 addi.a \ptr, \ptr, 64 282 ae_s64.i aed13, \ptr, .Lxchal_ofs_+0 283 ae_s64.i aed14, \ptr, .Lxchal_ofs_+8 284 ae_s64.i aed15, \ptr, .Lxchal_ofs_+16 285 ae_salign64.i u0, \ptr, .Lxchal_ofs_+24 286 ae_salign64.i u1, \ptr, .Lxchal_ofs_+32 287 ae_salign64.i u2, \ptr, .Lxchal_ofs_+40 288 ae_salign64.i u3, \ptr, .Lxchal_ofs_+48 289 .set .Lxchal_pofs_, .Lxchal_pofs_ + 128 290 .set .Lxchal_ofs_, .Lxchal_ofs_ + 56 291 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 292 xchal_sa_align \ptr, 0, 0, 8, 8 293 .set .Lxchal_ofs_, .Lxchal_ofs_ + 184 294 .endif 295 .endm // xchal_cp1_store 296 297 /* 298 * Macro to load the state of TIE coprocessor AudioEngineLX. 299 * Required parameters: 300 * ptr Save area pointer address register (clobbered) 301 * (register must contain a 8 byte aligned address). 302 * at1..at4 Four temporary address registers (first XCHAL_CP1_NUM_ATMPS 303 * registers are clobbered, the remaining are unused). 304 * Optional parameters are the same as for xchal_ncp_load. 305 */ 306 #define xchal_cp_AudioEngineLX_load xchal_cp1_load 307 .macro xchal_cp1_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 308 xchal_sa_start \continue, \ofs 309 // Custom caller-saved registers not used by default by the compiler: 310 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 311 xchal_sa_align \ptr, 0, 0, 8, 8 312 l32i \at1, \ptr, .Lxchal_ofs_+0 313 wur.ae_ovf_sar \at1 // ureg 240 314 l32i \at1, \ptr, .Lxchal_ofs_+4 315 wur.ae_bithead \at1 // ureg 241 316 l32i \at1, \ptr, .Lxchal_ofs_+8 317 wur.ae_ts_fts_bu_bp \at1 // ureg 242 318 l32i \at1, \ptr, .Lxchal_ofs_+12 319 wur.ae_cw_sd_no \at1 // ureg 243 320 l32i \at1, \ptr, .Lxchal_ofs_+16 321 wur.ae_cbegin0 \at1 // ureg 246 322 l32i \at1, \ptr, .Lxchal_ofs_+20 323 wur.ae_cend0 \at1 // ureg 247 324 ae_l64.i aed0, \ptr, .Lxchal_ofs_+24 325 ae_l64.i aed1, \ptr, .Lxchal_ofs_+32 326 ae_l64.i aed2, \ptr, .Lxchal_ofs_+40 327 ae_l64.i aed3, \ptr, .Lxchal_ofs_+48 328 ae_l64.i aed4, \ptr, .Lxchal_ofs_+56 329 addi.a \ptr, \ptr, 64 330 ae_l64.i aed5, \ptr, .Lxchal_ofs_+0 331 ae_l64.i aed6, \ptr, .Lxchal_ofs_+8 332 ae_l64.i aed7, \ptr, .Lxchal_ofs_+16 333 ae_l64.i aed8, \ptr, .Lxchal_ofs_+24 334 ae_l64.i aed9, \ptr, .Lxchal_ofs_+32 335 ae_l64.i aed10, \ptr, .Lxchal_ofs_+40 336 ae_l64.i aed11, \ptr, .Lxchal_ofs_+48 337 ae_l64.i aed12, \ptr, .Lxchal_ofs_+56 338 addi.a \ptr, \ptr, 64 339 ae_l64.i aed13, \ptr, .Lxchal_ofs_+0 340 ae_l64.i aed14, \ptr, .Lxchal_ofs_+8 341 ae_l64.i aed15, \ptr, .Lxchal_ofs_+16 342 addi.a \ptr, \ptr, 24 343 ae_lalign64.i u0, \ptr, .Lxchal_ofs_+0 344 ae_lalign64.i u1, \ptr, .Lxchal_ofs_+8 345 ae_lalign64.i u2, \ptr, .Lxchal_ofs_+16 346 ae_lalign64.i u3, \ptr, .Lxchal_ofs_+24 347 .set .Lxchal_pofs_, .Lxchal_pofs_ + 152 348 .set .Lxchal_ofs_, .Lxchal_ofs_ + 32 349 .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 350 xchal_sa_align \ptr, 0, 0, 8, 8 351 .set .Lxchal_ofs_, .Lxchal_ofs_ + 184 352 .endif 353 .endm // xchal_cp1_load 354 355 #define XCHAL_CP1_NUM_ATMPS 1 356 #define XCHAL_SA_NUM_ATMPS 1 357 358 /* Empty macros for unconfigured coprocessors: */ 359 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 360 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 361 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 362 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 363 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 364 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 365 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 366 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 367 .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 368 .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 369 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm 370 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm 371 372 #endif /* 0 */ 373 374 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 375
