1 /* 2 * xtensa/config/system.h -- HAL definitions that are dependent on SYSTEM configuration 3 * 4 * NOTE: The location and contents of this file are highly subject to change. 5 * 6 * Source for configuration-independent binaries (which link in a 7 * configuration-specific HAL library) must NEVER include this file. 8 * The HAL itself has historically included this file in some instances, 9 * but this is not appropriate either, because the HAL is meant to be 10 * core-specific but system independent. 11 */ 12 13 /* Copyright (c) 2000-2010 Tensilica Inc. 14 15 Permission is hereby granted, free of charge, to any person obtaining 16 a copy of this software and associated documentation files (the 17 "Software"), to deal in the Software without restriction, including 18 without limitation the rights to use, copy, modify, merge, publish, 19 distribute, sublicense, and/or sell copies of the Software, and to 20 permit persons to whom the Software is furnished to do so, subject to 21 the following conditions: 22 23 The above copyright notice and this permission notice shall be included 24 in all copies or substantial portions of the Software. 25 26 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 27 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 28 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 29 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 30 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 31 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 32 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 33 34 #if !defined __XCC__ 35 36 #ifndef XTENSA_CONFIG_SYSTEM_H 37 #define XTENSA_CONFIG_SYSTEM_H 38 39 /*#include <xtensa/hal.h>*/ 40 41 42 43 /*---------------------------------------------------------------------- 44 CONFIGURED SOFTWARE OPTIONS 45 ----------------------------------------------------------------------*/ 46 47 #define XSHAL_USE_ABSOLUTE_LITERALS 0 /* (sw-only option, whether software uses absolute literals) */ 48 #define XSHAL_HAVE_TEXT_SECTION_LITERALS 1 /* Set if there is some memory that allows both code and literals. */ 49 50 #define XSHAL_ABI XTHAL_ABI_WINDOWED /* (sw-only option, selected ABI) */ 51 /* The above maps to one of the following constants: */ 52 #define XTHAL_ABI_WINDOWED 0 53 #define XTHAL_ABI_CALL0 1 54 /* Alternatives: */ 55 /*#define XSHAL_WINDOWED_ABI 1*/ /* set if windowed ABI selected */ 56 /*#define XSHAL_CALL0_ABI 0*/ /* set if call0 ABI selected */ 57 58 #define XSHAL_CLIB XTHAL_CLIB_NEWLIB /* (sw-only option, selected C library) */ 59 /* The above maps to one of the following constants: */ 60 #define XTHAL_CLIB_NEWLIB 0 61 #define XTHAL_CLIB_UCLIBC 1 62 #define XTHAL_CLIB_XCLIB 2 63 /* Alternatives: */ 64 /*#define XSHAL_NEWLIB 1*/ /* set if newlib C library selected */ 65 /*#define XSHAL_UCLIBC 0*/ /* set if uCLibC C library selected */ 66 /*#define XSHAL_XCLIB 0*/ /* set if Xtensa C library selected */ 67 68 #define XSHAL_USE_FLOATING_POINT 1 69 70 #define XSHAL_FLOATING_POINT_ABI 0 71 72 /* SW workarounds enabled for HW errata: */ 73 74 /* SW options for functional safety: */ 75 #define XSHAL_FUNC_SAFETY_ENABLED 0 76 77 /*---------------------------------------------------------------------- 78 DEVICE ADDRESSES 79 ----------------------------------------------------------------------*/ 80 81 /* 82 * Strange place to find these, but the configuration GUI 83 * allows moving these around to account for various core 84 * configurations. Specific boards (and their BSP software) 85 * will have specific meanings for these components. 86 */ 87 88 /* I/O Block areas: */ 89 #define XSHAL_IOBLOCK_CACHED_VADDR 0x70000000 90 #define XSHAL_IOBLOCK_CACHED_PADDR 0x70000000 91 #define XSHAL_IOBLOCK_CACHED_SIZE 0x0E000000 92 93 #define XSHAL_IOBLOCK_BYPASS_VADDR 0x50000000 94 #define XSHAL_IOBLOCK_BYPASS_PADDR 0x50000000 95 #define XSHAL_IOBLOCK_BYPASS_SIZE 0x0E000000 96 97 /* System ROM: */ 98 #define XSHAL_ROM_VADDR 0xBEFE0000 99 #define XSHAL_ROM_PADDR 0xBEFE0000 100 #define XSHAL_ROM_SIZE 0x00020000 101 /* Largest available area (free of vectors): */ 102 #define XSHAL_ROM_AVAIL_VADDR 0xBEFE0BC0 103 #define XSHAL_ROM_AVAIL_VSIZE 0x0001F440 104 105 /* System RAM: */ 106 #define XSHAL_RAM_VADDR 0x80000000 107 #define XSHAL_RAM_PADDR 0x80000000 108 #define XSHAL_RAM_VSIZE 0x3EFE0000 109 #define XSHAL_RAM_PSIZE 0x3EFE0000 110 #define XSHAL_RAM_SIZE XSHAL_RAM_PSIZE 111 /* Largest available area (free of vectors): */ 112 #define XSHAL_RAM_AVAIL_VADDR 0x80000000 113 #define XSHAL_RAM_AVAIL_VSIZE 0x3EFE0000 114 115 /* 116 * Shadow system RAM (same device as system RAM, at different address). 117 * (Emulation boards need this for the SONIC Ethernet driver 118 * when data caches are configured for writeback mode.) 119 * NOTE: on full MMU configs, this points to the BYPASS virtual address 120 * of system RAM, ie. is the same as XSHAL_RAM_* except that virtual 121 * addresses are viewed through the BYPASS static map rather than 122 * the CACHED static map. 123 */ 124 #define XSHAL_RAM_BYPASS_VADDR 0x20000000 125 #define XSHAL_RAM_BYPASS_PADDR 0x20000000 126 #define XSHAL_RAM_BYPASS_PSIZE 0x20000000 127 128 /* Alternate system RAM (different device than system RAM): */ 129 /*#define XSHAL_ALTRAM_[VP]ADDR ...not configured...*/ 130 /*#define XSHAL_ALTRAM_SIZE ...not configured...*/ 131 132 /* Some available location in which to place devices in a simulation (eg. XTMP): */ 133 #define XSHAL_SIMIO_CACHED_VADDR 0xC0000000 134 #define XSHAL_SIMIO_BYPASS_VADDR 0xC0000000 135 #define XSHAL_SIMIO_PADDR 0xC0000000 136 #define XSHAL_SIMIO_SIZE 0x20000000 137 138 139 /*---------------------------------------------------------------------- 140 * For use by reference testbench exit and diagnostic routines. 141 */ 142 #define XSHAL_MAGIC_EXIT 0xe0000000 143 144 /*---------------------------------------------------------------------- 145 * DEVICE-ADDRESS DEPENDENT... 146 * 147 * Values written to CACHEATTR special register (or its equivalent) 148 * to enable and disable caches in various modes. 149 *----------------------------------------------------------------------*/ 150 151 /*---------------------------------------------------------------------- 152 BACKWARD COMPATIBILITY ... 153 ----------------------------------------------------------------------*/ 154 155 /* 156 * NOTE: the following two macros are DEPRECATED. Use the latter 157 * board-specific macros instead, which are specially tuned for the 158 * particular target environments' memory maps. 159 */ 160 #define XSHAL_CACHEATTR_BYPASS XSHAL_XT2000_CACHEATTR_BYPASS /* disable caches in bypass mode */ 161 #define XSHAL_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_DEFAULT /* default setting to enable caches (no writeback!) */ 162 163 /*---------------------------------------------------------------------- 164 GENERIC 165 ----------------------------------------------------------------------*/ 166 167 /* For the following, a 512MB region is used if it contains a system (PIF) RAM, 168 * system (PIF) ROM, local memory, or XLMI. */ 169 170 /* These set any unused 512MB region to cache-BYPASS attribute: */ 171 #define XSHAL_ALLVALID_CACHEATTR_WRITEBACK 0x22442222 /* enable caches in write-back mode */ 172 #define XSHAL_ALLVALID_CACHEATTR_WRITEALLOC 0x22112222 /* enable caches in write-allocate mode */ 173 #define XSHAL_ALLVALID_CACHEATTR_WRITETHRU 0x22112222 /* enable caches in write-through mode */ 174 #define XSHAL_ALLVALID_CACHEATTR_BYPASS 0x22222222 /* disable caches in bypass mode */ 175 #define XSHAL_ALLVALID_CACHEATTR_DEFAULT XSHAL_ALLVALID_CACHEATTR_WRITEBACK /* default setting to enable caches */ 176 177 /* These set any unused 512MB region to ILLEGAL attribute: */ 178 #define XSHAL_STRICT_CACHEATTR_WRITEBACK 0xFF44FFFF /* enable caches in write-back mode */ 179 #define XSHAL_STRICT_CACHEATTR_WRITEALLOC 0xFF11FFFF /* enable caches in write-allocate mode */ 180 #define XSHAL_STRICT_CACHEATTR_WRITETHRU 0xFF11FFFF /* enable caches in write-through mode */ 181 #define XSHAL_STRICT_CACHEATTR_BYPASS 0xFF22FFFF /* disable caches in bypass mode */ 182 #define XSHAL_STRICT_CACHEATTR_DEFAULT XSHAL_STRICT_CACHEATTR_WRITEBACK /* default setting to enable caches */ 183 184 /* These set the first 512MB, if unused, to ILLEGAL attribute to help catch 185 * NULL-pointer dereference bugs; all other unused 512MB regions are set 186 * to cache-BYPASS attribute: */ 187 #define XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 0x2244222F /* enable caches in write-back mode */ 188 #define XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 0x2211222F /* enable caches in write-allocate mode */ 189 #define XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 0x2211222F /* enable caches in write-through mode */ 190 #define XSHAL_TRAPNULL_CACHEATTR_BYPASS 0x2222222F /* disable caches in bypass mode */ 191 #define XSHAL_TRAPNULL_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK /* default setting to enable caches */ 192 193 /*---------------------------------------------------------------------- 194 ISS (Instruction Set Simulator) SPECIFIC ... 195 ----------------------------------------------------------------------*/ 196 197 /* For now, ISS defaults to the TRAPNULL settings: */ 198 #define XSHAL_ISS_CACHEATTR_WRITEBACK XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 199 #define XSHAL_ISS_CACHEATTR_WRITEALLOC XSHAL_TRAPNULL_CACHEATTR_WRITEALLOC 200 #define XSHAL_ISS_CACHEATTR_WRITETHRU XSHAL_TRAPNULL_CACHEATTR_WRITETHRU 201 #define XSHAL_ISS_CACHEATTR_BYPASS XSHAL_TRAPNULL_CACHEATTR_BYPASS 202 #define XSHAL_ISS_CACHEATTR_DEFAULT XSHAL_TRAPNULL_CACHEATTR_WRITEBACK 203 204 #define XSHAL_ISS_PIPE_REGIONS 0 205 #define XSHAL_ISS_SDRAM_REGIONS 0 206 207 208 /*---------------------------------------------------------------------- 209 XT2000 BOARD SPECIFIC ... 210 ----------------------------------------------------------------------*/ 211 212 /* For the following, a 512MB region is used if it contains any system RAM, 213 * system ROM, local memory, XLMI, or other XT2000 board device or memory. 214 * Regions containing devices are forced to cache-BYPASS mode regardless 215 * of whether the macro is _WRITEBACK vs. _BYPASS etc. */ 216 217 /* These set any 512MB region unused on the XT2000 to ILLEGAL attribute: */ 218 #define XSHAL_XT2000_CACHEATTR_WRITEBACK 0xFF44422F /* enable caches in write-back mode */ 219 #define XSHAL_XT2000_CACHEATTR_WRITEALLOC 0xFF11122F /* enable caches in write-allocate mode */ 220 #define XSHAL_XT2000_CACHEATTR_WRITETHRU 0xFF11122F /* enable caches in write-through mode */ 221 #define XSHAL_XT2000_CACHEATTR_BYPASS 0xFF22222F /* disable caches in bypass mode */ 222 #define XSHAL_XT2000_CACHEATTR_DEFAULT XSHAL_XT2000_CACHEATTR_WRITEBACK /* default setting to enable caches */ 223 224 #define XSHAL_XT2000_PIPE_REGIONS 0x00000000 /* BusInt pipeline regions */ 225 #define XSHAL_XT2000_SDRAM_REGIONS 0x00000104 /* BusInt SDRAM regions */ 226 227 228 /*---------------------------------------------------------------------- 229 VECTOR INFO AND SIZES 230 ----------------------------------------------------------------------*/ 231 232 #define XSHAL_VECTORS_PACKED 0 233 #define XSHAL_STATIC_VECTOR_SELECT 0 234 #define XSHAL_RESET_VECTOR_VADDR 0xBEFE0000 235 #define XSHAL_RESET_VECTOR_PADDR 0xBEFE0000 236 #define XSHAL_MEMERROR_VECTOR_VADDR 0xBEFE0400 237 #define XSHAL_MEMERROR_VECTOR_PADDR 0xBEFE0400 238 239 /* 240 * Sizes allocated to vectors by the system (memory map) configuration. 241 * These sizes are constrained by core configuration (eg. one vector's 242 * code cannot overflow into another vector) but are dependent on the 243 * system or board (or LSP) memory map configuration. 244 * 245 * Whether or not each vector happens to be in a system ROM is also 246 * a system configuration matter, sometimes useful, included here also: 247 */ 248 #define XSHAL_RESET_VECTOR_SIZE 0x00000300 249 #define XSHAL_RESET_VECTOR_ISROM 1 250 #define XSHAL_USER_VECTOR_SIZE 0x00000038 251 #define XSHAL_USER_VECTOR_ISROM 1 252 #define XSHAL_PROGRAMEXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ 253 #define XSHAL_USEREXC_VECTOR_SIZE XSHAL_USER_VECTOR_SIZE /* for backward compatibility */ 254 #define XSHAL_KERNEL_VECTOR_SIZE 0x00000038 255 #define XSHAL_KERNEL_VECTOR_ISROM 1 256 #define XSHAL_STACKEDEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ 257 #define XSHAL_KERNELEXC_VECTOR_SIZE XSHAL_KERNEL_VECTOR_SIZE /* for backward compatibility */ 258 #define XSHAL_DOUBLEEXC_VECTOR_SIZE 0x00000040 259 #define XSHAL_DOUBLEEXC_VECTOR_ISROM 1 260 #define XSHAL_WINDOW_VECTORS_SIZE 0x00000178 261 #define XSHAL_WINDOW_VECTORS_ISROM 1 262 #define XSHAL_INTLEVEL2_VECTOR_SIZE 0x00000038 263 #define XSHAL_INTLEVEL2_VECTOR_ISROM 1 264 #define XSHAL_INTLEVEL3_VECTOR_SIZE 0x00000038 265 #define XSHAL_INTLEVEL3_VECTOR_ISROM 1 266 #define XSHAL_INTLEVEL4_VECTOR_SIZE 0x00000038 267 #define XSHAL_INTLEVEL4_VECTOR_ISROM 1 268 #define XSHAL_INTLEVEL5_VECTOR_SIZE 0x00000038 269 #define XSHAL_INTLEVEL5_VECTOR_ISROM 1 270 #define XSHAL_INTLEVEL6_VECTOR_SIZE 0x00000038 271 #define XSHAL_INTLEVEL6_VECTOR_ISROM 1 272 #define XSHAL_DEBUG_VECTOR_SIZE XSHAL_INTLEVEL6_VECTOR_SIZE 273 #define XSHAL_DEBUG_VECTOR_ISROM XSHAL_INTLEVEL6_VECTOR_ISROM 274 #define XSHAL_NMI_VECTOR_SIZE 0x00000038 275 #define XSHAL_NMI_VECTOR_ISROM 1 276 #define XSHAL_INTLEVEL7_VECTOR_SIZE XSHAL_NMI_VECTOR_SIZE 277 278 279 #endif /*XTENSA_CONFIG_SYSTEM_H*/ 280 281 #else 282 283 #error "xcc should not use this header" 284 285 #endif /* __XCC__ */ 286
