1 /****************************************************************************** 2 * Filename: hw_vims_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_VIMS_H__ 34 #define __HW_VIMS_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // VIMS component 40 // 41 //***************************************************************************** 42 // Module Description 43 #define VIMS_O_DESC 0x00000000U 44 45 // Extended Module Description 46 #define VIMS_O_DESCEX 0x00000004U 47 48 // Internal. Only to be used through TI provided API. 49 #define VIMS_O_FLWS1T 0x00000008U 50 51 // Internal. Only to be used through TI provided API. 52 #define VIMS_O_FLWS2T 0x0000000CU 53 54 // Internal. Only to be used through TI provided API. 55 #define VIMS_O_PTRMC0 0x00000018U 56 57 // Internal. Only to be used through TI provided API. 58 #define VIMS_O_B0TRMC1 0x0000001CU 59 60 // Internal. Only to be used through TI provided API. 61 #define VIMS_O_B0TRMC0 0x00000020U 62 63 // Internal. Only to be used through TI provided API. 64 #define VIMS_O_FLBLCK 0x00000100U 65 66 // Internal. Only to be used through TI provided API. 67 #define VIMS_O_CFG 0x000003FCU 68 69 // Flash main region write/erase protection configuration 1 70 #define VIMS_O_WEPRA 0x00000410U 71 72 // Flash main region write/erase protection configuration 2 73 #define VIMS_O_WEPRB 0x00000414U 74 75 // Flash write/erase protection configuration for other regions 76 #define VIMS_O_WEPRAUX 0x0000041CU 77 78 // Flash status 79 #define VIMS_O_FLBSTAT 0x00000420U 80 81 // Cache control 82 #define VIMS_O_CCHCTRL 0x00000424U 83 84 //***************************************************************************** 85 // 86 // Register: VIMS_O_DESC 87 // 88 //***************************************************************************** 89 // Field: [31:16] MODID 90 // 91 // Module identifier used to uniquely identify this IP. 92 #define VIMS_DESC_MODID_W 16U 93 #define VIMS_DESC_MODID_M 0xFFFF0000U 94 #define VIMS_DESC_MODID_S 16U 95 96 // Field: [15:12] STDIPOFF 97 // 98 // Standard IP MMR block offset. Standard IP MMRs are the set of from 99 // aggregated IRQ registers till DTB. 100 // 101 // 0: Standard IP MMRs do not exist 102 // 103 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 104 // address) 105 #define VIMS_DESC_STDIPOFF_W 4U 106 #define VIMS_DESC_STDIPOFF_M 0x0000F000U 107 #define VIMS_DESC_STDIPOFF_S 12U 108 109 // Field: [11:8] INSTIDX 110 // 111 // IP Instance ID number. If multiple instances of IP exist in the device, this 112 // field can identify the instance number (0-15). 113 #define VIMS_DESC_INSTIDX_W 4U 114 #define VIMS_DESC_INSTIDX_M 0x00000F00U 115 #define VIMS_DESC_INSTIDX_S 8U 116 117 // Field: [7:4] MAJREV 118 // 119 // Major revision of IP (0-15). 120 #define VIMS_DESC_MAJREV_W 4U 121 #define VIMS_DESC_MAJREV_M 0x000000F0U 122 #define VIMS_DESC_MAJREV_S 4U 123 124 // Field: [3:0] MINREV 125 // 126 // Minor revision of IP (0-15). 127 #define VIMS_DESC_MINREV_W 4U 128 #define VIMS_DESC_MINREV_M 0x0000000FU 129 #define VIMS_DESC_MINREV_S 0U 130 131 //***************************************************************************** 132 // 133 // Register: VIMS_O_DESCEX 134 // 135 //***************************************************************************** 136 // Field: [27] NBANK 137 // 138 // Provides the FLASH Bank count 139 #define VIMS_DESCEX_NBANK 0x08000000U 140 #define VIMS_DESCEX_NBANK_M 0x08000000U 141 #define VIMS_DESCEX_NBANK_S 27U 142 143 // Field: [26:15] FLSZ 144 // 145 // This provides the total FLASH size in Kilo Bytes. The total FLASH size is 146 // (FLSZ + 1)KB 147 #define VIMS_DESCEX_FLSZ_W 12U 148 #define VIMS_DESCEX_FLSZ_M 0x07FF8000U 149 #define VIMS_DESCEX_FLSZ_S 15U 150 151 // Field: [14:0] ROMSZ 152 // 153 // Provides the size of ROM in Bytes. 154 #define VIMS_DESCEX_ROMSZ_W 15U 155 #define VIMS_DESCEX_ROMSZ_M 0x00007FFFU 156 #define VIMS_DESCEX_ROMSZ_S 0U 157 158 //***************************************************************************** 159 // 160 // Register: VIMS_O_FLWS1T 161 // 162 //***************************************************************************** 163 // Field: [2:0] VAL 164 // 165 // Internal. Only to be used through TI provided API. 166 // ENUMs: 167 // WS7 Internal. Only to be used through TI provided API. 168 // WS6 Internal. Only to be used through TI provided API. 169 // WS5 Internal. Only to be used through TI provided API. 170 // WS4 Internal. Only to be used through TI provided API. 171 // WS3 Internal. Only to be used through TI provided API. 172 // WS2 Internal. Only to be used through TI provided API. 173 // WS1 Internal. Only to be used through TI provided API. 174 // WS0 Internal. Only to be used through TI provided API. 175 #define VIMS_FLWS1T_VAL_W 3U 176 #define VIMS_FLWS1T_VAL_M 0x00000007U 177 #define VIMS_FLWS1T_VAL_S 0U 178 #define VIMS_FLWS1T_VAL_WS7 0x00000007U 179 #define VIMS_FLWS1T_VAL_WS6 0x00000006U 180 #define VIMS_FLWS1T_VAL_WS5 0x00000005U 181 #define VIMS_FLWS1T_VAL_WS4 0x00000004U 182 #define VIMS_FLWS1T_VAL_WS3 0x00000003U 183 #define VIMS_FLWS1T_VAL_WS2 0x00000002U 184 #define VIMS_FLWS1T_VAL_WS1 0x00000001U 185 #define VIMS_FLWS1T_VAL_WS0 0x00000000U 186 187 //***************************************************************************** 188 // 189 // Register: VIMS_O_FLWS2T 190 // 191 //***************************************************************************** 192 // Field: [2:0] VAL 193 // 194 // Internal. Only to be used through TI provided API. 195 // ENUMs: 196 // WS7 Internal. Only to be used through TI provided API. 197 // WS6 Internal. Only to be used through TI provided API. 198 // WS5 Internal. Only to be used through TI provided API. 199 // WS4 Internal. Only to be used through TI provided API. 200 // WS3 Internal. Only to be used through TI provided API. 201 // WS2 Internal. Only to be used through TI provided API. 202 // WS1 Internal. Only to be used through TI provided API. 203 // WS0 Internal. Only to be used through TI provided API. 204 #define VIMS_FLWS2T_VAL_W 3U 205 #define VIMS_FLWS2T_VAL_M 0x00000007U 206 #define VIMS_FLWS2T_VAL_S 0U 207 #define VIMS_FLWS2T_VAL_WS7 0x00000007U 208 #define VIMS_FLWS2T_VAL_WS6 0x00000006U 209 #define VIMS_FLWS2T_VAL_WS5 0x00000005U 210 #define VIMS_FLWS2T_VAL_WS4 0x00000004U 211 #define VIMS_FLWS2T_VAL_WS3 0x00000003U 212 #define VIMS_FLWS2T_VAL_WS2 0x00000002U 213 #define VIMS_FLWS2T_VAL_WS1 0x00000001U 214 #define VIMS_FLWS2T_VAL_WS0 0x00000000U 215 216 //***************************************************************************** 217 // 218 // Register: VIMS_O_PTRMC0 219 // 220 //***************************************************************************** 221 // Field: [31:0] VAL 222 // 223 // Internal. Only to be used through TI provided API. 224 #define VIMS_PTRMC0_VAL_W 32U 225 #define VIMS_PTRMC0_VAL_M 0xFFFFFFFFU 226 #define VIMS_PTRMC0_VAL_S 0U 227 228 //***************************************************************************** 229 // 230 // Register: VIMS_O_B0TRMC1 231 // 232 //***************************************************************************** 233 // Field: [31:0] VAL 234 // 235 // Internal. Only to be used through TI provided API. 236 #define VIMS_B0TRMC1_VAL_W 32U 237 #define VIMS_B0TRMC1_VAL_M 0xFFFFFFFFU 238 #define VIMS_B0TRMC1_VAL_S 0U 239 240 //***************************************************************************** 241 // 242 // Register: VIMS_O_B0TRMC0 243 // 244 //***************************************************************************** 245 // Field: [31:0] VAL 246 // 247 // Internal. Only to be used through TI provided API. 248 #define VIMS_B0TRMC0_VAL_W 32U 249 #define VIMS_B0TRMC0_VAL_M 0xFFFFFFFFU 250 #define VIMS_B0TRMC0_VAL_S 0U 251 252 //***************************************************************************** 253 // 254 // Register: VIMS_O_FLBLCK 255 // 256 //***************************************************************************** 257 // Field: [0] VAL 258 // 259 // Internal. Only to be used through TI provided API. 260 // ENUMs: 261 // BLOCK Internal. Only to be used through TI provided API. 262 // ALLOW Internal. Only to be used through TI provided API. 263 #define VIMS_FLBLCK_VAL 0x00000001U 264 #define VIMS_FLBLCK_VAL_M 0x00000001U 265 #define VIMS_FLBLCK_VAL_S 0U 266 #define VIMS_FLBLCK_VAL_BLOCK 0x00000001U 267 #define VIMS_FLBLCK_VAL_ALLOW 0x00000000U 268 269 //***************************************************************************** 270 // 271 // Register: VIMS_O_CFG 272 // 273 //***************************************************************************** 274 // Field: [1] TRMVLID 275 // 276 // Internal. Only to be used through TI provided API. 277 #define VIMS_CFG_TRMVLID 0x00000002U 278 #define VIMS_CFG_TRMVLID_M 0x00000002U 279 #define VIMS_CFG_TRMVLID_S 1U 280 281 // Field: [0] WEPRTRM 282 // 283 // Internal. Only to be used through TI provided API. 284 // ENUMs: 285 // ALLOW Internal. Only to be used through TI provided API. 286 // RESTRICT Internal. Only to be used through TI provided API. 287 #define VIMS_CFG_WEPRTRM 0x00000001U 288 #define VIMS_CFG_WEPRTRM_M 0x00000001U 289 #define VIMS_CFG_WEPRTRM_S 0U 290 #define VIMS_CFG_WEPRTRM_ALLOW 0x00000001U 291 #define VIMS_CFG_WEPRTRM_RESTRICT 0x00000000U 292 293 //***************************************************************************** 294 // 295 // Register: VIMS_O_WEPRA 296 // 297 //***************************************************************************** 298 // Field: [31:0] VAL 299 // 300 // Flash write/erase protection configuration value. 301 #define VIMS_WEPRA_VAL_W 32U 302 #define VIMS_WEPRA_VAL_M 0xFFFFFFFFU 303 #define VIMS_WEPRA_VAL_S 0U 304 305 //***************************************************************************** 306 // 307 // Register: VIMS_O_WEPRB 308 // 309 //***************************************************************************** 310 // Field: [27:0] VAL 311 // 312 // Flash write/erase protection configuration value. 313 #define VIMS_WEPRB_VAL_W 28U 314 #define VIMS_WEPRB_VAL_M 0x0FFFFFFFU 315 #define VIMS_WEPRB_VAL_S 0U 316 317 //***************************************************************************** 318 // 319 // Register: VIMS_O_WEPRAUX 320 // 321 //***************************************************************************** 322 // Field: [2] WEPREGR 323 // 324 // Flash engr region write/erase protection configuration value. 325 #define VIMS_WEPRAUX_WEPREGR 0x00000004U 326 #define VIMS_WEPRAUX_WEPREGR_M 0x00000004U 327 #define VIMS_WEPRAUX_WEPREGR_S 2U 328 329 // Field: [1] WEPRTRM 330 // 331 // Flash trim region write/erase protection configuration value. 332 #define VIMS_WEPRAUX_WEPRTRM 0x00000002U 333 #define VIMS_WEPRAUX_WEPRTRM_M 0x00000002U 334 #define VIMS_WEPRAUX_WEPRTRM_S 1U 335 336 // Field: [0] WEPRNMN 337 // 338 // Flash non main region write/erase protection configuration value. 339 #define VIMS_WEPRAUX_WEPRNMN 0x00000001U 340 #define VIMS_WEPRAUX_WEPRNMN_M 0x00000001U 341 #define VIMS_WEPRAUX_WEPRNMN_S 0U 342 343 //***************************************************************************** 344 // 345 // Register: VIMS_O_FLBSTAT 346 // 347 //***************************************************************************** 348 // Field: [3] PARERR 349 // 350 // This bit indicates parity error on write/erase and read protection MMRs. 351 // This bit is sticky when set to 1 by hardware. 352 // ENUMs: 353 // ERROR Error 354 // NOERROR No Error 355 #define VIMS_FLBSTAT_PARERR 0x00000008U 356 #define VIMS_FLBSTAT_PARERR_M 0x00000008U 357 #define VIMS_FLBSTAT_PARERR_S 3U 358 #define VIMS_FLBSTAT_PARERR_ERROR 0x00000008U 359 #define VIMS_FLBSTAT_PARERR_NOERROR 0x00000000U 360 361 // Field: [2] B0BSY 362 // 363 // This bit indicates if flash is busy. 364 // ENUMs: 365 // BUSY Busy 366 // IDLE Idle 367 #define VIMS_FLBSTAT_B0BSY 0x00000004U 368 #define VIMS_FLBSTAT_B0BSY_M 0x00000004U 369 #define VIMS_FLBSTAT_B0BSY_S 2U 370 #define VIMS_FLBSTAT_B0BSY_BUSY 0x00000004U 371 #define VIMS_FLBSTAT_B0BSY_IDLE 0x00000000U 372 373 // Field: [1] B2TRDY 374 // 375 // This bit indicates if flash is ready in 2T mode. 376 // ENUMs: 377 // READY Ready 378 // NOTREADY Not Ready 379 #define VIMS_FLBSTAT_B2TRDY 0x00000002U 380 #define VIMS_FLBSTAT_B2TRDY_M 0x00000002U 381 #define VIMS_FLBSTAT_B2TRDY_S 1U 382 #define VIMS_FLBSTAT_B2TRDY_READY 0x00000002U 383 #define VIMS_FLBSTAT_B2TRDY_NOTREADY 0x00000000U 384 385 // Field: [0] B1TRDY 386 // 387 // This bit indicates if flash is ready in 1T mode. 388 // ENUMs: 389 // READY Ready 390 // NOTREADY Not Ready 391 #define VIMS_FLBSTAT_B1TRDY 0x00000001U 392 #define VIMS_FLBSTAT_B1TRDY_M 0x00000001U 393 #define VIMS_FLBSTAT_B1TRDY_S 0U 394 #define VIMS_FLBSTAT_B1TRDY_READY 0x00000001U 395 #define VIMS_FLBSTAT_B1TRDY_NOTREADY 0x00000000U 396 397 //***************************************************************************** 398 // 399 // Register: VIMS_O_CCHCTRL 400 // 401 //***************************************************************************** 402 // Field: [2] CCHMPEN 403 // 404 // This bit is used to enable the micropredictor unit. 405 // ENUMs: 406 // EN Enable 407 // DIS Disable 408 #define VIMS_CCHCTRL_CCHMPEN 0x00000004U 409 #define VIMS_CCHCTRL_CCHMPEN_M 0x00000004U 410 #define VIMS_CCHCTRL_CCHMPEN_S 2U 411 #define VIMS_CCHCTRL_CCHMPEN_EN 0x00000004U 412 #define VIMS_CCHCTRL_CCHMPEN_DIS 0x00000000U 413 414 // Field: [1] CCHPFEN 415 // 416 // This bit is used to enable the prefetch unit. 417 // ENUMs: 418 // EN Enable 419 // DIS Disable 420 #define VIMS_CCHCTRL_CCHPFEN 0x00000002U 421 #define VIMS_CCHCTRL_CCHPFEN_M 0x00000002U 422 #define VIMS_CCHCTRL_CCHPFEN_S 1U 423 #define VIMS_CCHCTRL_CCHPFEN_EN 0x00000002U 424 #define VIMS_CCHCTRL_CCHPFEN_DIS 0x00000000U 425 426 // Field: [0] CCHEN 427 // 428 // This bit is used to enable the cache. 429 // ENUMs: 430 // EN Enable 431 // DIS Disable 432 #define VIMS_CCHCTRL_CCHEN 0x00000001U 433 #define VIMS_CCHCTRL_CCHEN_M 0x00000001U 434 #define VIMS_CCHCTRL_CCHEN_S 0U 435 #define VIMS_CCHCTRL_CCHEN_EN 0x00000001U 436 #define VIMS_CCHCTRL_CCHEN_DIS 0x00000000U 437 438 439 //***************************************************************************** 440 // 441 // This section defines the register offsets of 442 // VIMS component 443 // 444 //***************************************************************************** 445 // Status 446 #define VIMS_O_STAT 0x00000000 447 448 // Control 449 #define VIMS_O_CTL 0x00000004 450 451 //***************************************************************************** 452 // 453 // Register: VIMS_O_STAT 454 // 455 //***************************************************************************** 456 // Field: [5] IDCODE_LB_DIS 457 // 458 // Icode/Dcode flash line buffer status 459 // 460 // 0: Enabled or in transition to disabled 461 // 1: Disabled and flushed 462 #define VIMS_STAT_IDCODE_LB_DIS 0x00000020 463 #define VIMS_STAT_IDCODE_LB_DIS_BITN 5 464 #define VIMS_STAT_IDCODE_LB_DIS_M 0x00000020 465 #define VIMS_STAT_IDCODE_LB_DIS_S 5 466 467 // Field: [4] SYSBUS_LB_DIS 468 // 469 // Sysbus flash line buffer control 470 // 471 // 0: Enabled or in transition to disabled 472 // 1: Disabled and flushed 473 #define VIMS_STAT_SYSBUS_LB_DIS 0x00000010 474 #define VIMS_STAT_SYSBUS_LB_DIS_BITN 4 475 #define VIMS_STAT_SYSBUS_LB_DIS_M 0x00000010 476 #define VIMS_STAT_SYSBUS_LB_DIS_S 4 477 478 // Field: [3] MODE_CHANGING 479 // 480 // VIMS mode change status 481 // 482 // 0: VIMS is in the mode defined by MODE 483 // 1: VIMS is in the process of changing to the mode given in CTL.MODE 484 #define VIMS_STAT_MODE_CHANGING 0x00000008 485 #define VIMS_STAT_MODE_CHANGING_BITN 3 486 #define VIMS_STAT_MODE_CHANGING_M 0x00000008 487 #define VIMS_STAT_MODE_CHANGING_S 3 488 489 // Field: [2] INV 490 // 491 // This bit is set when invalidation of the cache memory is active / ongoing 492 #define VIMS_STAT_INV 0x00000004 493 #define VIMS_STAT_INV_BITN 2 494 #define VIMS_STAT_INV_M 0x00000004 495 #define VIMS_STAT_INV_S 2 496 497 // Field: [1:0] MODE 498 // 499 // Current VIMS mode 500 // ENUMs: 501 // OFF VIMS Off mode 502 // CACHE VIMS Cache mode 503 // GPRAM VIMS GPRAM mode 504 #define VIMS_STAT_MODE_W 2 505 #define VIMS_STAT_MODE_M 0x00000003 506 #define VIMS_STAT_MODE_S 0 507 #define VIMS_STAT_MODE_OFF 0x00000003 508 #define VIMS_STAT_MODE_CACHE 0x00000001 509 #define VIMS_STAT_MODE_GPRAM 0x00000000 510 511 //***************************************************************************** 512 // 513 // Register: VIMS_O_CTL 514 // 515 //***************************************************************************** 516 // Field: [31] STATS_CLR 517 // 518 // Set this bit to clear statistic counters. 519 #define VIMS_CTL_STATS_CLR 0x80000000 520 #define VIMS_CTL_STATS_CLR_BITN 31 521 #define VIMS_CTL_STATS_CLR_M 0x80000000 522 #define VIMS_CTL_STATS_CLR_S 31 523 524 // Field: [30] STATS_EN 525 // 526 // Set this bit to enable statistic counters. 527 #define VIMS_CTL_STATS_EN 0x40000000 528 #define VIMS_CTL_STATS_EN_BITN 30 529 #define VIMS_CTL_STATS_EN_M 0x40000000 530 #define VIMS_CTL_STATS_EN_S 30 531 532 // Field: [29] DYN_CG_EN 533 // 534 // 0: The in-built clock gate functionality is bypassed. 535 // 1: The in-built clock gate functionality is enabled, automatically gating 536 // the clock when not needed. 537 #define VIMS_CTL_DYN_CG_EN 0x20000000 538 #define VIMS_CTL_DYN_CG_EN_BITN 29 539 #define VIMS_CTL_DYN_CG_EN_M 0x20000000 540 #define VIMS_CTL_DYN_CG_EN_S 29 541 542 // Field: [5] IDCODE_LB_DIS 543 // 544 // Icode/Dcode flash line buffer control 545 // 546 // 0: Enable 547 // 1: Disable 548 #define VIMS_CTL_IDCODE_LB_DIS 0x00000020 549 #define VIMS_CTL_IDCODE_LB_DIS_BITN 5 550 #define VIMS_CTL_IDCODE_LB_DIS_M 0x00000020 551 #define VIMS_CTL_IDCODE_LB_DIS_S 5 552 553 // Field: [4] SYSBUS_LB_DIS 554 // 555 // Sysbus flash line buffer control 556 // 557 // 0: Enable 558 // 1: Disable 559 #define VIMS_CTL_SYSBUS_LB_DIS 0x00000010 560 #define VIMS_CTL_SYSBUS_LB_DIS_BITN 4 561 #define VIMS_CTL_SYSBUS_LB_DIS_M 0x00000010 562 #define VIMS_CTL_SYSBUS_LB_DIS_S 4 563 564 // Field: [3] ARB_CFG 565 // 566 // Icode/Dcode and sysbus arbitation scheme 567 // 568 // 0: Static arbitration (icode/docde > sysbus) 569 // 1: Round-robin arbitration 570 #define VIMS_CTL_ARB_CFG 0x00000008 571 #define VIMS_CTL_ARB_CFG_BITN 3 572 #define VIMS_CTL_ARB_CFG_M 0x00000008 573 #define VIMS_CTL_ARB_CFG_S 3 574 575 // Field: [2] PREF_EN 576 // 577 // Tag prefetch control 578 // 579 // 0: Disabled 580 // 1: Enabled 581 #define VIMS_CTL_PREF_EN 0x00000004 582 #define VIMS_CTL_PREF_EN_BITN 2 583 #define VIMS_CTL_PREF_EN_M 0x00000004 584 #define VIMS_CTL_PREF_EN_S 2 585 586 // Field: [1:0] MODE 587 // 588 // VIMS mode request. 589 // Write accesses to this field will be blocked while STAT.MODE_CHANGING is set 590 // to 1. 591 // ENUMs: 592 // OFF VIMS Off mode 593 // CACHE VIMS Cache mode 594 // GPRAM VIMS GPRAM mode 595 #define VIMS_CTL_MODE_W 2 596 #define VIMS_CTL_MODE_M 0x00000003 597 #define VIMS_CTL_MODE_S 0 598 #define VIMS_CTL_MODE_OFF 0x00000003 599 #define VIMS_CTL_MODE_CACHE 0x00000001 600 #define VIMS_CTL_MODE_GPRAM 0x00000000 601 602 603 604 #endif // __VIMS__ 605
