1 /****************************************************************************** 2 * Filename: hw_scscs_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_SCSCS_H__ 34 #define __HW_SCSCS_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // SCSCS component 40 // 41 //***************************************************************************** 42 // Peripheral ID Register 4 43 #define SCSCS_O_PIDR4 0x00000010U 44 45 // Peripheral ID Register 5 46 #define SCSCS_O_PIDR5 0x00000014U 47 48 // Peripheral ID Register 6 49 #define SCSCS_O_PIDR6 0x00000018U 50 51 // Peripheral ID Register 7 52 #define SCSCS_O_PIDR7 0x0000001CU 53 54 // Peripheral ID Register 0 55 #define SCSCS_O_PIDR0 0x00000020U 56 57 // Peripheral ID Register 1 58 #define SCSCS_O_PIDR1 0x00000024U 59 60 // Peripheral ID Register 2 61 #define SCSCS_O_PIDR2 0x00000028U 62 63 // Peripheral ID Register 3 64 #define SCSCS_O_PIDR3 0x0000002CU 65 66 // Component ID Register 0 67 #define SCSCS_O_CIDR0 0x00000030U 68 69 // Component ID Register 1 70 #define SCSCS_O_CIDR1 0x00000034U 71 72 // Component ID Register 2 73 #define SCSCS_O_CIDR2 0x00000038U 74 75 // Component ID Register 3 76 #define SCSCS_O_CIDR3 0x0000003CU 77 78 //***************************************************************************** 79 // 80 // Register: SCSCS_O_PIDR4 81 // 82 //***************************************************************************** 83 // Field: [7:4] SIZE 84 // 85 // This is a 4-bit value that indicates the total contiguous size of the memory 86 // window used by this component in powers of 2 from the standard 4KB. If a 87 // component only requires the standard 4KB then this should read as 0x0, 4KB 88 // only, for 8KB set to 0x1, 16KB == 0x2, 32KB == 0x3, and so on. 89 #define SCSCS_PIDR4_SIZE_W 4U 90 #define SCSCS_PIDR4_SIZE_M 0x000000F0U 91 #define SCSCS_PIDR4_SIZE_S 4U 92 93 // Field: [3:0] DES_2 94 // 95 // Number of JEDEC continuation codes. Indicates the designer of the component 96 // (along with the identity code) 97 #define SCSCS_PIDR4_DES_2_W 4U 98 #define SCSCS_PIDR4_DES_2_M 0x0000000FU 99 #define SCSCS_PIDR4_DES_2_S 0U 100 101 //***************************************************************************** 102 // 103 // Register: SCSCS_O_PIDR5 104 // 105 //***************************************************************************** 106 //***************************************************************************** 107 // 108 // Register: SCSCS_O_PIDR6 109 // 110 //***************************************************************************** 111 //***************************************************************************** 112 // 113 // Register: SCSCS_O_PIDR7 114 // 115 //***************************************************************************** 116 //***************************************************************************** 117 // 118 // Register: SCSCS_O_PIDR0 119 // 120 //***************************************************************************** 121 // Field: [7:0] PART_0 122 // 123 // Bits [7:0] of the component's part number. This is selected by the designer 124 // of the component. 125 #define SCSCS_PIDR0_PART_0_W 8U 126 #define SCSCS_PIDR0_PART_0_M 0x000000FFU 127 #define SCSCS_PIDR0_PART_0_S 0U 128 129 //***************************************************************************** 130 // 131 // Register: SCSCS_O_PIDR1 132 // 133 //***************************************************************************** 134 // Field: [7:4] DES_0 135 // 136 // Bits [3:0] of the JEDEC identity code indicating the designer of the 137 // component (along with the continuation code) 138 #define SCSCS_PIDR1_DES_0_W 4U 139 #define SCSCS_PIDR1_DES_0_M 0x000000F0U 140 #define SCSCS_PIDR1_DES_0_S 4U 141 142 // Field: [3:0] PART_1 143 // 144 // Bits [11:8] of the component's part number. This is selected by the designer 145 // of the component. 146 #define SCSCS_PIDR1_PART_1_W 4U 147 #define SCSCS_PIDR1_PART_1_M 0x0000000FU 148 #define SCSCS_PIDR1_PART_1_S 0U 149 150 //***************************************************************************** 151 // 152 // Register: SCSCS_O_PIDR2 153 // 154 //***************************************************************************** 155 // Field: [7:4] REVISION 156 // 157 // The Revision field is an incremental value starting at 0x0 for the first 158 // design of this component. This only increases by 1 for both major and minor 159 // revisions and is simply used as a look-up to establish the exact major/minor 160 // revision. 161 #define SCSCS_PIDR2_REVISION_W 4U 162 #define SCSCS_PIDR2_REVISION_M 0x000000F0U 163 #define SCSCS_PIDR2_REVISION_S 4U 164 165 // Field: [3] JEDEC 166 // 167 // Always set. Indicates that a JEDEC assigned value is used 168 #define SCSCS_PIDR2_JEDEC 0x00000008U 169 #define SCSCS_PIDR2_JEDEC_M 0x00000008U 170 #define SCSCS_PIDR2_JEDEC_S 3U 171 172 // Field: [2:0] DES_1 173 // 174 // Bits [6:4] of the JEDEC identity code indicating the designer of the 175 // component (along with the continuation code) 176 #define SCSCS_PIDR2_DES_1_W 3U 177 #define SCSCS_PIDR2_DES_1_M 0x00000007U 178 #define SCSCS_PIDR2_DES_1_S 0U 179 180 //***************************************************************************** 181 // 182 // Register: SCSCS_O_PIDR3 183 // 184 //***************************************************************************** 185 // Field: [7:4] REVAND 186 // 187 // This field indicates minor errata fixes specific to this design, for example 188 // metal fixes after implementation. In most cases this field is zero. It is 189 // recommended that component designers ensure this field can be changed by a 190 // metal fix if required, for example by driving it from registers that reset 191 // to zero. 192 #define SCSCS_PIDR3_REVAND_W 4U 193 #define SCSCS_PIDR3_REVAND_M 0x000000F0U 194 #define SCSCS_PIDR3_REVAND_S 4U 195 196 // Field: [3:0] CMOD 197 // 198 // Where the component is reusable IP, this value indicates if the customer has 199 // modified the behavior of the component. In most cases this field is zero. 200 #define SCSCS_PIDR3_CMOD_W 4U 201 #define SCSCS_PIDR3_CMOD_M 0x0000000FU 202 #define SCSCS_PIDR3_CMOD_S 0U 203 204 //***************************************************************************** 205 // 206 // Register: SCSCS_O_CIDR0 207 // 208 //***************************************************************************** 209 // Field: [7:0] PRMBL_0 210 // 211 // Contains bits [7:0] of the component identification 212 #define SCSCS_CIDR0_PRMBL_0_W 8U 213 #define SCSCS_CIDR0_PRMBL_0_M 0x000000FFU 214 #define SCSCS_CIDR0_PRMBL_0_S 0U 215 216 //***************************************************************************** 217 // 218 // Register: SCSCS_O_CIDR1 219 // 220 //***************************************************************************** 221 // Field: [7:4] CLASS 222 // 223 // Class of the component. E.g. ROM table, CoreSight component etc. Constitutes 224 // bits [15:12] of the component identification. 225 #define SCSCS_CIDR1_CLASS_W 4U 226 #define SCSCS_CIDR1_CLASS_M 0x000000F0U 227 #define SCSCS_CIDR1_CLASS_S 4U 228 229 // Field: [3:0] PRMBL_1 230 // 231 // Contains bits [11:8] of the component identification 232 #define SCSCS_CIDR1_PRMBL_1_W 4U 233 #define SCSCS_CIDR1_PRMBL_1_M 0x0000000FU 234 #define SCSCS_CIDR1_PRMBL_1_S 0U 235 236 //***************************************************************************** 237 // 238 // Register: SCSCS_O_CIDR2 239 // 240 //***************************************************************************** 241 // Field: [7:0] PRMBL_2 242 // 243 // Contains bits [23:16] of the component identification 244 #define SCSCS_CIDR2_PRMBL_2_W 8U 245 #define SCSCS_CIDR2_PRMBL_2_M 0x000000FFU 246 #define SCSCS_CIDR2_PRMBL_2_S 0U 247 248 //***************************************************************************** 249 // 250 // Register: SCSCS_O_CIDR3 251 // 252 //***************************************************************************** 253 // Field: [7:0] PRMBL_3 254 // 255 // Contains bits [31:24] of the component identification 256 #define SCSCS_CIDR3_PRMBL_3_W 8U 257 #define SCSCS_CIDR3_PRMBL_3_M 0x000000FFU 258 #define SCSCS_CIDR3_PRMBL_3_S 0U 259 260 261 #endif // __SCSCS__ 262
