1 /****************************************************************************** 2 * Filename: hw_lgpt3_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LGPT3_H__ 34 #define __HW_LGPT3_H__ 35 36 //***************************************************************************** 37 // 38 // Register: LGPT3_O_CNTR 39 // 40 //***************************************************************************** 41 // Field: [23:0] VAL 42 // 43 // Current counter value. 44 // If CTL.MODE = QDEC this can be used to set the initial counter value during 45 // QDEC. Writing to CNTR in other modes than QDEC is possible, but may result 46 // in unpredictable behavior. 47 #define LGPT3_CNTR_VAL_W 24U 48 #define LGPT3_CNTR_VAL_M 0x00FFFFFFU 49 50 //***************************************************************************** 51 // 52 // Register: LGPT3_O_DMARW 53 // 54 //***************************************************************************** 55 // Field: [23:0] VAL 56 // 57 // DMA read write value. 58 // 59 // The value that is read/written from/to the registers. 60 #define LGPT3_DMARW_VAL_W 24U 61 #define LGPT3_DMARW_VAL_M 0x00FFFFFFU 62 63 //***************************************************************************** 64 // 65 // Register: LGPT3_O_PTGT 66 // 67 //***************************************************************************** 68 // Field: [23:0] VAL 69 // 70 // The pipleline target value. 71 #define LGPT3_PTGT_VAL_W 24U 72 #define LGPT3_PTGT_VAL_M 0x00FFFFFFU 73 74 //***************************************************************************** 75 // 76 // Register: LGPT3_O_PC0CC 77 // 78 //***************************************************************************** 79 // Field: [23:0] VAL 80 // 81 // Pipeline Capture Compare value. 82 // 83 // User defined pipeline compare value or channel-updated capture value. 84 // 85 // A read or write to this register will clear the RIS.C0CC interrupt. 86 // 87 // Compare mode: 88 // An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is 89 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 90 // and prevents jitter on the edges of the generated signal. 91 // 92 // Capture mode: 93 // When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 94 // the low or high phase of the selected signal. This is specified by 95 // C0CFG.EDGE. 96 #define LGPT3_PC0CC_VAL_W 24U 97 #define LGPT3_PC0CC_VAL_M 0x00FFFFFFU 98 99 //***************************************************************************** 100 // 101 // Register: LGPT3_O_PC1CC 102 // 103 //***************************************************************************** 104 // Field: [23:0] VAL 105 // 106 // Pipeline Capture Compare value. 107 // 108 // User defined pipeline compare value or channel-updated capture value. 109 // 110 // A read or write to this register will clear the RIS.C1CC interrupt. 111 // 112 // Compare mode: 113 // An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is 114 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 115 // and prevents jitter on the edges of the generated signal. 116 // 117 // Capture mode: 118 // When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 119 // the low or high phase of the selected signal. This is specified by 120 // C1CFG.EDGE. 121 #define LGPT3_PC1CC_VAL_W 24U 122 #define LGPT3_PC1CC_VAL_M 0x00FFFFFFU 123 124 //***************************************************************************** 125 // 126 // Register: LGPT3_O_PC2CC 127 // 128 //***************************************************************************** 129 // Field: [23:0] VAL 130 // 131 // Pipeline Capture Compare value. 132 // 133 // User defined pipeline compare value or channel-updated capture value. 134 // 135 // A read or write to this register will clear the RIS.C2CC interrupt. 136 // 137 // Compare mode: 138 // An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is 139 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 140 // and prevents jitter on the edges of the generated signal. 141 // 142 // Capture mode: 143 // When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 144 // the low or high phase of the selected signal. This is specified by 145 // C2CFG.EDGE. 146 #define LGPT3_PC2CC_VAL_W 24U 147 #define LGPT3_PC2CC_VAL_M 0x00FFFFFFU 148 149 //***************************************************************************** 150 // 151 // Register: LGPT3_O_TGT 152 // 153 //***************************************************************************** 154 // Field: [23:0] VAL 155 // 156 // User defined counter target value. 157 #define LGPT3_TGT_VAL_W 24U 158 #define LGPT3_TGT_VAL_M 0x00FFFFFFU 159 160 //***************************************************************************** 161 // 162 // Register: LGPT3_O_C0CC 163 // 164 //***************************************************************************** 165 // Field: [23:0] VAL 166 // 167 // Capture Compare value. 168 // 169 // User defined compare value or channel-updated capture value. 170 // 171 // A read or write to this register will clear the RIS.C0CC interrupt. 172 // 173 // Compare mode: 174 // VAL is compared against CNTR.VAL and an event is generated as specified by 175 // C0CFG.CCACT when these are equal. 176 // 177 // Capture mode: 178 // The current counter value is stored in VAL when a capture event occurs. 179 // C0CFG.CCACT determines if VAL is a signal period or a regular capture value. 180 #define LGPT3_C0CC_VAL_W 24U 181 #define LGPT3_C0CC_VAL_M 0x00FFFFFFU 182 183 //***************************************************************************** 184 // 185 // Register: LGPT3_O_C1CC 186 // 187 //***************************************************************************** 188 // Field: [23:0] VAL 189 // 190 // Capture Compare value. 191 // 192 // User defined compare value or channel-updated capture value. 193 // 194 // A read or write to this register will clear the RIS.C1CC interrupt. 195 // 196 // Compare mode: 197 // VAL is compared against CNTR.VAL and an event is generated as specified by 198 // C1CFG.CCACT when these are equal. 199 // 200 // Capture mode: 201 // The current counter value is stored in VAL when a capture event occurs. 202 // C1CFG.CCACT determines if VAL is a signal period or a regular capture value. 203 #define LGPT3_C1CC_VAL_W 24U 204 #define LGPT3_C1CC_VAL_M 0x00FFFFFFU 205 206 //***************************************************************************** 207 // 208 // Register: LGPT3_O_C2CC 209 // 210 //***************************************************************************** 211 // Field: [23:0] VAL 212 // 213 // Capture Compare value. 214 // 215 // User defined compare value or channel-updated capture value. 216 // 217 // A read or write to this register will clear the RIS.C2CC interrupt. 218 // 219 // Compare mode: 220 // VAL is compared against CNTR.VAL and an event is generated as specified by 221 // C2CFG.CCACT when these are equal. 222 // 223 // Capture mode: 224 // The current counter value is stored in VAL when a capture event occurs. 225 // C2CFG.CCACT determines if VAL is a signal period or a regular capture value. 226 #define LGPT3_C2CC_VAL_W 24U 227 #define LGPT3_C2CC_VAL_M 0x00FFFFFFU 228 229 //***************************************************************************** 230 // 231 // Register: LGPT3_O_PTGTNC 232 // 233 //***************************************************************************** 234 // Field: [23:0] VAL 235 // 236 // A read or write to this register will not clear the RIS.TGT interrupt. 237 // 238 // If CTL.MODE != QDEC. 239 // Target value for next counter period. 240 // The timer copies VAL to TGT.VAL when CNTR.VAL becomes 0. The copy does not 241 // happen when restarting the timer. 242 // This is useful to avoid period jitter in PWM applications with time-varying 243 // period, sometimes referenced as phase corrected PWM. 244 // 245 // If CTL.MODE = QDEC. 246 // The CNTR.VAL is updated with VAL on IDX. VAL is not loaded into TGT.VAL when 247 // CNTR.VAL becomes 0. 248 #define LGPT3_PTGTNC_VAL_W 24U 249 #define LGPT3_PTGTNC_VAL_M 0x00FFFFFFU 250 251 //***************************************************************************** 252 // 253 // Register: LGPT3_O_PC0CCNC 254 // 255 //***************************************************************************** 256 // Field: [23:0] VAL 257 // 258 // Pipeline Capture Compare value. 259 // 260 // User defined pipeline compare value or channel-updated capture value. 261 // 262 // A read or write to this register will not clear the RIS.C0CC interrupt. 263 // 264 // Compare mode: 265 // An update of VAL will be transferred to C0CC.VAL when the next CNTR.VAL is 266 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 267 // and prevents jitter on the edges of the generated signal. 268 // 269 // Capture mode: 270 // When C0CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 271 // the low or high phase of the selected signal. This is specified by 272 // C0CFG.EDGE. 273 #define LGPT3_PC0CCNC_VAL_W 24U 274 #define LGPT3_PC0CCNC_VAL_M 0x00FFFFFFU 275 276 //***************************************************************************** 277 // 278 // Register: LGPT3_O_PC1CCNC 279 // 280 //***************************************************************************** 281 // Field: [23:0] VAL 282 // 283 // Pipeline Capture Compare value. 284 // 285 // User defined pipeline compare value or channel-updated capture value. 286 // 287 // A read or write to this register will not clear the RIS.C1CC interrupt. 288 // 289 // Compare mode: 290 // An update of VAL will be transferred to C1CC.VAL when the next CNTR.VAL is 291 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 292 // and prevents jitter on the edges of the generated signal. 293 // 294 // Capture mode: 295 // When C1CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 296 // the low or high phase of the selected signal. This is specified by 297 // C1CFG.EDGE. 298 #define LGPT3_PC1CCNC_VAL_W 24U 299 #define LGPT3_PC1CCNC_VAL_M 0x00FFFFFFU 300 301 //***************************************************************************** 302 // 303 // Register: LGPT3_O_PC2CCNC 304 // 305 //***************************************************************************** 306 // Field: [23:0] VAL 307 // 308 // Pipeline Capture Compare value. 309 // 310 // User defined pipeline compare value or channel-updated capture value. 311 // 312 // A read or write to this register will not clear the RIS.C2CC interrupt. 313 // 314 // Compare mode: 315 // An update of VAL will be transferred to C2CC.VAL when the next CNTR.VAL is 316 // zero and CTL.MODE is different from DIS. This is useful for PWM generation 317 // and prevents jitter on the edges of the generated signal. 318 // 319 // Capture mode: 320 // When C2CFG.CCACT equals PER_PULSE_WIDTH_MEAS then VAL contains the width of 321 // the low or high phase of the selected signal. This is specified by 322 // C2CFG.EDGE. 323 #define LGPT3_PC2CCNC_VAL_W 24U 324 #define LGPT3_PC2CCNC_VAL_M 0x00FFFFFFU 325 326 //***************************************************************************** 327 // 328 // Register: LGPT3_O_TGTNC 329 // 330 //***************************************************************************** 331 // Field: [23:0] VAL 332 // 333 // User defined counter target value. 334 #define LGPT3_TGTNC_VAL_W 24U 335 #define LGPT3_TGTNC_VAL_M 0x00FFFFFFU 336 337 //***************************************************************************** 338 // 339 // Register: LGPT3_O_C0CCNC 340 // 341 //***************************************************************************** 342 // Field: [23:0] VAL 343 // 344 // Capture Compare value. 345 // 346 // User defined compare value or channel-updated capture value. 347 // 348 // A read or write to this register will not clear the RIS.C0CC interrupt. 349 // 350 // Compare mode: 351 // VAL is compared against CNTR.VAL and an event is generated as specified by 352 // C0CFG.CCACT when these are equal. 353 // 354 // Capture mode: 355 // The current counter value is stored in VAL when a capture event occurs. 356 // C0CFG.CCACT determines if VAL is a signal period or a regular capture value. 357 #define LGPT3_C0CCNC_VAL_W 24U 358 #define LGPT3_C0CCNC_VAL_M 0x00FFFFFFU 359 360 //***************************************************************************** 361 // 362 // Register: LGPT3_O_C1CCNC 363 // 364 //***************************************************************************** 365 // Field: [23:0] VAL 366 // 367 // Capture Compare value. 368 // 369 // User defined compare value or channel-updated capture value. 370 // 371 // A read or write to this register will not clear the RIS.C1CC interrupt. 372 // 373 // Compare mode: 374 // VAL is compared against CNTR.VAL and an event is generated as specified by 375 // C1CFG.CCACT when these are equal. 376 // 377 // Capture mode: 378 // The current counter value is stored in VAL when a capture event occurs. 379 // C1CFG.CCACT determines if VAL is a signal period or a regular capture value. 380 #define LGPT3_C1CCNC_VAL_W 24U 381 #define LGPT3_C1CCNC_VAL_M 0x00FFFFFFU 382 383 //***************************************************************************** 384 // 385 // Register: LGPT3_O_C2CCNC 386 // 387 //***************************************************************************** 388 // Field: [23:0] VAL 389 // 390 // Capture Compare value. 391 // 392 // User defined compare value or channel-updated capture value. 393 // 394 // A read or write to this register will not clear the RIS.C2CC interrupt. 395 // 396 // Compare mode: 397 // VAL is compared against CNTR.VAL and an event is generated as specified by 398 // C2CFG.CCACT when these are equal. 399 // 400 // Capture mode: 401 // The current counter value is stored in VAL when a capture event occurs. 402 // C2CFG.CCACT determines if VAL is a signal period or a regular capture value. 403 #define LGPT3_C2CCNC_VAL_W 24U 404 #define LGPT3_C2CCNC_VAL_M 0x00FFFFFFU 405 406 407 #endif // __LGPT3__ 408
