1 /****************************************************************************** 2 * Filename: hw_lgpt1_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_LGPT1_H__ 34 #define __HW_LGPT1_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // LGPT1 component 40 // 41 //***************************************************************************** 42 // Description Register. 43 // Description Extended 44 // Start Configuration 45 // Timer Control 46 // Output Control 47 // Counter 48 // Clock Prescaler Configuration 49 // Prescaler Event 50 // Channel Input Filter 51 // Fault 52 // Park 53 // Dead Band Delay 54 // Dead Band Control 55 // Direct Memory Accsess 56 // Direct Memory Access 57 // ADC Trigger 58 // IO Controller 59 // Interrupt mask. 60 // Raw interrupt status. 61 // Masked interrupt status. 62 // Interrupt set register. 63 // Interrupt clear register. 64 // Interrupt mask set register. 65 // Interrupt mask clear register. 66 // Debug control 67 // Channel 0 Configuration 68 // Channel 1 Configuration 69 // Channel 2 Configuration 70 // Pipeline Target 71 // Pipeline Channel 0 Capture Compare 72 // Pipeline Channel 1 Capture Compare 73 // Pipeline Channel 2 Capture Compare 74 // Target 75 // Channel 0 Capture Compare 76 // Channel 1 Capture Compare 77 // Channel 2 Capture Compare 78 // Pipeline Target No Clear 79 // Pipeline Channel 0 Capture Compare No Clear 80 // Pipeline Channel 1 Capture Compare No Clear 81 // Pipeline Channel 2 Capture Compare No Clear 82 // Target No Clear 83 // Channel 0 Capture Compare No Clear 84 // Channel 1 Capture Compare No Clear 85 // Channel 2 Capture Compare No Clear 86 #define LGPT1_O_FAULT 0x00000024U 87 #define LGPT1_O_PARK 0x00000028U 88 #define LGPT1_O_DBDLY 0x0000002CU 89 #define LGPT1_O_DBCTL 0x00000030U 90 91 //***************************************************************************** 92 // 93 // Register: LGPT1_O_FAULT 94 // 95 //***************************************************************************** 96 // Field: [1:0] CTL 97 // 98 // Fault control 99 // 100 // On active fault input the counter can optionally stop. If the counter stops 101 // this is done by hardware, software must then restart the timer if wanted. 102 // The fault input overrides channel 0 IOC input when CTL != DIS. 103 // This means that channel 0 receives fault as input signal when C0CFG.INPUT = 104 // IO and CTL != DIS. 105 // 106 // CHFILT can be used to avoid glitching on the fault input. Fault is level 107 // triggered, the polarity is set by the C0CFG.EDGE field. Here C0CFG.EDGE = 108 // RISE gives active high and C0CFG.EDGE = FALL gives active low polarity. 109 // 110 // Fault is typically used together with PARK to stop the PWM signal to an 111 // external motor control circuit safely. Configure PARK to ensure predefined 112 // values of the PWM outputs. 113 // 114 // If CTL != DIS the RIS.FAULT interrupt is set immediately when the fault 115 // input is active while CTL.MODE != DIS. 116 // 117 // The three modes of fault is described below: 118 // 119 // CTL = IMMEDIATE 120 // In this mode the counter stops immediately on an active fault input. This is 121 // done by hardware by setting CTL.MODE = DIS. To start the counter software 122 // must set CTL.MODE != DIS. 123 // When the counter has stopped, the input synchronizers and the channel filter 124 // is not running. This means that if RIS.FAULT is cleared it will not be set 125 // again while CTL.MODE = DIS. 126 // 127 // CTL = ZEROCOND 128 // In this mode the counter stops when CNTR = 0 after an active fault input. If 129 // the RIS.FAULT interrupt has been cleared by software before CNTR = 0, and 130 // the fault input is inactive, the counter will continue as normal. 131 // When the counter stops on zero, it can be started again by clearing the 132 // RIS.FAULT interrupt if the fault input is inactive. To change the counter 133 // mode set CTL.MODE = DIS, clear the RIS.FAULT interrupt, then start timer in 134 // wanted mode. 135 // 136 // CTL = IRQ 137 // In this mode only the RIS.FAULT flag is set on an active fault input. 138 // ENUMs: 139 // IRQ Interrupt request. Only set RIS.FAULT on active 140 // fault. 141 // ZERCOND Zero condition. The counter stops when CNTR = 0. 142 // IMMEDIATE Immediate reaction. The counter stops immediately 143 // on fault. 144 // DIS Disable. The timer ignores fault. 145 #define LGPT1_FAULT_CTL_W 2U 146 #define LGPT1_FAULT_CTL_M 0x00000003U 147 #define LGPT1_FAULT_CTL_S 0U 148 #define LGPT1_FAULT_CTL_IRQ 0x00000003U 149 #define LGPT1_FAULT_CTL_ZERCOND 0x00000002U 150 #define LGPT1_FAULT_CTL_IMMEDIATE 0x00000001U 151 #define LGPT1_FAULT_CTL_DIS 0x00000000U 152 153 //***************************************************************************** 154 // 155 // Register: LGPT1_O_PARK 156 // 157 //***************************************************************************** 158 // Field: [7] IOCPS2 159 // 160 // IO Complementary Park State 2 161 // 162 // Park state for IO Complementary output 2. 163 // ENUMs: 164 // HIGH Output is set high in park mode. 165 // LOW Output is set low in park mode. 166 // Field: [6] IOPS2 167 // 168 // IO Park State 2 169 // 170 // Park state for IO output 2. 171 // ENUMs: 172 // HIGH Output is set high in park mode. 173 // LOW Output is set low in park mode. 174 // Field: [5] IOCPS1 175 // 176 // IO Complementary Park State 1 177 // 178 // Park state for IO Complementary output 1. 179 // ENUMs: 180 // HIGH Output is set high in park mode. 181 // LOW Output is set low in park mode. 182 // Field: [4] IOPS1 183 // 184 // IO Park State 1 185 // 186 // Park state for IO output 1. 187 // ENUMs: 188 // HIGH Output is set high in park mode. 189 // LOW Output is set low in park mode. 190 // Field: [3] IOCPS0 191 // 192 // IO Complementary Park State 0 193 // 194 // Park state for IO Complementary output 0. 195 // ENUMs: 196 // HIGH Output is set high in park mode. 197 // LOW Output is set low in park mode. 198 // Field: [2] IOPS0 199 // 200 // IO Park State 0 201 // 202 // Park state for IO output 0. 203 // ENUMs: 204 // HIGH Output is set high in park mode. 205 // LOW Output is set low in park mode. 206 // Field: [1:0] CTL 207 // 208 // Park Control. 209 // ENUMs: 210 // BOTH Enter parkmode on fault or debug. 211 // DEBUG Enter park mode on debug. 212 // FAULT Enter park mode on fault. 213 // DIS Disable park mode. 214 #define LGPT1_PARK_IOCPS2 0x00000080U 215 #define LGPT1_PARK_IOCPS2_M 0x00000080U 216 #define LGPT1_PARK_IOCPS2_S 7U 217 #define LGPT1_PARK_IOCPS2_HIGH 0x00000080U 218 #define LGPT1_PARK_IOCPS2_LOW 0x00000000U 219 #define LGPT1_PARK_IOPS2 0x00000040U 220 #define LGPT1_PARK_IOPS2_M 0x00000040U 221 #define LGPT1_PARK_IOPS2_S 6U 222 #define LGPT1_PARK_IOPS2_HIGH 0x00000040U 223 #define LGPT1_PARK_IOPS2_LOW 0x00000000U 224 #define LGPT1_PARK_IOCPS1 0x00000020U 225 #define LGPT1_PARK_IOCPS1_M 0x00000020U 226 #define LGPT1_PARK_IOCPS1_S 5U 227 #define LGPT1_PARK_IOCPS1_HIGH 0x00000020U 228 #define LGPT1_PARK_IOCPS1_LOW 0x00000000U 229 #define LGPT1_PARK_IOPS1 0x00000010U 230 #define LGPT1_PARK_IOPS1_M 0x00000010U 231 #define LGPT1_PARK_IOPS1_S 4U 232 #define LGPT1_PARK_IOPS1_HIGH 0x00000010U 233 #define LGPT1_PARK_IOPS1_LOW 0x00000000U 234 #define LGPT1_PARK_IOCPS0 0x00000008U 235 #define LGPT1_PARK_IOCPS0_M 0x00000008U 236 #define LGPT1_PARK_IOCPS0_S 3U 237 #define LGPT1_PARK_IOCPS0_HIGH 0x00000008U 238 #define LGPT1_PARK_IOCPS0_LOW 0x00000000U 239 #define LGPT1_PARK_IOPS0 0x00000004U 240 #define LGPT1_PARK_IOPS0_M 0x00000004U 241 #define LGPT1_PARK_IOPS0_S 2U 242 #define LGPT1_PARK_IOPS0_HIGH 0x00000004U 243 #define LGPT1_PARK_IOPS0_LOW 0x00000000U 244 #define LGPT1_PARK_CTL_W 2U 245 #define LGPT1_PARK_CTL_M 0x00000003U 246 #define LGPT1_PARK_CTL_S 0U 247 #define LGPT1_PARK_CTL_BOTH 0x00000003U 248 #define LGPT1_PARK_CTL_DEBUG 0x00000002U 249 #define LGPT1_PARK_CTL_FAULT 0x00000001U 250 #define LGPT1_PARK_CTL_DIS 0x00000000U 251 252 //***************************************************************************** 253 // 254 // Register: LGPT1_O_DBDLY 255 // 256 //***************************************************************************** 257 // Field: [27:16] FALLDLY 258 // 259 // Fall delay. 260 // 261 // The number of system clock periods inserted between the fall of the dead 262 // band reference signal and the rise of the inverted output signal. 263 // Field: [11:0] RISEDLY 264 // 265 // Rise delay. 266 // 267 // The number of system clock periods inserted between the rise of the dead 268 // band reference signal and the rise of the output signal. 269 #define LGPT1_DBDLY_FALLDLY_W 12U 270 #define LGPT1_DBDLY_FALLDLY_M 0x0FFF0000U 271 #define LGPT1_DBDLY_FALLDLY_S 16U 272 #define LGPT1_DBDLY_RISEDLY_W 12U 273 #define LGPT1_DBDLY_RISEDLY_M 0x00000FFFU 274 #define LGPT1_DBDLY_RISEDLY_S 0U 275 276 //***************************************************************************** 277 // 278 // Register: LGPT1_O_DBCTL 279 // 280 //***************************************************************************** 281 // Field: [2] IO2 282 // 283 // Enable dead band on IO and IO complementary output 2. 284 // ENUMs: 285 // EN Enable 286 // DIS Disable 287 // Field: [1] IO1 288 // 289 // Enable dead band on IO and IO complementary output 1. 290 // ENUMs: 291 // EN Enable 292 // DIS Disable 293 // Field: [0] IO0 294 // 295 // Enable dead band on IO and IO complementary output 0. 296 // ENUMs: 297 // EN Enable 298 // DIS Disable 299 #define LGPT1_DBCTL_IO2 0x00000004U 300 #define LGPT1_DBCTL_IO2_M 0x00000004U 301 #define LGPT1_DBCTL_IO2_S 2U 302 #define LGPT1_DBCTL_IO2_EN 0x00000004U 303 #define LGPT1_DBCTL_IO2_DIS 0x00000000U 304 #define LGPT1_DBCTL_IO1 0x00000002U 305 #define LGPT1_DBCTL_IO1_M 0x00000002U 306 #define LGPT1_DBCTL_IO1_S 1U 307 #define LGPT1_DBCTL_IO1_EN 0x00000002U 308 #define LGPT1_DBCTL_IO1_DIS 0x00000000U 309 #define LGPT1_DBCTL_IO0 0x00000001U 310 #define LGPT1_DBCTL_IO0_M 0x00000001U 311 #define LGPT1_DBCTL_IO0_S 0U 312 #define LGPT1_DBCTL_IO0_EN 0x00000001U 313 #define LGPT1_DBCTL_IO0_DIS 0x00000000U 314 315 316 #endif // __LGPT1__ 317
