1 /****************************************************************************** 2 * Filename: hw_i2c_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_I2C_H__ 34 #define __HW_I2C_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // I2C component 40 // 41 //***************************************************************************** 42 // Target Own Address 43 #define I2C_O_TOAR 0x00000000U 44 45 // Target Control and Status 46 #define I2C_O_TSTA 0x00000004U 47 48 // Target control 49 #define I2C_O_TCTL 0x00000004U 50 51 // Target Data 52 #define I2C_O_TDR 0x00000008U 53 54 // Target Interrupt Mask 55 #define I2C_O_TIMR 0x0000000CU 56 57 // Target Raw Interrupt Status 58 #define I2C_O_TRIS 0x00000010U 59 60 // Target Masked Interrupt Status 61 #define I2C_O_TMIS 0x00000014U 62 63 // Target Interrupt Clear 64 #define I2C_O_TICR 0x00000018U 65 66 // Controller Target Address 67 #define I2C_O_CTA 0x00000800U 68 69 // Controller Control and Status 70 #define I2C_O_CSTA 0x00000804U 71 72 // Controller control 73 #define I2C_O_CCTL 0x00000804U 74 75 // Controller Data 76 #define I2C_O_CDR 0x00000808U 77 78 // Controller Timer Period 79 #define I2C_O_CTPR 0x0000080CU 80 81 // Controller Interrupt Mask 82 #define I2C_O_CIMR 0x00000810U 83 84 // Controller Raw Interrupt Status 85 #define I2C_O_CRIS 0x00000814U 86 87 // Controller Masked Interrupt Status 88 #define I2C_O_CMIS 0x00000818U 89 90 // Controller Interrupt Clear 91 #define I2C_O_CICR 0x0000081CU 92 93 // Controller Configuration 94 #define I2C_O_CCR 0x00000820U 95 96 //***************************************************************************** 97 // 98 // Register: I2C_O_TOAR 99 // 100 //***************************************************************************** 101 // Field: [6:0] OAR 102 // 103 // Target own address. This field specifies bits a6 through a0 of the target 104 // address. 105 #define I2C_TOAR_OAR_W 7U 106 #define I2C_TOAR_OAR_M 0x0000007FU 107 #define I2C_TOAR_OAR_S 0U 108 109 //***************************************************************************** 110 // 111 // Register: I2C_O_TSTA 112 // 113 //***************************************************************************** 114 // Field: [2] FBR 115 // 116 // First byte received. 117 // This bit is only applicable when the TSTA.RREQ bit is set and is 118 // automatically cleared when data has been read from the TDR register. 119 // Note: This bit is not used for target transmit operations. 120 // ENUMs: 121 // SET The first byte following the target's own address 122 // has been received. 123 // CLR The first byte following the target's own address 124 // has not been received 125 #define I2C_TSTA_FBR 0x00000004U 126 #define I2C_TSTA_FBR_M 0x00000004U 127 #define I2C_TSTA_FBR_S 2U 128 #define I2C_TSTA_FBR_SET 0x00000004U 129 #define I2C_TSTA_FBR_CLR 0x00000000U 130 131 // Field: [1] TREQ 132 // 133 // This field reflects the transmit request status 134 // ENUMs: 135 // SET The I2C has been addressed as a target transmitter 136 // and is using clock stretching to delay the 137 // controller until data has been written to the 138 // TDR register 139 // CLR No outstanding transmit request 140 #define I2C_TSTA_TREQ 0x00000002U 141 #define I2C_TSTA_TREQ_M 0x00000002U 142 #define I2C_TSTA_TREQ_S 1U 143 #define I2C_TSTA_TREQ_SET 0x00000002U 144 #define I2C_TSTA_TREQ_CLR 0x00000000U 145 146 // Field: [0] RREQ 147 // 148 // This field reflects the receive request status. 149 // ENUMs: 150 // SET The target has outstanding receive data from the 151 // external controller and is using clock 152 // stretching to delay the controller until data 153 // has been read from the TDR register 154 // CLR No outstanding receive data 155 #define I2C_TSTA_RREQ 0x00000001U 156 #define I2C_TSTA_RREQ_M 0x00000001U 157 #define I2C_TSTA_RREQ_S 0U 158 #define I2C_TSTA_RREQ_SET 0x00000001U 159 #define I2C_TSTA_RREQ_CLR 0x00000000U 160 161 //***************************************************************************** 162 // 163 // Register: I2C_O_TCTL 164 // 165 //***************************************************************************** 166 // Field: [0] DA 167 // 168 // This field sets the device active control 169 // ENUMs: 170 // EN Enable the target operation 171 // DIS Disable the target operation 172 #define I2C_TCTL_DA 0x00000001U 173 #define I2C_TCTL_DA_M 0x00000001U 174 #define I2C_TCTL_DA_S 0U 175 #define I2C_TCTL_DA_EN 0x00000001U 176 #define I2C_TCTL_DA_DIS 0x00000000U 177 178 //***************************************************************************** 179 // 180 // Register: I2C_O_TDR 181 // 182 //***************************************************************************** 183 // Field: [7:0] DATA 184 // 185 // Data for transfer. This field contains the data for transfer during a target 186 // receive or a transmit operation. When written, the register data is used as 187 // transmit data. When read, this register returns the last data received. Data 188 // is stored until next update, either by a system write to the controller for 189 // transmit or by an external controller to the target for receive. 190 #define I2C_TDR_DATA_W 8U 191 #define I2C_TDR_DATA_M 0x000000FFU 192 #define I2C_TDR_DATA_S 0U 193 194 //***************************************************************************** 195 // 196 // Register: I2C_O_TIMR 197 // 198 //***************************************************************************** 199 // Field: [2] STOPIM 200 // 201 // Stop condition interrupt mask 202 // ENUMs: 203 // EN Enable interrupt mask 204 // DIS Disable interrupt mask 205 #define I2C_TIMR_STOPIM 0x00000004U 206 #define I2C_TIMR_STOPIM_M 0x00000004U 207 #define I2C_TIMR_STOPIM_S 2U 208 #define I2C_TIMR_STOPIM_EN 0x00000004U 209 #define I2C_TIMR_STOPIM_DIS 0x00000000U 210 211 // Field: [1] STARTIM 212 // 213 // Start condition interrupt mask 214 // ENUMs: 215 // EN Enable interrupt mask 216 // DIS Disable interrupt mask 217 #define I2C_TIMR_STARTIM 0x00000002U 218 #define I2C_TIMR_STARTIM_M 0x00000002U 219 #define I2C_TIMR_STARTIM_S 1U 220 #define I2C_TIMR_STARTIM_EN 0x00000002U 221 #define I2C_TIMR_STARTIM_DIS 0x00000000U 222 223 // Field: [0] DATAIM 224 // 225 // Data interrupt mask 226 // ENUMs: 227 // EN Enable interrupt mask 228 // DIS Disable interrupt mask 229 #define I2C_TIMR_DATAIM 0x00000001U 230 #define I2C_TIMR_DATAIM_M 0x00000001U 231 #define I2C_TIMR_DATAIM_S 0U 232 #define I2C_TIMR_DATAIM_EN 0x00000001U 233 #define I2C_TIMR_DATAIM_DIS 0x00000000U 234 235 //***************************************************************************** 236 // 237 // Register: I2C_O_TRIS 238 // 239 //***************************************************************************** 240 // Field: [2] STOPRIS 241 // 242 // Stop condition raw interrupt status 243 // This bit is cleared by writing a 1 to TICR.STOPIC. 244 // ENUMs: 245 // SET Interrupt occured 246 // CLR Interrupt did not occur 247 #define I2C_TRIS_STOPRIS 0x00000004U 248 #define I2C_TRIS_STOPRIS_M 0x00000004U 249 #define I2C_TRIS_STOPRIS_S 2U 250 #define I2C_TRIS_STOPRIS_SET 0x00000004U 251 #define I2C_TRIS_STOPRIS_CLR 0x00000000U 252 253 // Field: [1] STARTRIS 254 // 255 // Start condition raw interrupt status 256 // This bit is cleared by writing a 1 to TICR.STARTIC. 257 // ENUMs: 258 // SET Interrupt occured 259 // CLR Interrupt did not occur 260 #define I2C_TRIS_STARTRIS 0x00000002U 261 #define I2C_TRIS_STARTRIS_M 0x00000002U 262 #define I2C_TRIS_STARTRIS_S 1U 263 #define I2C_TRIS_STARTRIS_SET 0x00000002U 264 #define I2C_TRIS_STARTRIS_CLR 0x00000000U 265 266 // Field: [0] DATARIS 267 // 268 // Data raw interrupt status 269 // This bit is cleared by writing a 1 to TICR.DATAIC. 270 // ENUMs: 271 // SET Interrupt occured 272 // CLR Interrupt did not occur 273 #define I2C_TRIS_DATARIS 0x00000001U 274 #define I2C_TRIS_DATARIS_M 0x00000001U 275 #define I2C_TRIS_DATARIS_S 0U 276 #define I2C_TRIS_DATARIS_SET 0x00000001U 277 #define I2C_TRIS_DATARIS_CLR 0x00000000U 278 279 //***************************************************************************** 280 // 281 // Register: I2C_O_TMIS 282 // 283 //***************************************************************************** 284 // Field: [2] STOPMIS 285 // 286 // Stop condition masked interrupt status 287 // This bit is cleared by writing a 1 to TICR.STOPIC. 288 // ENUMs: 289 // SET Masked interrupt occured 290 // CLR Masked interrupt did not occur 291 #define I2C_TMIS_STOPMIS 0x00000004U 292 #define I2C_TMIS_STOPMIS_M 0x00000004U 293 #define I2C_TMIS_STOPMIS_S 2U 294 #define I2C_TMIS_STOPMIS_SET 0x00000004U 295 #define I2C_TMIS_STOPMIS_CLR 0x00000000U 296 297 // Field: [1] STARTMIS 298 // 299 // Start condition masked interrupt status 300 // This bit is cleared by writing a 1 to TICR.STARTIC. 301 // ENUMs: 302 // SET Masked interrput occured 303 // CLR Masked interrupt did not occur 304 #define I2C_TMIS_STARTMIS 0x00000002U 305 #define I2C_TMIS_STARTMIS_M 0x00000002U 306 #define I2C_TMIS_STARTMIS_S 1U 307 #define I2C_TMIS_STARTMIS_SET 0x00000002U 308 #define I2C_TMIS_STARTMIS_CLR 0x00000000U 309 310 // Field: [0] DATAMIS 311 // 312 // Start condition masked interrupt status 313 // This bit is cleared by writing a 1 to TICR.DATAIC. 314 // ENUMs: 315 // SET Masked interrupt occured 316 // CLR Masked interrupt did not occur 317 #define I2C_TMIS_DATAMIS 0x00000001U 318 #define I2C_TMIS_DATAMIS_M 0x00000001U 319 #define I2C_TMIS_DATAMIS_S 0U 320 #define I2C_TMIS_DATAMIS_SET 0x00000001U 321 #define I2C_TMIS_DATAMIS_CLR 0x00000000U 322 323 //***************************************************************************** 324 // 325 // Register: I2C_O_TICR 326 // 327 //***************************************************************************** 328 // Field: [2] STOPIC 329 // 330 // Stop condition interrupt clear 331 // ENUMs: 332 // EN Clear interrupt 333 // Writing 1 to this bit 334 // clears TRIS.STOPRIS and TMIS.STOPMIS 335 // DIS No effect 336 #define I2C_TICR_STOPIC 0x00000004U 337 #define I2C_TICR_STOPIC_M 0x00000004U 338 #define I2C_TICR_STOPIC_S 2U 339 #define I2C_TICR_STOPIC_EN 0x00000004U 340 #define I2C_TICR_STOPIC_DIS 0x00000000U 341 342 // Field: [1] STARTIC 343 // 344 // Start condition interrupt clear 345 // ENUMs: 346 // EN Clear interrupt 347 // Writing 1 to this bit 348 // clears TRIS.STARTRIS and TMIS.STARTMIS 349 // DIS No effect 350 #define I2C_TICR_STARTIC 0x00000002U 351 #define I2C_TICR_STARTIC_M 0x00000002U 352 #define I2C_TICR_STARTIC_S 1U 353 #define I2C_TICR_STARTIC_EN 0x00000002U 354 #define I2C_TICR_STARTIC_DIS 0x00000000U 355 356 // Field: [0] DATAIC 357 // 358 // Data interrupt clear 359 // ENUMs: 360 // EN Clear interrupt 361 // Writing 1 to this bit 362 // clears TRIS.DATARIS and TMIS.DATAMIS 363 // DIS No effect 364 #define I2C_TICR_DATAIC 0x00000001U 365 #define I2C_TICR_DATAIC_M 0x00000001U 366 #define I2C_TICR_DATAIC_S 0U 367 #define I2C_TICR_DATAIC_EN 0x00000001U 368 #define I2C_TICR_DATAIC_DIS 0x00000000U 369 370 //***************************************************************************** 371 // 372 // Register: I2C_O_CTA 373 // 374 //***************************************************************************** 375 // Field: [7:1] SA 376 // 377 // Controller target address 378 // Defines which target is addressed for the transaction in controller mode 379 #define I2C_CTA_SA_W 7U 380 #define I2C_CTA_SA_M 0x000000FEU 381 #define I2C_CTA_SA_S 1U 382 383 // Field: [0] RS 384 // 385 // Receive or Send 386 // This bit-field specifies the next operation with addressed target CTA.SA. 387 // ENUMs: 388 // EN Receive data from target 389 // DIS Transmit/send data to target 390 #define I2C_CTA_RS 0x00000001U 391 #define I2C_CTA_RS_M 0x00000001U 392 #define I2C_CTA_RS_S 0U 393 #define I2C_CTA_RS_EN 0x00000001U 394 #define I2C_CTA_RS_DIS 0x00000000U 395 396 //***************************************************************************** 397 // 398 // Register: I2C_O_CSTA 399 // 400 //***************************************************************************** 401 // Field: [6] BUSBSY 402 // 403 // Bus busy 404 // Note:The bit changes based on the CCTRL.START and CCTRL.STOP conditions. 405 // ENUMs: 406 // SET The bus is busy. 407 // CLR The bus is idle. 408 #define I2C_CSTA_BUSBSY 0x00000040U 409 #define I2C_CSTA_BUSBSY_M 0x00000040U 410 #define I2C_CSTA_BUSBSY_S 6U 411 #define I2C_CSTA_BUSBSY_SET 0x00000040U 412 #define I2C_CSTA_BUSBSY_CLR 0x00000000U 413 414 // Field: [5] IDLE 415 // 416 // This field specifies whether I2C is idle or not 417 // ENUMs: 418 // SET The controller is idle. 419 // CLR The controller is not idle. 420 #define I2C_CSTA_IDLE 0x00000020U 421 #define I2C_CSTA_IDLE_M 0x00000020U 422 #define I2C_CSTA_IDLE_S 5U 423 #define I2C_CSTA_IDLE_SET 0x00000020U 424 #define I2C_CSTA_IDLE_CLR 0x00000000U 425 426 // Field: [4] ARBLST 427 // 428 // The filed specifies the arbitration status 429 // ENUMs: 430 // SET The controller lost arbitration. 431 // CLR The controller won arbitration. 432 #define I2C_CSTA_ARBLST 0x00000010U 433 #define I2C_CSTA_ARBLST_M 0x00000010U 434 #define I2C_CSTA_ARBLST_S 4U 435 #define I2C_CSTA_ARBLST_SET 0x00000010U 436 #define I2C_CSTA_ARBLST_CLR 0x00000000U 437 438 // Field: [3] DATACKN 439 // 440 // This field contains Data acknowledge status 441 // ENUMs: 442 // SET The transmitted data was not acknowledged 443 // CLR The transmitted data was acknowledged 444 #define I2C_CSTA_DATACKN 0x00000008U 445 #define I2C_CSTA_DATACKN_M 0x00000008U 446 #define I2C_CSTA_DATACKN_S 3U 447 #define I2C_CSTA_DATACKN_SET 0x00000008U 448 #define I2C_CSTA_DATACKN_CLR 0x00000000U 449 450 // Field: [2] ADRACKN 451 // 452 // This field reflects the address acknowledge status 453 // ENUMs: 454 // SET The transmitted address was not acknowledged 455 // CLR The transmitted address was acknowledged 456 #define I2C_CSTA_ADRACKN 0x00000004U 457 #define I2C_CSTA_ADRACKN_M 0x00000004U 458 #define I2C_CSTA_ADRACKN_S 2U 459 #define I2C_CSTA_ADRACKN_SET 0x00000004U 460 #define I2C_CSTA_ADRACKN_CLR 0x00000000U 461 462 // Field: [1] ERR 463 // 464 // This field reflects the error status 465 // ENUMs: 466 // SET An error occurred with the last operation 467 // CLR No error was detected on the last operation 468 #define I2C_CSTA_ERR 0x00000002U 469 #define I2C_CSTA_ERR_M 0x00000002U 470 #define I2C_CSTA_ERR_S 1U 471 #define I2C_CSTA_ERR_SET 0x00000002U 472 #define I2C_CSTA_ERR_CLR 0x00000000U 473 474 // Field: [0] BUSY 475 // 476 // This field reflects the I2C busy status 477 // Note: The I2C controller requires four CLKSVT clock cycles to assert the 478 // BUSY status after I2C controller operation has been initiated through a 479 // write into CCTL register. 480 // Hence after programming CCTL register, application is requested to wait for 481 // four CLKSVT clock cycles before issuing a controller status inquiry through 482 // a read from CSTA register. Any prior inquiry would result in wrong status 483 // being reported. 484 // ENUMs: 485 // SET The controller is busy 486 // CLR The controller is idle 487 #define I2C_CSTA_BUSY 0x00000001U 488 #define I2C_CSTA_BUSY_M 0x00000001U 489 #define I2C_CSTA_BUSY_S 0U 490 #define I2C_CSTA_BUSY_SET 0x00000001U 491 #define I2C_CSTA_BUSY_CLR 0x00000000U 492 493 //***************************************************************************** 494 // 495 // Register: I2C_O_CCTL 496 // 497 //***************************************************************************** 498 // Field: [3] ACK 499 // 500 // This field is to enable the data acknowledge. 501 // Note:This bit-field must be cleared when the I2C bus controller requires no 502 // further data to be transmitted from the target transmitter. 503 // ENUMs: 504 // EN The received data byte is acknowledged 505 // automatically by the controller 506 // DIS The received data byte is not acknowledged 507 // automatically by the controller 508 #define I2C_CCTL_ACK 0x00000008U 509 #define I2C_CCTL_ACK_M 0x00000008U 510 #define I2C_CCTL_ACK_S 3U 511 #define I2C_CCTL_ACK_EN 0x00000008U 512 #define I2C_CCTL_ACK_DIS 0x00000000U 513 514 // Field: [2] STOP 515 // 516 // This field is to set stop condition . 517 // Note: This bit-field determines if the cycle stops at the end of the data 518 // cycle or continues on to a repeated start condition. 519 // ENUMs: 520 // EN The controller generates the stop condition 521 // DIS The controller does not generate the stop 522 // condition 523 #define I2C_CCTL_STOP 0x00000004U 524 #define I2C_CCTL_STOP_M 0x00000004U 525 #define I2C_CCTL_STOP_S 2U 526 #define I2C_CCTL_STOP_EN 0x00000004U 527 #define I2C_CCTL_STOP_DIS 0x00000000U 528 529 // Field: [1] START 530 // 531 // This field is to set start or repeated start condition. 532 // ENUMs: 533 // EN The controller generates the start condition. 534 // DIS The controller does not generate the start 535 // condition 536 #define I2C_CCTL_START 0x00000002U 537 #define I2C_CCTL_START_M 0x00000002U 538 #define I2C_CCTL_START_S 1U 539 #define I2C_CCTL_START_EN 0x00000002U 540 #define I2C_CCTL_START_DIS 0x00000000U 541 542 // Field: [0] RUN 543 // 544 // This field is to set the controller enable. 545 // ENUMs: 546 // EN The controller is enabled to transmit or receive 547 // data 548 // DIS The controller is disabled. 549 #define I2C_CCTL_RUN 0x00000001U 550 #define I2C_CCTL_RUN_M 0x00000001U 551 #define I2C_CCTL_RUN_S 0U 552 #define I2C_CCTL_RUN_EN 0x00000001U 553 #define I2C_CCTL_RUN_DIS 0x00000000U 554 555 //***************************************************************************** 556 // 557 // Register: I2C_O_CDR 558 // 559 //***************************************************************************** 560 // Field: [7:0] DATA 561 // 562 // When Read: Last RX Data is returned 563 // When Written: Data is transferred during TX transaction 564 #define I2C_CDR_DATA_W 8U 565 #define I2C_CDR_DATA_M 0x000000FFU 566 #define I2C_CDR_DATA_S 0U 567 568 //***************************************************************************** 569 // 570 // Register: I2C_O_CTPR 571 // 572 //***************************************************************************** 573 // Field: [7] TPR_7 574 // 575 // Must be set to 0 to set CTPR.TPR. If set to 1, a write to CTPR.TPR will be 576 // ignored. 577 #define I2C_CTPR_TPR_7 0x00000080U 578 #define I2C_CTPR_TPR_7_M 0x00000080U 579 #define I2C_CTPR_TPR_7_S 7U 580 581 // Field: [6:0] TPR 582 // 583 // SCL clock period 584 // This field specifies the period of the SCL clock. 585 // SCL_PRD = 2*(1+TPR)*(SCL_LP + SCL_HP)*CLK_PRD, where: 586 // SCL_PRD is the SCL line period (I2C clock). 587 // TPR is the timer period register value (range of 1 to 127) 588 // SCL_LP is the SCL low period (fixed at 6). 589 // SCL_HP is the SCL high period (fixed at 4). 590 // CLK_PRD is the CLKSVT period in ns. 591 #define I2C_CTPR_TPR_W 7U 592 #define I2C_CTPR_TPR_M 0x0000007FU 593 #define I2C_CTPR_TPR_S 0U 594 595 //***************************************************************************** 596 // 597 // Register: I2C_O_CIMR 598 // 599 //***************************************************************************** 600 // Field: [0] IM 601 // 602 // Interrupt mask 603 // ENUMs: 604 // EN Enable interrupt mask 605 // DIS Disable interrupt mask 606 #define I2C_CIMR_IM 0x00000001U 607 #define I2C_CIMR_IM_M 0x00000001U 608 #define I2C_CIMR_IM_S 0U 609 #define I2C_CIMR_IM_EN 0x00000001U 610 #define I2C_CIMR_IM_DIS 0x00000000U 611 612 //***************************************************************************** 613 // 614 // Register: I2C_O_CRIS 615 // 616 //***************************************************************************** 617 // Field: [0] RIS 618 // 619 // Raw interrupt status 620 // This bit is cleared by writing 1 to CICR.IC bit. 621 // ENUMs: 622 // SET Interrupt occured 623 // CLR Interrupt did not occur 624 #define I2C_CRIS_RIS 0x00000001U 625 #define I2C_CRIS_RIS_M 0x00000001U 626 #define I2C_CRIS_RIS_S 0U 627 #define I2C_CRIS_RIS_SET 0x00000001U 628 #define I2C_CRIS_RIS_CLR 0x00000000U 629 630 //***************************************************************************** 631 // 632 // Register: I2C_O_CMIS 633 // 634 //***************************************************************************** 635 // Field: [0] MIS 636 // 637 // Masked interrupt status 638 // This bit is cleared by writing 1 to CICR.IC bit. 639 // ENUMs: 640 // SET Masked interrupt occured 641 // CLR Masked interrupt did not occur 642 #define I2C_CMIS_MIS 0x00000001U 643 #define I2C_CMIS_MIS_M 0x00000001U 644 #define I2C_CMIS_MIS_S 0U 645 #define I2C_CMIS_MIS_SET 0x00000001U 646 #define I2C_CMIS_MIS_CLR 0x00000000U 647 648 //***************************************************************************** 649 // 650 // Register: I2C_O_CICR 651 // 652 //***************************************************************************** 653 // Field: [0] IC 654 // 655 // Interrupt clear 656 // ENUMs: 657 // EN Clear Interrupt 658 // Writing 1 to this bit 659 // clears CRIS.RIS and CMIS.MIS. 660 // DIS No effect 661 #define I2C_CICR_IC 0x00000001U 662 #define I2C_CICR_IC_M 0x00000001U 663 #define I2C_CICR_IC_S 0U 664 #define I2C_CICR_IC_EN 0x00000001U 665 #define I2C_CICR_IC_DIS 0x00000000U 666 667 //***************************************************************************** 668 // 669 // Register: I2C_O_CCR 670 // 671 //***************************************************************************** 672 // Field: [5] TFE 673 // 674 // I2C target function enable 675 // 676 // ENUMs: 677 // EN Target mode enabled 678 // DIS Target mode disabled 679 #define I2C_CCR_TFE 0x00000020U 680 #define I2C_CCR_TFE_M 0x00000020U 681 #define I2C_CCR_TFE_S 5U 682 #define I2C_CCR_TFE_EN 0x00000020U 683 #define I2C_CCR_TFE_DIS 0x00000000U 684 685 // Field: [4] CFE 686 // 687 // I2C controller function enable 688 // ENUMs: 689 // EN Controller mode enabled 690 // DIS Controller mode disabled 691 #define I2C_CCR_CFE 0x00000010U 692 #define I2C_CCR_CFE_M 0x00000010U 693 #define I2C_CCR_CFE_S 4U 694 #define I2C_CCR_CFE_EN 0x00000010U 695 #define I2C_CCR_CFE_DIS 0x00000000U 696 697 // Field: [0] LPBK 698 // 699 // I2C loopback 700 // ENUMs: 701 // EN Test mode (Loopback operation) enabled 702 // DIS Test mode (Loopback operation) disabled 703 #define I2C_CCR_LPBK 0x00000001U 704 #define I2C_CCR_LPBK_M 0x00000001U 705 #define I2C_CCR_LPBK_S 0U 706 #define I2C_CCR_LPBK_EN 0x00000001U 707 #define I2C_CCR_LPBK_DIS 0x00000000U 708 709 710 #endif // __I2C__ 711
