1 /****************************************************************************** 2 * Filename: hw_dcb_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_DCB_H__ 34 #define __HW_DCB_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // DCB component 40 // 41 //***************************************************************************** 42 // Debug Fault Status Register 43 #define DCB_O_DFSR 0x00000000U 44 45 // Debug Halting Control and Status Register 46 #define DCB_O_DHCSR 0x000000C0U 47 48 // Debug Core Register Selector Register 49 #define DCB_O_DCRSR 0x000000C4U 50 51 // Debug Core Register Data Register 52 #define DCB_O_DCRDR 0x000000C8U 53 54 // Debug Exception and Monitor Control Register 55 #define DCB_O_DEMCR 0x000000CCU 56 57 //***************************************************************************** 58 // 59 // Register: DCB_O_DFSR 60 // 61 //***************************************************************************** 62 // Field: [4] EXTERNAL 63 // 64 // External debug request flag 65 // 0x0:No edbgrq external debug request occurred 66 // 0x1:Edbgrq has halted the core 67 #define DCB_DFSR_EXTERNAL 0x00000010U 68 #define DCB_DFSR_EXTERNAL_M 0x00000010U 69 #define DCB_DFSR_EXTERNAL_S 4U 70 71 // Field: [3] VCATCH 72 // 73 // Vector catch flag. When the VCATCH flag is set, a flag in the Debug 74 // Exception and Monitor Control Register is also set to indicate the type of 75 // vector catch. 76 // 0x0:No vector catch occurred 77 // 0x1:Vector catch occurred 78 #define DCB_DFSR_VCATCH 0x00000008U 79 #define DCB_DFSR_VCATCH_M 0x00000008U 80 #define DCB_DFSR_VCATCH_S 3U 81 82 // Field: [2] DWTRAP 83 // 84 // Data Watchpoint (DW) flag. 85 // 0x0:No dw match 86 // 0x1:Dw match 87 #define DCB_DFSR_DWTRAP 0x00000004U 88 #define DCB_DFSR_DWTRAP_M 0x00000004U 89 #define DCB_DFSR_DWTRAP_S 2U 90 91 // Field: [1] BKPT 92 // 93 // The BKPT flag is set by the execution of the BKPT instruction or on an 94 // instruction whose address triggered the breakpoint comparator match. When 95 // the processor has halted, the return PC points to the address of the 96 // breakpointed instruction. 97 // 0x0:No bkpt instruction or hardware breakpoint match 98 // 0x1:Bkpt instruction or hardware breakpoint match 99 #define DCB_DFSR_BKPT 0x00000002U 100 #define DCB_DFSR_BKPT_M 0x00000002U 101 #define DCB_DFSR_BKPT_S 1U 102 103 // Field: [0] HALTED 104 // 105 // Halt request flag 106 // 0x0:No halt request 107 // 0x1:Halt requested by dap access to c_halt or halted with c_step asserted 108 #define DCB_DFSR_HALTED 0x00000001U 109 #define DCB_DFSR_HALTED_M 0x00000001U 110 #define DCB_DFSR_HALTED_S 0U 111 112 //***************************************************************************** 113 // 114 // Register: DCB_O_DHCSR 115 // 116 //***************************************************************************** 117 // Field: [25] S_RESET_ST 118 // 119 // Indicates that the core has been reset, or is now being reset, since the 120 // last time this bit was read. This a sticky bit that clears on read. So, 121 // reading twice and getting 1 then 0 means it was reset in the past. Reading 122 // twice and getting 1 both times means that it is currently reset and held in 123 // reset. 124 #define DCB_DHCSR_S_RESET_ST 0x02000000U 125 #define DCB_DHCSR_S_RESET_ST_M 0x02000000U 126 #define DCB_DHCSR_S_RESET_ST_S 25U 127 128 // Field: [24] S_RETIRE_ST 129 // 130 // Core has retired at least part of an instruction since last read. This is a 131 // sticky bit that clears on read. 132 #define DCB_DHCSR_S_RETIRE_ST 0x01000000U 133 #define DCB_DHCSR_S_RETIRE_ST_M 0x01000000U 134 #define DCB_DHCSR_S_RETIRE_ST_S 24U 135 136 // Field: [17] S_HALT 137 // 138 // The core is halted in debug state only if S_HALT is set. 139 #define DCB_DHCSR_S_HALT 0x00020000U 140 #define DCB_DHCSR_S_HALT_M 0x00020000U 141 #define DCB_DHCSR_S_HALT_S 17U 142 143 // Field: [16] S_REGRDY 144 // 145 // Register Read/Write to the Debug Core Register Selector Register is 146 // available. Set in response to a successful register access. 147 #define DCB_DHCSR_S_REGRDY 0x00010000U 148 #define DCB_DHCSR_S_REGRDY_M 0x00010000U 149 #define DCB_DHCSR_S_REGRDY_S 16U 150 151 // Field: [3] C_MASKINTS 152 // 153 // When this bit is set and debug is enabled, external interrupts, SysTick, and 154 // PendSV are masked. Does not affect NMI, Hard Fault or SVCall. When C_DEBUGEN 155 // = 0, this bit has no effect. 156 #define DCB_DHCSR_C_MASKINTS 0x00000008U 157 #define DCB_DHCSR_C_MASKINTS_M 0x00000008U 158 #define DCB_DHCSR_C_MASKINTS_S 3U 159 160 // Field: [2] C_STEP 161 // 162 // Causes a debug event on any instruction or exception being executed, 163 // resulting in the core single stepping. 164 #define DCB_DHCSR_C_STEP 0x00000004U 165 #define DCB_DHCSR_C_STEP_M 0x00000004U 166 #define DCB_DHCSR_C_STEP_S 2U 167 168 // Field: [1] C_HALT 169 // 170 // Halts the core. This bit is set automatically when the core triggers a debug 171 // event, for example, on a breakpoint. This bit clears on core reset. When 172 // C_DEBUGEN = 0, this bit has no effect. 173 #define DCB_DHCSR_C_HALT 0x00000002U 174 #define DCB_DHCSR_C_HALT_M 0x00000002U 175 #define DCB_DHCSR_C_HALT_S 1U 176 177 // Field: [0] C_DEBUGEN 178 // 179 // Enables or disable debug 180 // ENUMs: 181 // DBG_EN Debug enabled 182 // DBG_DIS Debug disabled 183 #define DCB_DHCSR_C_DEBUGEN 0x00000001U 184 #define DCB_DHCSR_C_DEBUGEN_M 0x00000001U 185 #define DCB_DHCSR_C_DEBUGEN_S 0U 186 #define DCB_DHCSR_C_DEBUGEN_DBG_EN 0x00000001U 187 #define DCB_DHCSR_C_DEBUGEN_DBG_DIS 0x00000000U 188 189 //***************************************************************************** 190 // 191 // Register: DCB_O_DCRSR 192 // 193 //***************************************************************************** 194 // Field: [16] REGWnR 195 // 196 // Register Write-not-Read 197 // 0x0:Read 198 // 0x1:Write 199 #define DCB_DCRSR_REGWNR 0x00010000U 200 #define DCB_DCRSR_REGWNR_M 0x00010000U 201 #define DCB_DCRSR_REGWNR_S 16U 202 203 // Field: [4:0] REGSEL 204 // 205 // Select processor register 206 // 0x00:R0 207 // 0x01:R1 208 // 0x02:R2 209 // 0x03:R3 210 // 0x04:R4 211 // 0x05:R5 212 // 0x06:R6 213 // 0x07:R7 214 // 0x08:R8 215 // 0x09:R9 216 // 0x0a:R10 217 // 0x0b:R11 218 // 0x0c:R12 219 // 0x0d:Current sp 220 // 0x0e:Lr 221 // 0x0f:Debug Return Address 222 // 0x10:Xpsr flags, execution number, and state information 223 // 0x11:Msp (main sp) 224 // 0x12:Psp (process sp) 225 // 0x14:Control (dcrdr[25:24]), primask (dcrdr[0]) 226 #define DCB_DCRSR_REGSEL_W 5U 227 #define DCB_DCRSR_REGSEL_M 0x0000001FU 228 #define DCB_DCRSR_REGSEL_S 0U 229 230 //***************************************************************************** 231 // 232 // Register: DCB_O_DCRDR 233 // 234 //***************************************************************************** 235 // Field: [31:0] DBGTMP 236 // 237 // Data temporary cache, for reading and writing registers. 238 #define DCB_DCRDR_DBGTMP_W 32U 239 #define DCB_DCRDR_DBGTMP_M 0xFFFFFFFFU 240 #define DCB_DCRDR_DBGTMP_S 0U 241 242 //***************************************************************************** 243 // 244 // Register: DCB_O_DEMCR 245 // 246 //***************************************************************************** 247 // Field: [24] DWTENA 248 // 249 // Global enable or disable for the DW unit 250 // 0x0:Dw unit disabled. watchpoint cannot halt the core. the dw pcsr reads as 251 // oxffffffff. 252 // 0x1:Dw unit enabled 253 #define DCB_DEMCR_DWTENA 0x01000000U 254 #define DCB_DEMCR_DWTENA_M 0x01000000U 255 #define DCB_DEMCR_DWTENA_S 24U 256 257 // Field: [10] VC_HARDERR 258 // 259 // Debug trap on a Hard Fault 260 #define DCB_DEMCR_VC_HARDERR 0x00000400U 261 #define DCB_DEMCR_VC_HARDERR_M 0x00000400U 262 #define DCB_DEMCR_VC_HARDERR_S 10U 263 264 // Field: [0] VC_CORERESET 265 // 266 // Reset Vector Catch. Halt running system if HRESETn is asserted 267 #define DCB_DEMCR_VC_CORERESET 0x00000001U 268 #define DCB_DEMCR_VC_CORERESET_M 0x00000001U 269 #define DCB_DEMCR_VC_CORERESET_S 0U 270 271 272 #endif // __DCB__ 273
