1 /****************************************************************************** 2 * Filename: hw_dbgss_h 3 ****************************************************************************** 4 * Copyright (c) 2021 Texas Instruments Incorporated. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1) Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2) Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * 3) Neither the name of the copyright holder nor the names of its contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 ******************************************************************************/ 32 33 #ifndef __HW_DBGSS_H__ 34 #define __HW_DBGSS_H__ 35 36 //***************************************************************************** 37 // 38 // This section defines the register offsets of 39 // DBGSS component 40 // 41 //***************************************************************************** 42 // Module Description 43 #define DBGSS_O_DESC 0x00000000U 44 45 // Interrupt mask 46 #define DBGSS_O_IMASK 0x00000044U 47 48 // Raw interrupt status 49 #define DBGSS_O_RIS 0x0000004CU 50 51 // Masked interrupt status 52 #define DBGSS_O_MIS 0x00000054U 53 54 // Interrupt set 55 #define DBGSS_O_ISET 0x0000005CU 56 57 // Interrupt clear 58 #define DBGSS_O_ICLR 0x00000064U 59 60 // Set Interupt Mask in IMASK 61 #define DBGSS_O_IMSET 0x0000006CU 62 63 // Clear Interupt Mask in IMASK 64 #define DBGSS_O_IMCLR 0x00000074U 65 66 // Transmit data register 67 #define DBGSS_O_TXD 0x00000100U 68 69 // Transmit control register 70 #define DBGSS_O_TXCTL 0x00000104U 71 72 // Receive data register 73 #define DBGSS_O_RXD 0x00000108U 74 75 // Receive control register 76 #define DBGSS_O_RXCTL 0x0000010CU 77 78 // Transmit Data Peek Register 79 #define DBGSS_O_TXDPEEK 0x00000110U 80 81 // Receive Data Peek Register 82 #define DBGSS_O_RXDPEEK 0x00000114U 83 84 // Special enable authorization register 85 #define DBGSS_O_SPECIAL_AUTH 0x00000200U 86 87 // Special enable authorization set register 88 #define DBGSS_O_SPECIAL_AUTH_SET 0x00000204U 89 90 // Special enable authorization clear register 91 #define DBGSS_O_SPECIAL_AUTH_CLR 0x00000208U 92 93 // Application authorization register 94 #define DBGSS_O_APP_AUTH 0x00000210U 95 96 // Application authorization set register 97 #define DBGSS_O_APP_AUTH_SET 0x00000214U 98 99 // Application authorization clear register 100 #define DBGSS_O_APP_AUTH_CLR 0x00000218U 101 102 // Debug control register 103 #define DBGSS_O_DBGCTL 0x0000021CU 104 105 //***************************************************************************** 106 // 107 // Register: DBGSS_O_DESC 108 // 109 //***************************************************************************** 110 // Field: [31:16] MODULEID 111 // 112 // Module identifier used to uniquely identify this IP. 113 // ENUMs: 114 // MAX Maximum possible value 115 // MIN Minimum value 116 #define DBGSS_DESC_MODULEID_W 16U 117 #define DBGSS_DESC_MODULEID_M 0xFFFF0000U 118 #define DBGSS_DESC_MODULEID_S 16U 119 #define DBGSS_DESC_MODULEID_MAX 0xFFFF0000U 120 #define DBGSS_DESC_MODULEID_MIN 0x00000000U 121 122 // Field: [15:12] STDIPOFF 123 // 124 // Standard IP MMR block offset. Standard IP MMRs are the set of from 125 // aggregated IRQ registers till DTB. 126 // 127 // 0: Standard IP MMRs do not exist 128 // 129 // 0x1-0xF: Standard IP MMRs begin at offset of (64*STDIPOFF from the base IP 130 // address) 131 // 132 // 0: STDIP MMRs do not exist 133 // 0x1-0xF: These MMRs begin at offset 64*STDIPOFF from IP base address 134 // ENUMs: 135 // MAX Maximum possible value 136 // MIN Minimum Value 137 #define DBGSS_DESC_STDIPOFF_W 4U 138 #define DBGSS_DESC_STDIPOFF_M 0x0000F000U 139 #define DBGSS_DESC_STDIPOFF_S 12U 140 #define DBGSS_DESC_STDIPOFF_MAX 0x0000F000U 141 #define DBGSS_DESC_STDIPOFF_MIN 0x00000000U 142 143 // Field: [11:8] INSTIDX 144 // 145 // IP Instance ID number. If multiple instances of IP exist in the device, this 146 // field can identify the instance number (0-15). 147 // ENUMs: 148 // MAX Maximum possible value 149 // MIN Minimum Value 150 #define DBGSS_DESC_INSTIDX_W 4U 151 #define DBGSS_DESC_INSTIDX_M 0x00000F00U 152 #define DBGSS_DESC_INSTIDX_S 8U 153 #define DBGSS_DESC_INSTIDX_MAX 0x00000F00U 154 #define DBGSS_DESC_INSTIDX_MIN 0x00000000U 155 156 // Field: [7:4] MAJREV 157 // 158 // Major revision of IP (0-15). 159 // ENUMs: 160 // MAX Maximum possible value 161 // MIN Minimum Value 162 #define DBGSS_DESC_MAJREV_W 4U 163 #define DBGSS_DESC_MAJREV_M 0x000000F0U 164 #define DBGSS_DESC_MAJREV_S 4U 165 #define DBGSS_DESC_MAJREV_MAX 0x000000F0U 166 #define DBGSS_DESC_MAJREV_MIN 0x00000000U 167 168 // Field: [3:0] MINREV 169 // 170 // Minor revision of IP (0-15). 171 // ENUMs: 172 // MAX Maximum possible value 173 // MIN Minimum Value 174 #define DBGSS_DESC_MINREV_W 4U 175 #define DBGSS_DESC_MINREV_M 0x0000000FU 176 #define DBGSS_DESC_MINREV_S 0U 177 #define DBGSS_DESC_MINREV_MAX 0x0000000FU 178 #define DBGSS_DESC_MINREV_MIN 0x00000000U 179 180 //***************************************************************************** 181 // 182 // Register: DBGSS_O_IMASK 183 // 184 //***************************************************************************** 185 // Field: [3] PWRDWNIFG 186 // 187 // PWRDWNIFG interrupt mask 188 // ENUMs: 189 // SET Interrupt will request an interrupt service 190 // routine and corresponding bit in MIS will be 191 // set 192 // CLR Interrupt is masked out 193 #define DBGSS_IMASK_PWRDWNIFG 0x00000008U 194 #define DBGSS_IMASK_PWRDWNIFG_M 0x00000008U 195 #define DBGSS_IMASK_PWRDWNIFG_S 3U 196 #define DBGSS_IMASK_PWRDWNIFG_SET 0x00000008U 197 #define DBGSS_IMASK_PWRDWNIFG_CLR 0x00000000U 198 199 // Field: [2] PWRUPIFG 200 // 201 // PWRUPIFG interrupt mask 202 // ENUMs: 203 // SET Interrupt will request an interrupt service 204 // routine and corresponding bit in MIS will be 205 // set 206 // CLR Interrupt is masked out 207 #define DBGSS_IMASK_PWRUPIFG 0x00000004U 208 #define DBGSS_IMASK_PWRUPIFG_M 0x00000004U 209 #define DBGSS_IMASK_PWRUPIFG_S 2U 210 #define DBGSS_IMASK_PWRUPIFG_SET 0x00000004U 211 #define DBGSS_IMASK_PWRUPIFG_CLR 0x00000000U 212 213 // Field: [1] RXIFG 214 // 215 // RXIFG interrupt mask 216 // ENUMs: 217 // SET Interrupt will request an interrupt service 218 // routine and corresponding bit in MIS will be 219 // set 220 // CLR Interrupt is masked out 221 #define DBGSS_IMASK_RXIFG 0x00000002U 222 #define DBGSS_IMASK_RXIFG_M 0x00000002U 223 #define DBGSS_IMASK_RXIFG_S 1U 224 #define DBGSS_IMASK_RXIFG_SET 0x00000002U 225 #define DBGSS_IMASK_RXIFG_CLR 0x00000000U 226 227 // Field: [0] TXIFG 228 // 229 // TXIFG interrupt mask 230 // ENUMs: 231 // EN Enable Interrupt Mask 232 // DIS Disable Interrupt Mask 233 #define DBGSS_IMASK_TXIFG 0x00000001U 234 #define DBGSS_IMASK_TXIFG_M 0x00000001U 235 #define DBGSS_IMASK_TXIFG_S 0U 236 #define DBGSS_IMASK_TXIFG_EN 0x00000001U 237 #define DBGSS_IMASK_TXIFG_DIS 0x00000000U 238 239 //***************************************************************************** 240 // 241 // Register: DBGSS_O_RIS 242 // 243 //***************************************************************************** 244 // Field: [3] PWRDWNIFG 245 // 246 // Raw interrupt status for PWRDWNIFG 247 // ENUMs: 248 // SET PWRDWNIFG occurred 249 // CLR PWRDWNIFG did not occur 250 #define DBGSS_RIS_PWRDWNIFG 0x00000008U 251 #define DBGSS_RIS_PWRDWNIFG_M 0x00000008U 252 #define DBGSS_RIS_PWRDWNIFG_S 3U 253 #define DBGSS_RIS_PWRDWNIFG_SET 0x00000008U 254 #define DBGSS_RIS_PWRDWNIFG_CLR 0x00000000U 255 256 // Field: [2] PWRUPIFG 257 // 258 // Raw interrupt status for PWRUPIFG 259 // ENUMs: 260 // SET PWRUPIFG occurred 261 // CLR PWRUPIFG did not occur 262 #define DBGSS_RIS_PWRUPIFG 0x00000004U 263 #define DBGSS_RIS_PWRUPIFG_M 0x00000004U 264 #define DBGSS_RIS_PWRUPIFG_S 2U 265 #define DBGSS_RIS_PWRUPIFG_SET 0x00000004U 266 #define DBGSS_RIS_PWRUPIFG_CLR 0x00000000U 267 268 // Field: [1] RXIFG 269 // 270 // Raw interrupt status for RXIFG 271 // ENUMs: 272 // SET RXIFG occurred 273 // CLR RXIFG did not occur 274 #define DBGSS_RIS_RXIFG 0x00000002U 275 #define DBGSS_RIS_RXIFG_M 0x00000002U 276 #define DBGSS_RIS_RXIFG_S 1U 277 #define DBGSS_RIS_RXIFG_SET 0x00000002U 278 #define DBGSS_RIS_RXIFG_CLR 0x00000000U 279 280 // Field: [0] TXIFG 281 // 282 // Raw interrupt status for TXIFG 283 // ENUMs: 284 // SET TXIFG occurred 285 // CLR TXIFG did not occur 286 #define DBGSS_RIS_TXIFG 0x00000001U 287 #define DBGSS_RIS_TXIFG_M 0x00000001U 288 #define DBGSS_RIS_TXIFG_S 0U 289 #define DBGSS_RIS_TXIFG_SET 0x00000001U 290 #define DBGSS_RIS_TXIFG_CLR 0x00000000U 291 292 //***************************************************************************** 293 // 294 // Register: DBGSS_O_MIS 295 // 296 //***************************************************************************** 297 // Field: [3] PWRDWNIFG 298 // 299 // Masked interrupt status for PWRDWNIFG 300 // ENUMs: 301 // SET PWRDWNIFG requests an interrupt service routine 302 // CLR PWRDWNIFG did not request an interrupt service 303 // routine 304 #define DBGSS_MIS_PWRDWNIFG 0x00000008U 305 #define DBGSS_MIS_PWRDWNIFG_M 0x00000008U 306 #define DBGSS_MIS_PWRDWNIFG_S 3U 307 #define DBGSS_MIS_PWRDWNIFG_SET 0x00000008U 308 #define DBGSS_MIS_PWRDWNIFG_CLR 0x00000000U 309 310 // Field: [2] PWRUPIFG 311 // 312 // Masked interrupt status for PWRUPIFG 313 // ENUMs: 314 // SET PWRUPIFG requests an interrupt service routine 315 // CLR PWRUPIFG did not request an interrupt service 316 // routine 317 #define DBGSS_MIS_PWRUPIFG 0x00000004U 318 #define DBGSS_MIS_PWRUPIFG_M 0x00000004U 319 #define DBGSS_MIS_PWRUPIFG_S 2U 320 #define DBGSS_MIS_PWRUPIFG_SET 0x00000004U 321 #define DBGSS_MIS_PWRUPIFG_CLR 0x00000000U 322 323 // Field: [1] RXIFG 324 // 325 // Masked interrupt status for RXIFG 326 // ENUMs: 327 // SET RXIFG requests an interrupt service routine 328 // CLR RXIFG did not request an interrupt service routine 329 #define DBGSS_MIS_RXIFG 0x00000002U 330 #define DBGSS_MIS_RXIFG_M 0x00000002U 331 #define DBGSS_MIS_RXIFG_S 1U 332 #define DBGSS_MIS_RXIFG_SET 0x00000002U 333 #define DBGSS_MIS_RXIFG_CLR 0x00000000U 334 335 // Field: [0] TXIFG 336 // 337 // Masked interrupt status for TXIFG 338 // ENUMs: 339 // SET TXIFG requests an interrupt service routine 340 // CLR TXIFG did not request an interrupt service routine 341 #define DBGSS_MIS_TXIFG 0x00000001U 342 #define DBGSS_MIS_TXIFG_M 0x00000001U 343 #define DBGSS_MIS_TXIFG_S 0U 344 #define DBGSS_MIS_TXIFG_SET 0x00000001U 345 #define DBGSS_MIS_TXIFG_CLR 0x00000000U 346 347 //***************************************************************************** 348 // 349 // Register: DBGSS_O_ISET 350 // 351 //***************************************************************************** 352 // Field: [3] PWRDWNIFG 353 // 354 // Sets PWRDWNIFG in RIS register 355 // ENUMs: 356 // SET Set interrupt 357 // NOEFF Writing a 0 has no effect 358 #define DBGSS_ISET_PWRDWNIFG 0x00000008U 359 #define DBGSS_ISET_PWRDWNIFG_M 0x00000008U 360 #define DBGSS_ISET_PWRDWNIFG_S 3U 361 #define DBGSS_ISET_PWRDWNIFG_SET 0x00000008U 362 #define DBGSS_ISET_PWRDWNIFG_NOEFF 0x00000000U 363 364 // Field: [2] PWRUPIFG 365 // 366 // Sets PWRUPIFG in RIS register 367 // ENUMs: 368 // SET Set interrupt 369 // NOEFF Writing a 0 has no effect 370 #define DBGSS_ISET_PWRUPIFG 0x00000004U 371 #define DBGSS_ISET_PWRUPIFG_M 0x00000004U 372 #define DBGSS_ISET_PWRUPIFG_S 2U 373 #define DBGSS_ISET_PWRUPIFG_SET 0x00000004U 374 #define DBGSS_ISET_PWRUPIFG_NOEFF 0x00000000U 375 376 // Field: [1] RXIFG 377 // 378 // Sets RXIFG in RIS register 379 // ENUMs: 380 // SET Set interrupt 381 // NOEFF Writing a 0 has no effect 382 #define DBGSS_ISET_RXIFG 0x00000002U 383 #define DBGSS_ISET_RXIFG_M 0x00000002U 384 #define DBGSS_ISET_RXIFG_S 1U 385 #define DBGSS_ISET_RXIFG_SET 0x00000002U 386 #define DBGSS_ISET_RXIFG_NOEFF 0x00000000U 387 388 // Field: [0] TXIFG 389 // 390 // Sets TXIFG in RIS register 391 // ENUMs: 392 // SET Set interrupt 393 // NOEFF Writing a 0 has no effect 394 #define DBGSS_ISET_TXIFG 0x00000001U 395 #define DBGSS_ISET_TXIFG_M 0x00000001U 396 #define DBGSS_ISET_TXIFG_S 0U 397 #define DBGSS_ISET_TXIFG_SET 0x00000001U 398 #define DBGSS_ISET_TXIFG_NOEFF 0x00000000U 399 400 //***************************************************************************** 401 // 402 // Register: DBGSS_O_ICLR 403 // 404 //***************************************************************************** 405 // Field: [3] PWRDWNIFG 406 // 407 // Clears PWRDWNIFG interrupt 408 // ENUMs: 409 // CLR Clear interrupt 410 // NOEFF Writing a 0 has no effect 411 #define DBGSS_ICLR_PWRDWNIFG 0x00000008U 412 #define DBGSS_ICLR_PWRDWNIFG_M 0x00000008U 413 #define DBGSS_ICLR_PWRDWNIFG_S 3U 414 #define DBGSS_ICLR_PWRDWNIFG_CLR 0x00000008U 415 #define DBGSS_ICLR_PWRDWNIFG_NOEFF 0x00000000U 416 417 // Field: [2] PWRUPIFG 418 // 419 // Clears PWRUPIFG interrupt 420 // ENUMs: 421 // CLR Clear interrupt 422 // NOEFF Writing a 0 has no effect 423 #define DBGSS_ICLR_PWRUPIFG 0x00000004U 424 #define DBGSS_ICLR_PWRUPIFG_M 0x00000004U 425 #define DBGSS_ICLR_PWRUPIFG_S 2U 426 #define DBGSS_ICLR_PWRUPIFG_CLR 0x00000004U 427 #define DBGSS_ICLR_PWRUPIFG_NOEFF 0x00000000U 428 429 // Field: [1] RXIFG 430 // 431 // Clears RXIFG interrupt 432 // ENUMs: 433 // CLR Clear interrupt 434 // NOEFF Writing a 0 has no effect 435 #define DBGSS_ICLR_RXIFG 0x00000002U 436 #define DBGSS_ICLR_RXIFG_M 0x00000002U 437 #define DBGSS_ICLR_RXIFG_S 1U 438 #define DBGSS_ICLR_RXIFG_CLR 0x00000002U 439 #define DBGSS_ICLR_RXIFG_NOEFF 0x00000000U 440 441 // Field: [0] TXIFG 442 // 443 // Clears TXIFG interrupt 444 // ENUMs: 445 // CLR Clear interrupt 446 // NOEFF Writing a 0 has no effect 447 #define DBGSS_ICLR_TXIFG 0x00000001U 448 #define DBGSS_ICLR_TXIFG_M 0x00000001U 449 #define DBGSS_ICLR_TXIFG_S 0U 450 #define DBGSS_ICLR_TXIFG_CLR 0x00000001U 451 #define DBGSS_ICLR_TXIFG_NOEFF 0x00000000U 452 453 //***************************************************************************** 454 // 455 // Register: DBGSS_O_IMSET 456 // 457 //***************************************************************************** 458 // Field: [3] PWRDWNIFG 459 // 460 // Set PWRDWNIFG interrupt mask 461 // ENUMs: 462 // SET Set interrupt mask 463 // NOEFF Writing a 0 has no effect 464 #define DBGSS_IMSET_PWRDWNIFG 0x00000008U 465 #define DBGSS_IMSET_PWRDWNIFG_M 0x00000008U 466 #define DBGSS_IMSET_PWRDWNIFG_S 3U 467 #define DBGSS_IMSET_PWRDWNIFG_SET 0x00000008U 468 #define DBGSS_IMSET_PWRDWNIFG_NOEFF 0x00000000U 469 470 // Field: [2] PWRUPIFG 471 // 472 // Set PWRUPIFG interrupt mask 473 // ENUMs: 474 // SET Set interrupt mask 475 // NOEFF Writing a 0 has no effect 476 #define DBGSS_IMSET_PWRUPIFG 0x00000004U 477 #define DBGSS_IMSET_PWRUPIFG_M 0x00000004U 478 #define DBGSS_IMSET_PWRUPIFG_S 2U 479 #define DBGSS_IMSET_PWRUPIFG_SET 0x00000004U 480 #define DBGSS_IMSET_PWRUPIFG_NOEFF 0x00000000U 481 482 // Field: [1] RXIFG 483 // 484 // Set RXIFG interrupt mask 485 // ENUMs: 486 // SET Set interrupt mask 487 // NOEFF Writing a 0 has no effect 488 #define DBGSS_IMSET_RXIFG 0x00000002U 489 #define DBGSS_IMSET_RXIFG_M 0x00000002U 490 #define DBGSS_IMSET_RXIFG_S 1U 491 #define DBGSS_IMSET_RXIFG_SET 0x00000002U 492 #define DBGSS_IMSET_RXIFG_NOEFF 0x00000000U 493 494 // Field: [0] TXIFG 495 // 496 // Set TXIFG interrupt mask 497 // ENUMs: 498 // SET Set interrupt mask 499 // NOEFF Writing a 0 has no effect 500 #define DBGSS_IMSET_TXIFG 0x00000001U 501 #define DBGSS_IMSET_TXIFG_M 0x00000001U 502 #define DBGSS_IMSET_TXIFG_S 0U 503 #define DBGSS_IMSET_TXIFG_SET 0x00000001U 504 #define DBGSS_IMSET_TXIFG_NOEFF 0x00000000U 505 506 //***************************************************************************** 507 // 508 // Register: DBGSS_O_IMCLR 509 // 510 //***************************************************************************** 511 // Field: [3] PWRDWNIFG 512 // 513 // Clears PWRDWNIFG interrupt mask 514 // ENUMs: 515 // CLR IMASK bit corresponding to PWRDWNIFG is cleared 516 // NO_EFFECT Writing a 0 has no effect 517 #define DBGSS_IMCLR_PWRDWNIFG 0x00000008U 518 #define DBGSS_IMCLR_PWRDWNIFG_M 0x00000008U 519 #define DBGSS_IMCLR_PWRDWNIFG_S 3U 520 #define DBGSS_IMCLR_PWRDWNIFG_CLR 0x00000008U 521 #define DBGSS_IMCLR_PWRDWNIFG_NO_EFFECT 0x00000000U 522 523 // Field: [2] PWRUPIFG 524 // 525 // Clears PWRUPIFG interrupt mask 526 // ENUMs: 527 // CLR IMASK bit corresponding to PWRUPIFG is cleared 528 // NO_EFFECT Writing a 0 has no effect 529 #define DBGSS_IMCLR_PWRUPIFG 0x00000004U 530 #define DBGSS_IMCLR_PWRUPIFG_M 0x00000004U 531 #define DBGSS_IMCLR_PWRUPIFG_S 2U 532 #define DBGSS_IMCLR_PWRUPIFG_CLR 0x00000004U 533 #define DBGSS_IMCLR_PWRUPIFG_NO_EFFECT 0x00000000U 534 535 // Field: [1] RXIFG 536 // 537 // Clears RXIFG interrupt mask 538 // ENUMs: 539 // CLR IMASK bit corresponding to RXIFG is cleared 540 // NO_EFFECT Writing a 0 has no effect 541 #define DBGSS_IMCLR_RXIFG 0x00000002U 542 #define DBGSS_IMCLR_RXIFG_M 0x00000002U 543 #define DBGSS_IMCLR_RXIFG_S 1U 544 #define DBGSS_IMCLR_RXIFG_CLR 0x00000002U 545 #define DBGSS_IMCLR_RXIFG_NO_EFFECT 0x00000000U 546 547 // Field: [0] TXIFG 548 // 549 // Clears TXIFG interrupt mask 550 // ENUMs: 551 // CLR IMASK bit corresponding to TXIFG is cleared 552 // NO_EFFECT Writing a 0 has no effect 553 #define DBGSS_IMCLR_TXIFG 0x00000001U 554 #define DBGSS_IMCLR_TXIFG_M 0x00000001U 555 #define DBGSS_IMCLR_TXIFG_S 0U 556 #define DBGSS_IMCLR_TXIFG_CLR 0x00000001U 557 #define DBGSS_IMCLR_TXIFG_NO_EFFECT 0x00000000U 558 559 //***************************************************************************** 560 // 561 // Register: DBGSS_O_TXD 562 // 563 //***************************************************************************** 564 // Field: [31:0] VAL 565 // 566 // SACI command/parameter word. Valid value when TXCTL.TXDSTA=1. TXCTL.TXDSTA 567 // gets automatically cleared upon read. 568 #define DBGSS_TXD_VAL_W 32U 569 #define DBGSS_TXD_VAL_M 0xFFFFFFFFU 570 #define DBGSS_TXD_VAL_S 0U 571 572 //***************************************************************************** 573 // 574 // Register: DBGSS_O_TXCTL 575 // 576 //***************************************************************************** 577 // Field: [7:1] FLAGS 578 // 579 // Software defined flags that are used by the SACI protocol (host to device). 580 #define DBGSS_TXCTL_FLAGS_W 7U 581 #define DBGSS_TXCTL_FLAGS_M 0x000000FEU 582 #define DBGSS_TXCTL_FLAGS_S 1U 583 584 // Field: [0] TXDSTA 585 // 586 // Indicates whether the host has written a word to the TXD register, which can 587 // be read by the device: 588 // TXDSTA is automatically set upon write to TXD register in SECAP and 589 // automatically gets cleared upon read from TXD 590 // ENUMs: 591 // FULL The TXD register contains a new SACI parameter 592 // word from the host, which can be read by the 593 // device. 594 // EMPTY The TXD register does not contain a new SACI 595 // parameter word from the host, and should not be 596 // read by the device. 597 #define DBGSS_TXCTL_TXDSTA 0x00000001U 598 #define DBGSS_TXCTL_TXDSTA_M 0x00000001U 599 #define DBGSS_TXCTL_TXDSTA_S 0U 600 #define DBGSS_TXCTL_TXDSTA_FULL 0x00000001U 601 #define DBGSS_TXCTL_TXDSTA_EMPTY 0x00000000U 602 603 //***************************************************************************** 604 // 605 // Register: DBGSS_O_RXD 606 // 607 //***************************************************************************** 608 // Field: [31:0] VAL 609 // 610 // SACI command response word. RXCTL.RXDSTA automatically set upon write. 611 // RXCTL.RXDSTA automatically cleared upon read (flush operation). 612 #define DBGSS_RXD_VAL_W 32U 613 #define DBGSS_RXD_VAL_M 0xFFFFFFFFU 614 #define DBGSS_RXD_VAL_S 0U 615 616 //***************************************************************************** 617 // 618 // Register: DBGSS_O_RXCTL 619 // 620 //***************************************************************************** 621 // Field: [7:1] FLAGS 622 // 623 // Software defined flags that are used by the SACI protocol (device to host). 624 #define DBGSS_RXCTL_FLAGS_W 7U 625 #define DBGSS_RXCTL_FLAGS_M 0x000000FEU 626 #define DBGSS_RXCTL_FLAGS_S 1U 627 628 // Field: [0] RXDSTA 629 // 630 // Indicates whether the device has written a word to the RXD register, which 631 // can be read by the host: 632 // RXDSTA is automatically set upon write to RXD and automatically cleared upon 633 // read from RXD register of SECAP or RXD. 634 // ENUMs: 635 // FULL The RXD register contains a new SACI response word 636 // from the device, which can be read by the host. 637 // EMPTY The RXD register does not contain a new SACI 638 // response word from the device, and should not 639 // be read by the host. 640 #define DBGSS_RXCTL_RXDSTA 0x00000001U 641 #define DBGSS_RXCTL_RXDSTA_M 0x00000001U 642 #define DBGSS_RXCTL_RXDSTA_S 0U 643 #define DBGSS_RXCTL_RXDSTA_FULL 0x00000001U 644 #define DBGSS_RXCTL_RXDSTA_EMPTY 0x00000000U 645 646 //***************************************************************************** 647 // 648 // Register: DBGSS_O_TXDPEEK 649 // 650 //***************************************************************************** 651 // Field: [31:0] VAL 652 // 653 // Transmit Data Peek Register. SACI command parameter word. TXCTL.TXDSTA not 654 // affected by read of TXDPEEK 655 #define DBGSS_TXDPEEK_VAL_W 32U 656 #define DBGSS_TXDPEEK_VAL_M 0xFFFFFFFFU 657 #define DBGSS_TXDPEEK_VAL_S 0U 658 659 //***************************************************************************** 660 // 661 // Register: DBGSS_O_RXDPEEK 662 // 663 //***************************************************************************** 664 // Field: [31:0] VAL 665 // 666 // Receive Data Peek Register. SACI command response word. RXCTL.RXDSTA not 667 // affected by read of RXDPEEK 668 #define DBGSS_RXDPEEK_VAL_W 32U 669 #define DBGSS_RXDPEEK_VAL_M 0xFFFFFFFFU 670 #define DBGSS_RXDPEEK_VAL_S 0U 671 672 //***************************************************************************** 673 // 674 // Register: DBGSS_O_SPECIAL_AUTH 675 // 676 //***************************************************************************** 677 // Field: [6] DBGDIS 678 // 679 // Indicates status of DBGDIS. 680 // ENUMs: 681 // DIS Disables debugging capability 682 // EN Enables debugging capability. 683 #define DBGSS_SPECIAL_AUTH_DBGDIS 0x00000040U 684 #define DBGSS_SPECIAL_AUTH_DBGDIS_M 0x00000040U 685 #define DBGSS_SPECIAL_AUTH_DBGDIS_S 6U 686 #define DBGSS_SPECIAL_AUTH_DBGDIS_DIS 0x00000040U 687 #define DBGSS_SPECIAL_AUTH_DBGDIS_EN 0x00000000U 688 689 // Field: [5] AHBAPEN 690 // 691 // Indicates status of AHBAPEN 692 // ENUMs: 693 // EN Enable AHB-AP 694 // DIS Disable AHB-AP 695 #define DBGSS_SPECIAL_AUTH_AHBAPEN 0x00000020U 696 #define DBGSS_SPECIAL_AUTH_AHBAPEN_M 0x00000020U 697 #define DBGSS_SPECIAL_AUTH_AHBAPEN_S 5U 698 #define DBGSS_SPECIAL_AUTH_AHBAPEN_EN 0x00000020U 699 #define DBGSS_SPECIAL_AUTH_AHBAPEN_DIS 0x00000000U 700 701 // Field: [4] CFGAPEN 702 // 703 // Indicates status of CFGAPEN 704 // ENUMs: 705 // EN Enable CFG-AP 706 // DIS Disable CFG-AP 707 #define DBGSS_SPECIAL_AUTH_CFGAPEN 0x00000010U 708 #define DBGSS_SPECIAL_AUTH_CFGAPEN_M 0x00000010U 709 #define DBGSS_SPECIAL_AUTH_CFGAPEN_S 4U 710 #define DBGSS_SPECIAL_AUTH_CFGAPEN_EN 0x00000010U 711 #define DBGSS_SPECIAL_AUTH_CFGAPEN_DIS 0x00000000U 712 713 // Field: [2] DFTAPEN 714 // 715 // Indicates status of DFTAPEN 716 // ENUMs: 717 // EN Enable DFT-TAP 718 // DIS Disable DFT-TAP 719 #define DBGSS_SPECIAL_AUTH_DFTAPEN 0x00000004U 720 #define DBGSS_SPECIAL_AUTH_DFTAPEN_M 0x00000004U 721 #define DBGSS_SPECIAL_AUTH_DFTAPEN_S 2U 722 #define DBGSS_SPECIAL_AUTH_DFTAPEN_EN 0x00000004U 723 #define DBGSS_SPECIAL_AUTH_DFTAPEN_DIS 0x00000000U 724 725 // Field: [0] SECAPEN 726 // 727 // Indicates status of SECAP 728 // ENUMs: 729 // EN Enable SEC-AP 730 // DIS Disable SEC-AP 731 #define DBGSS_SPECIAL_AUTH_SECAPEN 0x00000001U 732 #define DBGSS_SPECIAL_AUTH_SECAPEN_M 0x00000001U 733 #define DBGSS_SPECIAL_AUTH_SECAPEN_S 0U 734 #define DBGSS_SPECIAL_AUTH_SECAPEN_EN 0x00000001U 735 #define DBGSS_SPECIAL_AUTH_SECAPEN_DIS 0x00000000U 736 737 //***************************************************************************** 738 // 739 // Register: DBGSS_O_SPECIAL_AUTH_SET 740 // 741 //***************************************************************************** 742 // Field: [31:24] KEY 743 // 744 // This field must be configured with 0xA5 in order to access this register. 745 // ENUMs: 746 // _to_unlock_w_ This field must be written with 0xA5 to be able to 747 // set any of the enable bits 748 #define DBGSS_SPECIAL_AUTH_SET_KEY_W 8U 749 #define DBGSS_SPECIAL_AUTH_SET_KEY_M 0xFF000000U 750 #define DBGSS_SPECIAL_AUTH_SET_KEY_S 24U 751 #define DBGSS_SPECIAL_AUTH_SET_KEY__TO_UNLOCK_W_ 0xA5000000U 752 753 // Field: [6] DBGDIS 754 // 755 // This bit sets DBGDIS in SPECIAL_AUTH register. 756 // ENUMs: 757 // SET SET DBGDIS 758 // NOEFF Writing 0 has no effect 759 #define DBGSS_SPECIAL_AUTH_SET_DBGDIS 0x00000040U 760 #define DBGSS_SPECIAL_AUTH_SET_DBGDIS_M 0x00000040U 761 #define DBGSS_SPECIAL_AUTH_SET_DBGDIS_S 6U 762 #define DBGSS_SPECIAL_AUTH_SET_DBGDIS_SET 0x00000040U 763 #define DBGSS_SPECIAL_AUTH_SET_DBGDIS_NOEFF 0x00000000U 764 765 // Field: [5] AHBAPEN 766 // 767 // This bit sets AHBAPEN in SPECIAL_AUTH register. 768 // ENUMs: 769 // SET SET AHB-AP 770 // NOEFF Writing 0 has no effect 771 #define DBGSS_SPECIAL_AUTH_SET_AHBAPEN 0x00000020U 772 #define DBGSS_SPECIAL_AUTH_SET_AHBAPEN_M 0x00000020U 773 #define DBGSS_SPECIAL_AUTH_SET_AHBAPEN_S 5U 774 #define DBGSS_SPECIAL_AUTH_SET_AHBAPEN_SET 0x00000020U 775 #define DBGSS_SPECIAL_AUTH_SET_AHBAPEN_NOEFF 0x00000000U 776 777 // Field: [4] CFGAPEN 778 // 779 // This bit sets CFGAPEN in SPECIAL_AUTH register. 780 // ENUMs: 781 // SET Set CFGAPEN 782 // NOEFF Writing 0 has no effect 783 #define DBGSS_SPECIAL_AUTH_SET_CFGAPEN 0x00000010U 784 #define DBGSS_SPECIAL_AUTH_SET_CFGAPEN_M 0x00000010U 785 #define DBGSS_SPECIAL_AUTH_SET_CFGAPEN_S 4U 786 #define DBGSS_SPECIAL_AUTH_SET_CFGAPEN_SET 0x00000010U 787 #define DBGSS_SPECIAL_AUTH_SET_CFGAPEN_NOEFF 0x00000000U 788 789 // Field: [2] DFTAPEN 790 // 791 // This bit sets DFTAPEN in SPECIAL_AUTH register. 792 // ENUMs: 793 // SET Set DFTAPEN 794 // NOEFF Writing 0 has no effect 795 #define DBGSS_SPECIAL_AUTH_SET_DFTAPEN 0x00000004U 796 #define DBGSS_SPECIAL_AUTH_SET_DFTAPEN_M 0x00000004U 797 #define DBGSS_SPECIAL_AUTH_SET_DFTAPEN_S 2U 798 #define DBGSS_SPECIAL_AUTH_SET_DFTAPEN_SET 0x00000004U 799 #define DBGSS_SPECIAL_AUTH_SET_DFTAPEN_NOEFF 0x00000000U 800 801 // Field: [0] SECAPEN 802 // 803 // This bit sets SECAPEN bit in SPECIAL_AUTH register. 804 // ENUMs: 805 // SET Set SECAPEN 806 // NOEFF Writing 0 has no effect 807 #define DBGSS_SPECIAL_AUTH_SET_SECAPEN 0x00000001U 808 #define DBGSS_SPECIAL_AUTH_SET_SECAPEN_M 0x00000001U 809 #define DBGSS_SPECIAL_AUTH_SET_SECAPEN_S 0U 810 #define DBGSS_SPECIAL_AUTH_SET_SECAPEN_SET 0x00000001U 811 #define DBGSS_SPECIAL_AUTH_SET_SECAPEN_NOEFF 0x00000000U 812 813 //***************************************************************************** 814 // 815 // Register: DBGSS_O_SPECIAL_AUTH_CLR 816 // 817 //***************************************************************************** 818 // Field: [31:24] KEY 819 // 820 // This field must be configured with 0x22 in order to access this register. 821 // ENUMs: 822 // _to_unlock_w_ This field must be written with 0x22 to be able to 823 // clear any of the enable bits 824 #define DBGSS_SPECIAL_AUTH_CLR_KEY_W 8U 825 #define DBGSS_SPECIAL_AUTH_CLR_KEY_M 0xFF000000U 826 #define DBGSS_SPECIAL_AUTH_CLR_KEY_S 24U 827 #define DBGSS_SPECIAL_AUTH_CLR_KEY__TO_UNLOCK_W_ 0x22000000U 828 829 // Field: [6] DBGDIS 830 // 831 // This bit clears DBGDIS in SPECIAL_AUTH register. 832 // ENUMs: 833 // CLR Clear DBGDIS 834 // NOEFF Writing 0 has no effect 835 #define DBGSS_SPECIAL_AUTH_CLR_DBGDIS 0x00000040U 836 #define DBGSS_SPECIAL_AUTH_CLR_DBGDIS_M 0x00000040U 837 #define DBGSS_SPECIAL_AUTH_CLR_DBGDIS_S 6U 838 #define DBGSS_SPECIAL_AUTH_CLR_DBGDIS_CLR 0x00000040U 839 #define DBGSS_SPECIAL_AUTH_CLR_DBGDIS_NOEFF 0x00000000U 840 841 // Field: [5] AHBAPEN 842 // 843 // This bit clears AHBAPEN in SPECIAL_AUTH register. 844 // ENUMs: 845 // CLR Clear AHBAPEN 846 // NOEFF Writing 0 has no effect 847 #define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN 0x00000020U 848 #define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN_M 0x00000020U 849 #define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN_S 5U 850 #define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN_CLR 0x00000020U 851 #define DBGSS_SPECIAL_AUTH_CLR_AHBAPEN_NOEFF 0x00000000U 852 853 // Field: [4] CFGAPEN 854 // 855 // This bit clears CFGAPEN in SPECIAL_AUTH register. 856 // ENUMs: 857 // CLR Clear CFGAPEN 858 // NOEFF Writing 0 has no effect 859 #define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN 0x00000010U 860 #define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN_M 0x00000010U 861 #define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN_S 4U 862 #define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN_CLR 0x00000010U 863 #define DBGSS_SPECIAL_AUTH_CLR_CFGAPEN_NOEFF 0x00000000U 864 865 // Field: [2] DFTAPEN 866 // 867 // This bit clears DFTAPEN in SPECIAL_AUTH register. 868 // ENUMs: 869 // CLR Clear DFTAPEN 870 // NOEFF Writing 0 has no effect 871 #define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN 0x00000004U 872 #define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN_M 0x00000004U 873 #define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN_S 2U 874 #define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN_CLR 0x00000004U 875 #define DBGSS_SPECIAL_AUTH_CLR_DFTAPEN_NOEFF 0x00000000U 876 877 // Field: [0] SECAPEN 878 // 879 // This bit clears SECAPEN in SPECIAL_AUTH register. 880 // ENUMs: 881 // CLR Clear SECAPEN 882 // NOEFF Writing 0 has no effect 883 #define DBGSS_SPECIAL_AUTH_CLR_SECAPEN 0x00000001U 884 #define DBGSS_SPECIAL_AUTH_CLR_SECAPEN_M 0x00000001U 885 #define DBGSS_SPECIAL_AUTH_CLR_SECAPEN_S 0U 886 #define DBGSS_SPECIAL_AUTH_CLR_SECAPEN_CLR 0x00000001U 887 #define DBGSS_SPECIAL_AUTH_CLR_SECAPEN_NOEFF 0x00000000U 888 889 //***************************************************************************** 890 // 891 // Register: DBGSS_O_APP_AUTH 892 // 893 //***************************************************************************** 894 // Field: [1] NIDEN 895 // 896 // Controls non-invasive debug enable. 897 // ENUMs: 898 // EN Non-invasive debug enabled 899 // DIS Non-invasive debug disabled 900 #define DBGSS_APP_AUTH_NIDEN 0x00000002U 901 #define DBGSS_APP_AUTH_NIDEN_M 0x00000002U 902 #define DBGSS_APP_AUTH_NIDEN_S 1U 903 #define DBGSS_APP_AUTH_NIDEN_EN 0x00000002U 904 #define DBGSS_APP_AUTH_NIDEN_DIS 0x00000000U 905 906 // Field: [0] DBGEN 907 // 908 // Controls invasive debug enable. 909 // ENUMs: 910 // EN Invasive debug enabled 911 // DIS Invasive debug disabled 912 #define DBGSS_APP_AUTH_DBGEN 0x00000001U 913 #define DBGSS_APP_AUTH_DBGEN_M 0x00000001U 914 #define DBGSS_APP_AUTH_DBGEN_S 0U 915 #define DBGSS_APP_AUTH_DBGEN_EN 0x00000001U 916 #define DBGSS_APP_AUTH_DBGEN_DIS 0x00000000U 917 918 //***************************************************************************** 919 // 920 // Register: DBGSS_O_APP_AUTH_SET 921 // 922 //***************************************************************************** 923 // Field: [31:24] KEY 924 // 925 // This field must be configured with 0x39 in order to access this register. 926 // ENUMs: 927 // _to_unlock_w_ Write this value 0x39 to unlock writing to the 928 // APP_AUTH_SET register 929 #define DBGSS_APP_AUTH_SET_KEY_W 8U 930 #define DBGSS_APP_AUTH_SET_KEY_M 0xFF000000U 931 #define DBGSS_APP_AUTH_SET_KEY_S 24U 932 #define DBGSS_APP_AUTH_SET_KEY__TO_UNLOCK_W_ 0x39000000U 933 934 // Field: [1] NIDEN 935 // 936 // Sets NIDEN bit in [APP_AUTH ]register. 937 // ENUMs: 938 // SET Sets NIDEN 939 // NOEFF Writing 0 has no effect 940 #define DBGSS_APP_AUTH_SET_NIDEN 0x00000002U 941 #define DBGSS_APP_AUTH_SET_NIDEN_M 0x00000002U 942 #define DBGSS_APP_AUTH_SET_NIDEN_S 1U 943 #define DBGSS_APP_AUTH_SET_NIDEN_SET 0x00000002U 944 #define DBGSS_APP_AUTH_SET_NIDEN_NOEFF 0x00000000U 945 946 // Field: [0] DBGEN 947 // 948 // Sets DBGEN bit in APP_AUTH register. 949 // ENUMs: 950 // SET Sets DBGEN 951 // NOEFF Writing 0 has no effect 952 #define DBGSS_APP_AUTH_SET_DBGEN 0x00000001U 953 #define DBGSS_APP_AUTH_SET_DBGEN_M 0x00000001U 954 #define DBGSS_APP_AUTH_SET_DBGEN_S 0U 955 #define DBGSS_APP_AUTH_SET_DBGEN_SET 0x00000001U 956 #define DBGSS_APP_AUTH_SET_DBGEN_NOEFF 0x00000000U 957 958 //***************************************************************************** 959 // 960 // Register: DBGSS_O_APP_AUTH_CLR 961 // 962 //***************************************************************************** 963 // Field: [31:24] KEY 964 // 965 // This field must be configured with 0x7D in order to access this register. 966 // ENUMs: 967 // _to_unlock_w_ Write this value 0x7D to unlock writing to the 968 // APP_AUTH_CLR register 969 #define DBGSS_APP_AUTH_CLR_KEY_W 8U 970 #define DBGSS_APP_AUTH_CLR_KEY_M 0xFF000000U 971 #define DBGSS_APP_AUTH_CLR_KEY_S 24U 972 #define DBGSS_APP_AUTH_CLR_KEY__TO_UNLOCK_W_ 0x7D000000U 973 974 // Field: [1] NIDEN 975 // 976 // Clears NIDEN bit in APP_AUTH register. 977 // ENUMs: 978 // CLR Clears NIDEN 979 // NOEFF Writing 0 has no effect 980 #define DBGSS_APP_AUTH_CLR_NIDEN 0x00000002U 981 #define DBGSS_APP_AUTH_CLR_NIDEN_M 0x00000002U 982 #define DBGSS_APP_AUTH_CLR_NIDEN_S 1U 983 #define DBGSS_APP_AUTH_CLR_NIDEN_CLR 0x00000002U 984 #define DBGSS_APP_AUTH_CLR_NIDEN_NOEFF 0x00000000U 985 986 // Field: [0] DBGEN 987 // 988 // Clears DBGEN bit in APP_AUTH register. 989 // ENUMs: 990 // CLR Clears DBGEN 991 // NOEFF Writing 0 has no effect 992 #define DBGSS_APP_AUTH_CLR_DBGEN 0x00000001U 993 #define DBGSS_APP_AUTH_CLR_DBGEN_M 0x00000001U 994 #define DBGSS_APP_AUTH_CLR_DBGEN_S 0U 995 #define DBGSS_APP_AUTH_CLR_DBGEN_CLR 0x00000001U 996 #define DBGSS_APP_AUTH_CLR_DBGEN_NOEFF 0x00000000U 997 998 //***************************************************************************** 999 // 1000 // Register: DBGSS_O_DBGCTL 1001 // 1002 //***************************************************************************** 1003 // Field: [5] SWDCEN 1004 // 1005 // This bit is used to enable connection between SWD pads and IceMelter (wakeup 1006 // circuit used for detecting debug probe) 1007 // ENUMs: 1008 // EN Connection enabled 1009 // DIS Connection disabled 1010 #define DBGSS_DBGCTL_SWDCEN 0x00000020U 1011 #define DBGSS_DBGCTL_SWDCEN_M 0x00000020U 1012 #define DBGSS_DBGCTL_SWDCEN_S 5U 1013 #define DBGSS_DBGCTL_SWDCEN_EN 0x00000020U 1014 #define DBGSS_DBGCTL_SWDCEN_DIS 0x00000000U 1015 1016 // Field: [4] DBGPWRUPACK 1017 // 1018 // This bit field specifies the status of dbgpwrupack from pmctl. 1019 // ENUMs: 1020 // EN dbgpwrupreq is acknowledged. 1021 // DIS dbgpwrupreq is not acknowledged 1022 #define DBGSS_DBGCTL_DBGPWRUPACK 0x00000010U 1023 #define DBGSS_DBGCTL_DBGPWRUPACK_M 0x00000010U 1024 #define DBGSS_DBGCTL_DBGPWRUPACK_S 4U 1025 #define DBGSS_DBGCTL_DBGPWRUPACK_EN 0x00000010U 1026 #define DBGSS_DBGCTL_DBGPWRUPACK_DIS 0x00000000U 1027 1028 // Field: [3] SYSPWRUPACK 1029 // 1030 // This bit field specify the status of syspwrupack from pmctl. 1031 // ENUMs: 1032 // EN syspwrupreq is acknowledged 1033 // DIS syspwrupreq is not acknowledged 1034 #define DBGSS_DBGCTL_SYSPWRUPACK 0x00000008U 1035 #define DBGSS_DBGCTL_SYSPWRUPACK_M 0x00000008U 1036 #define DBGSS_DBGCTL_SYSPWRUPACK_S 3U 1037 #define DBGSS_DBGCTL_SYSPWRUPACK_EN 0x00000008U 1038 #define DBGSS_DBGCTL_SYSPWRUPACK_DIS 0x00000000U 1039 1040 // Field: [2] JTAGSEL 1041 // 1042 // This bit field specifies the status of JTAG MODE for TEST TAP. 1043 // ENUMs: 1044 // EN TEST TAP enabled 1045 // DIS TEST TAP disabled 1046 #define DBGSS_DBGCTL_JTAGSEL 0x00000004U 1047 #define DBGSS_DBGCTL_JTAGSEL_M 0x00000004U 1048 #define DBGSS_DBGCTL_JTAGSEL_S 2U 1049 #define DBGSS_DBGCTL_JTAGSEL_EN 0x00000004U 1050 #define DBGSS_DBGCTL_JTAGSEL_DIS 0x00000000U 1051 1052 // Field: [1] SWDSEL 1053 // 1054 // This bit field specifies the status of SWD MODE for connection. 1055 // ENUMs: 1056 // EN debug connection enabled. 1057 // DIS debug connection disabled. 1058 #define DBGSS_DBGCTL_SWDSEL 0x00000002U 1059 #define DBGSS_DBGCTL_SWDSEL_M 0x00000002U 1060 #define DBGSS_DBGCTL_SWDSEL_S 1U 1061 #define DBGSS_DBGCTL_SWDSEL_EN 0x00000002U 1062 #define DBGSS_DBGCTL_SWDSEL_DIS 0x00000000U 1063 1064 // Field: [0] SWDOVR 1065 // 1066 // This bit is used for connecting to IO pads to SWCLK/IO on SW-DP through a 1067 // software request and establish SWD connection without IceMelter trigger for 1068 // debug purpose. 1069 // ENUMs: 1070 // DBGENA Force 1 or debug enable mode in which SWD 1071 // connection is established bypassing IceMelter 1072 // sequence 1073 // TRNSPRT Transparent mode in which SWD connection is 1074 // established via IceMelter Sequence. 1075 #define DBGSS_DBGCTL_SWDOVR 0x00000001U 1076 #define DBGSS_DBGCTL_SWDOVR_M 0x00000001U 1077 #define DBGSS_DBGCTL_SWDOVR_S 0U 1078 #define DBGSS_DBGCTL_SWDOVR_DBGENA 0x00000001U 1079 #define DBGSS_DBGCTL_SWDOVR_TRNSPRT 0x00000000U 1080 1081 1082 #endif // __DBGSS__ 1083
