1 // SETTINGS FOR PHY BASED ON RADIO CONTROL LAYER (SOURCE FILE) 2 // 3 // Usage Protocol stack 4 // 5 // 6 // CODE EXPORT INFORMATION 7 // This file is generated 8 // 9 // Tool name SmartRF Studio 8 10 // Tool version 0.6.0.327 INTERNAL 11 // 12 // 13 // WORKSPACE INFORMATION 14 // 15 // Workspace file srf_cli.workspace 16 // Device CC2340R5 17 // Package QFN40 5x5 RKP 18 // Revision(s) B (2.0) 19 // SDK SimpleLink LPF3 SDK 8.11.00.09 20 // Board LP-EM-CC2340R5 21 // PHY 2.4 GHz - Bluetooth 5, LE - 1 Mbps / 2 Mbps / Coded 22 // 23 // 24 // PHY PROPERTIES 25 // 26 // Run-time properties: 27 // Sub-PHY 1 Mbps 28 // Channel 17 (2440 MHz) 29 // TX output power 5.0 dBm 30 31 #include "rcl_settings_ble.h" 32 #include DeviceFamily_constructPath(rf_patches/lrf_pbe_binary_ble5.h) 33 #include DeviceFamily_constructPath(rf_patches/lrf_mce_binary_ble5.h) 34 #include DeviceFamily_constructPath(rf_patches/lrf_rfe_binary_ble5.h) 35 36 37 // Configuration: Common 38 static const uint32_t LRF_commonRegConfig[] = 39 { 40 0x0000003C, // Segment length = 60 41 0x0004A001, // Data structure 32-bit region (start byte position = 4, count = 2) 42 (uint32_t) &LRF_txPowerTable, // LRF_swParam : txPowerTable 43 (uint32_t) &(fcfg->appTrims), // LRF_swParam : trimDef 44 0x14502001, // HW 32-bit region (start address = 0x1450, count = 2) 45 0x22000000, // LRFDPBE.POLY0H LRFDPBE.POLY0L 46 0x00065B00, // LRFDPBE.POLY1H LRFDPBE.POLY1L 47 0x10B41004, // HW 16-bit region (start address = 0x10B4, count = 5) 48 0x00C40021, // LRFDPBE.FCFG1 LRFDPBE.FCFG0 49 0x00800086, // LRFDPBE.FCFG3 LRFDPBE.FCFG2 50 0x00000044, // - LRFDPBE.FCFG4 51 0x14682000, // HW 32-bit region (start address = 0x1468, count = 1) 52 0x00020004, // LRFDPBE.TXFWBTHRS LRFDPBE.RXFRBTHRS 53 0x10DC1001, // HW 16-bit region (start address = 0x10DC, count = 2) 54 0x0B0B0202, // LRFDPBE.TIMPRE LRFDPBE.TIMCTL 55 0x00003009, // HW sparse region (address/value pairs, count = 10) 56 0x20C00003, // LRFDMDM.ADCDIGCONF 57 0x20C8001F, // LRFDMDM.MODSYMMAP0 58 0x20E40001, // LRFDMDM.DEMMISC1 59 0x20F00000, // LRFDMDM.DEMIQMC0 60 0x20FC0000, // LRFDMDM.DEMFIDC0 61 0x30800000, // LRFDRFE.MAGNTHRCFG 62 0x30880000, // LRFDRFE.RSSIOFFSET 63 0x30A80000, // LRFDRFE.SPARE4 64 0x31201820, // LRFDRFE.MISC0 65 0x31300C07, // LRFDRFE.PHEDISC 66 0x246C2000, // HW 32-bit region (start address = 0x246C, count = 1) 67 0x0000000C, // LRFDMDM.MODMAIN LRFDMDM.BAUDPRE 68 0x30B41001, // HW 16-bit region (start address = 0x30B4, count = 2) 69 0x00000006, // LRFDRFE.PA0 LRFDRFE.IFAMPRFLDO 70 0x30C40005, // HW zero region (start address = 0x30C4, count = 6) 71 0x30E4100C, // HW 16-bit region (start address = 0x30E4, count = 13) 72 0x00000200, // LRFDRFE.DCO LRFDRFE.ATSTREFH 73 0x00000008, // LRFDRFE.DIVLDO LRFDRFE.DIV 74 0x00000000, // LRFDRFE.DCOLDO0 LRFDRFE.TDCLDO 75 0x07060000, // LRFDRFE.PRE0 LRFDRFE.DCOLDO1 76 0x06050000, // LRFDRFE.PRE2 LRFDRFE.PRE1 77 0x40080603, // LRFDRFE.CAL0 LRFDRFE.PRE3 78 0x00007F00, // - LRFDRFE.CAL1 79 0x31381002, // HW 16-bit region (start address = 0x3138, count = 3) 80 0x047FDF7F, // LRFDRFE.PLLMON1 LRFDRFE.PLLMON0 81 0x00001804, // - LRFDRFE.MOD0 82 0x202A5001, // RAM 16-bit region (start address = 0x202A, count = 2) 83 0x00B400B4, // PBE_BLE5_RAM.RECALTIMEOUT PBE_BLE5_RAM.SYNTHCALTIMEOUT 84 0x00007001, // RAM sparse region (address/value pairs, count = 2) 85 0x20320197, // PBE_BLE5_RAM.FIFOCFG 86 0x20360002, // PBE_BLE5_RAM.NAKHUB 87 0x68046005, // RAM 32-bit region (start address = 0x6804, count = 6) 88 0x03000012, // RFE_COMMON_RAM.TDCCAL0 RFE_COMMON_RAM.SYNTHCTL 89 0x00100000, // RFE_COMMON_RAM.TDCCAL2 RFE_COMMON_RAM.TDCCAL1 90 0x569B0400, // RFE_COMMON_RAM.K1LSB RFE_COMMON_RAM.TDCPLL 91 0x012D010A, // RFE_COMMON_RAM.K2BL RFE_COMMON_RAM.K1MSB 92 0x132C0034, // RFE_COMMON_RAM.K3BL RFE_COMMON_RAM.K2AL 93 0x916F07AB, // RFE_COMMON_RAM.K5 RFE_COMMON_RAM.K3AL 94 0x68206005, // RAM 32-bit region (start address = 0x6820, count = 6) 95 0x00000000, // RFE_COMMON_RAM.RTRIMMIN RFE_COMMON_RAM.RTRIMOFF 96 0x48080008, // RFE_COMMON_RAM.DIVF RFE_COMMON_RAM.DIVI 97 0x00000000, // RFE_COMMON_RAM.DIVLDOF RFE_COMMON_RAM.DIVLDOI 98 0x00470014, // RFE_COMMON_RAM.LDOSETTLE RFE_COMMON_RAM.DIVLDOIOFF 99 0x0005002E, // RFE_COMMON_RAM.DCOSETTLE RFE_COMMON_RAM.CHRGSETTLE 100 0x0000FE00 // RFE_COMMON_RAM.IFAMPRFLDODEFAULT RFE_COMMON_RAM.IFAMPRFLDOTX 101 }; 102 103 // Configuration: Sub-PHY = 1 Mbps, 2 Mbps 104 static const uint32_t LRF_subPhy1Mbps2MbpsRegConfig[] = 105 { 106 0x00024010, // Segment length = 16 107 0x00003004, // HW sparse region (address/value pairs, count = 5) 108 0x1098AAAA, // LRFDPBE.MDMCMDPAR2 109 0x20B80015, // LRFDMDM.SYSTIMEVTMUX0 110 0x20F48087, // LRFDMDM.DEMDSBU 111 0x2134005F, // LRFDMDM.DEMSWQU0 112 0x30A41F40, // LRFDRFE.SPARE3 113 0x21001008, // HW 16-bit region (start address = 0x2100, count = 9) 114 0x00040224, // LRFDMDM.DEMDSXB0 LRFDMDM.DEMFEXB0 115 0x04000005, // LRFDMDM.DEMMAFI0 LRFDMDM.DEMFIFE0 116 0x00C17B20, // LRFDMDM.DEMMAFI2 LRFDMDM.DEMMAFI1 117 0x7F27000F, // LRFDMDM.DEMC1BE1 LRFDMDM.DEMC1BE0 118 0x0000017F, // - LRFDMDM.DEMC1BE2 119 0x30B0B000, // HW masked region (mask/value pairs, count = 1) 120 0xFF0F000A, // LRFDRFE.LNA 121 0x68425001, // RAM 16-bit region (start address = 0x6842, count = 2) 122 0x00000045 // RFE_COMMON_RAM.AGCINFO RFE_COMMON_RAM.SPARE1SHADOW 123 }; 124 125 // Configuration: Sub-PHY = 1 Mbps, Coded 126 static const uint32_t LRF_subPhy1MbpsCodedRegConfig[] = 127 { 128 0x00014005, // Segment length = 5 129 0x0000A000, // Data structure 32-bit region (start byte position = 0, count = 1) 130 (uint32_t) &LRF_swConfig1Mbps, // LRF_swParam : swConfig 131 0x00003001, // HW sparse region (address/value pairs, count = 2) 132 0x20D44000, // LRFDMDM.BAUD 133 0x21240A18 // LRFDMDM.SPARE0 134 }; 135 136 // Configuration: Sub-PHY = 2 Mbps, Coded 137 static const uint32_t LRF_subPhy2MbpsCodedRegConfig[] = 138 { 139 0x00030002, // Segment length = 2 140 0x00007000, // RAM sparse region (address/value pairs, count = 1) 141 0x683E004C // RFE_COMMON_RAM.PHYRSSIOFFSET 142 }; 143 144 // Configuration: Sub-PHY = 1 Mbps 145 static const uint32_t LRF_subPhy1MbpsRegConfig[] = 146 { 147 0x0003400D, // Segment length = 13 148 0x00003002, // HW sparse region (address/value pairs, count = 3) 149 0x10908007, // LRFDPBE.MDMCMDPAR0 150 0x20F80F50, // LRFDMDM.DEMCODC0 151 0x30A0A246, // LRFDRFE.SPARE2 152 0x24742000, // HW 32-bit region (start address = 0x2474, count = 1) 153 0x118205F9, // LRFDMDM.DEMMISC3 LRFDMDM.DEMMISC2 154 0x00007000, // RAM sparse region (address/value pairs, count = 1) 155 0x20200000, // PBE_BLE5_RAM.PHY 156 0x20245002, // RAM 16-bit region (start address = 0x2024, count = 3) 157 0x01AE018E, // PBE_BLE5_RAM.PRERXIFS PBE_BLE5_RAM.PRETXIFS 158 0x00000226, // - PBE_BLE5_RAM.RXTIMEOUT 159 0x683E5001, // RAM 16-bit region (start address = 0x683E, count = 2) 160 0x75F80050 // RFE_COMMON_RAM.SPARE0SHADOW RFE_COMMON_RAM.PHYRSSIOFFSET 161 }; 162 163 // Configuration: Sub-PHY = 2 Mbps 164 static const uint32_t LRF_subPhy2MbpsRegConfig[] = 165 { 166 0x00010010, // Segment length = 16 167 0x0000A000, // Data structure 32-bit region (start byte position = 0, count = 1) 168 (uint32_t) &LRF_swConfig2Mbps, // LRF_swParam : swConfig 169 0x00003004, // HW sparse region (address/value pairs, count = 5) 170 0x1090800F, // LRFDPBE.MDMCMDPAR0 171 0x20D48000, // LRFDMDM.BAUD 172 0x20F80F70, // LRFDMDM.DEMCODC0 173 0x21240A2C, // LRFDMDM.SPARE0 174 0x30A0A357, // LRFDRFE.SPARE2 175 0x24742000, // HW 32-bit region (start address = 0x2474, count = 1) 176 0x108100F9, // LRFDMDM.DEMMISC3 LRFDMDM.DEMMISC2 177 0x00007001, // RAM sparse region (address/value pairs, count = 2) 178 0x20200001, // PBE_BLE5_RAM.PHY 179 0x684055FA, // RFE_COMMON_RAM.SPARE0SHADOW 180 0x20245002, // RAM 16-bit region (start address = 0x2024, count = 3) 181 0x018C01B2, // PBE_BLE5_RAM.PRERXIFS PBE_BLE5_RAM.PRETXIFS 182 0x000001C2 // - PBE_BLE5_RAM.RXTIMEOUT 183 }; 184 185 // Configuration: Sub-PHY = Coded 186 static const uint32_t LRF_subPhyCodedRegConfig[] = 187 { 188 0x00020019, // Segment length = 25 189 0x00003001, // HW sparse region (address/value pairs, count = 2) 190 0x10900097, // LRFDPBE.MDMCMDPAR0 191 0x10983C3C, // LRFDPBE.MDMCMDPAR2 192 0x24742000, // HW 32-bit region (start address = 0x2474, count = 1) 193 0x158210F9, // LRFDMDM.DEMMISC3 LRFDMDM.DEMMISC2 194 0x20F41001, // HW 16-bit region (start address = 0x20F4, count = 2) 195 0x06F0808D, // LRFDMDM.DEMCODC0 LRFDMDM.DEMDSBU 196 0x21001008, // HW 16-bit region (start address = 0x2100, count = 9) 197 0x00060A24, // LRFDMDM.DEMDSXB0 LRFDMDM.DEMFEXB0 198 0x0000000C, // LRFDMDM.DEMMAFI0 LRFDMDM.DEMFIFE0 199 0x00783C14, // LRFDMDM.DEMMAFI2 LRFDMDM.DEMMAFI1 200 0x7F7F001F, // LRFDMDM.DEMC1BE1 LRFDMDM.DEMC1BE0 201 0x0000014C, // - LRFDMDM.DEMC1BE2 202 0x30941001, // HW 16-bit region (start address = 0x3094, count = 2) 203 0x34F21307, // LRFDRFE.SPARE0 LRFDRFE.MAGNCTL1 204 0x34502000, // HW 32-bit region (start address = 0x3450, count = 1) 205 0x00B00013, // LRFDRFE.SPARE3 LRFDRFE.SPARE2 206 0x30B0B000, // HW masked region (mask/value pairs, count = 1) 207 0xFF0F000E, // LRFDRFE.LNA 208 0x20205004, // RAM 16-bit region (start address = 0x2020, count = 5) 209 0x01200003, // PBE_BLE5_RAM.PRETXIFS500K PBE_BLE5_RAM.PHY 210 0x012C0102, // PBE_BLE5_RAM.PRERXIFS PBE_BLE5_RAM.PRETXIFS 211 0x000007EA, // - PBE_BLE5_RAM.RXTIMEOUT 212 0x68425001, // RAM 16-bit region (start address = 0x6842, count = 2) 213 0x0001001C // RFE_COMMON_RAM.AGCINFO RFE_COMMON_RAM.SPARE1SHADOW 214 }; 215 216 // Configuration: Coded TX rate = S8 (8 symbols per bit = 125 kbps) 217 static const uint32_t LRF_codedTxRateS8RegConfig[] = 218 { 219 0x00044002, // Segment length = 2 220 0x00003000, // HW sparse region (address/value pairs, count = 1) 221 0x21280000 // LRFDMDM.SPARE1 222 }; 223 224 // Configuration: Coded TX rate = S2 (2 symbols per bit = 500 kbps) 225 static const uint32_t LRF_codedTxRateS2RegConfig[] = 226 { 227 0x00040002, // Segment length = 2 228 0x00003000, // HW sparse region (address/value pairs, count = 1) 229 0x21280001 // LRFDMDM.SPARE1 230 }; 231 232 233 // LRF register configuration list 234 static const LRF_RegConfigList LRF_regConfigList = { 235 .numEntries = 9, 236 .entries = { 237 (LRF_ConfigWord*) LRF_commonRegConfig, 238 (LRF_ConfigWord*) LRF_subPhy1Mbps2MbpsRegConfig, 239 (LRF_ConfigWord*) LRF_subPhy1MbpsCodedRegConfig, 240 (LRF_ConfigWord*) LRF_subPhy2MbpsCodedRegConfig, 241 (LRF_ConfigWord*) LRF_subPhy1MbpsRegConfig, 242 (LRF_ConfigWord*) LRF_subPhy2MbpsRegConfig, 243 (LRF_ConfigWord*) LRF_subPhyCodedRegConfig, 244 (LRF_ConfigWord*) LRF_codedTxRateS8RegConfig, 245 (LRF_ConfigWord*) LRF_codedTxRateS2RegConfig 246 } 247 }; 248 249 // LRF_TxShape data structure 250 const LRF_TxShape LRF_shapeBaseGfsk067 = { 251 .scale = 0x0FDE2, 252 .numCoeff = 0x0011, 253 .coeff = { 0x01, 0x02, 0x05, 0x0A, 0x14, 0x22, 0x37, 0x52, 0x71, 0x91, 0xB0, 0xCB, 0xE0, 0xEE, 0xF8, 0xFD, 0xFF } 254 }; 255 256 // LRF_TxShape data structure 257 const LRF_TxShape LRF_shapeBaseGfsk05 = { 258 .scale = 0x0F183, 259 .numCoeff = 0x0014, 260 .coeff = { 0x01, 0x02, 0x03, 0x06, 0x0A, 0x11, 0x1A, 0x27, 0x37, 0x4B, 0x62, 0x7B, 0x94, 0xAD, 0xC4, 0xD8, 0xE7, 0xF3, 0xFB, 0xFF } 261 }; 262 263 // LRF_SwConfig data structure 264 const LRF_SwConfig LRF_swConfig1Mbps = { 265 .rxIntFrequency = 1000000, 266 .rxFrequencyOffset = 0, 267 .txFrequencyOffset = 1000000, 268 .modFrequencyDeviation = 0x0003D090, 269 .txShape = &LRF_shapeBaseGfsk067, 270 .bwIndex = 0x00, 271 .bwIndexDither = 0x01 272 }; 273 274 // LRF_SwConfig data structure 275 const LRF_SwConfig LRF_swConfig2Mbps = { 276 .rxIntFrequency = 850000, 277 .rxFrequencyOffset = 0, 278 .txFrequencyOffset = 850000, 279 .modFrequencyDeviation = 0x0007A120, 280 .txShape = &LRF_shapeBaseGfsk05, 281 .bwIndex = 0x01, 282 .bwIndexDither = 0x01 283 }; 284 285 // LRF_TxPowerTable data structure 286 const LRF_TxPowerTable LRF_txPowerTable = { 287 .numEntries = 0x0000000E, 288 .powerTable = { 289 { .power = { .fraction = 0, .dBm = -20 }, .tempCoeff = 0, .value = { .reserved = 0, .ib = 18, .gain = 0, .mode = 0, .noIfampRfLdoBypass = 0 } }, 290 { .power = { .fraction = 0, .dBm = -16 }, .tempCoeff = 0, .value = { .reserved = 0, .ib = 20, .gain = 1, .mode = 0, .noIfampRfLdoBypass = 0 } }, 291 { .power = { .fraction = 0, .dBm = -12 }, .tempCoeff = 5, .value = { .reserved = 0, .ib = 17, .gain = 3, .mode = 0, .noIfampRfLdoBypass = 0 } }, 292 { .power = { .fraction = 0, .dBm = -8 }, .tempCoeff = 12, .value = { .reserved = 0, .ib = 17, .gain = 4, .mode = 0, .noIfampRfLdoBypass = 0 } }, 293 { .power = { .fraction = 0, .dBm = -4 }, .tempCoeff = 25, .value = { .reserved = 0, .ib = 17, .gain = 5, .mode = 0, .noIfampRfLdoBypass = 0 } }, 294 { .power = { .fraction = 0, .dBm = 0 }, .tempCoeff = 40, .value = { .reserved = 0, .ib = 19, .gain = 6, .mode = 0, .noIfampRfLdoBypass = 0 } }, 295 { .power = { .fraction = 0, .dBm = 1 }, .tempCoeff = 65, .value = { .reserved = 0, .ib = 30, .gain = 6, .mode = 0, .noIfampRfLdoBypass = 0 } }, 296 { .power = { .fraction = 0, .dBm = 2 }, .tempCoeff = 41, .value = { .reserved = 0, .ib = 39, .gain = 4, .mode = 1, .noIfampRfLdoBypass = 0 } }, 297 { .power = { .fraction = 0, .dBm = 3 }, .tempCoeff = 43, .value = { .reserved = 0, .ib = 31, .gain = 5, .mode = 1, .noIfampRfLdoBypass = 0 } }, 298 { .power = { .fraction = 0, .dBm = 4 }, .tempCoeff = 50, .value = { .reserved = 0, .ib = 37, .gain = 5, .mode = 1, .noIfampRfLdoBypass = 0 } }, 299 { .power = { .fraction = 0, .dBm = 5 }, .tempCoeff = 55, .value = { .reserved = 0, .ib = 27, .gain = 6, .mode = 1, .noIfampRfLdoBypass = 0 } }, 300 { .power = { .fraction = 0, .dBm = 6 }, .tempCoeff = 75, .value = { .reserved = 0, .ib = 38, .gain = 6, .mode = 1, .noIfampRfLdoBypass = 0 } }, 301 { .power = { .fraction = 0, .dBm = 7 }, .tempCoeff = 80, .value = { .reserved = 0, .ib = 25, .gain = 7, .mode = 1, .noIfampRfLdoBypass = 0 } }, 302 { .power = { .fraction = 0, .dBm = 8 }, .tempCoeff = 180, .value = { .reserved = 0, .ib = 63, .gain = 7, .mode = 1, .noIfampRfLdoBypass = 0 } } 303 } 304 }; 305 306 // LRF_Config data structure 307 const LRF_Config LRF_config = { 308 .pbeImage = (const LRF_TOPsmImage*) LRF_PBE_binary_ble5, 309 .mceImage = (const LRF_TOPsmImage*) LRF_MCE_binary_ble5, 310 .rfeImage = (const LRF_TOPsmImage*) LRF_RFE_binary_ble5, 311 .regConfigList = &LRF_regConfigList 312 }; 313
