1 // SETTINGS FOR PHY BASED ON RADIO CONTROL LAYER (HEADER FILE) 2 // 3 // 4 // CODE EXPORT INFORMATION 5 // This file is generated 6 // 7 // Tool name SmartRF Studio 8 8 // Tool version 0.6.0.327 INTERNAL 9 // Created 2024-05-28 13:53:16.066 10 // Computer swtools 11 // User - 12 // 13 // 14 // WORKSPACE INFORMATION 15 // 16 // Workspace file srf_cli.workspace 17 // Device CC2340R5 18 // Package QFN40 5x5 RKP 19 // Revision(s) B (2.0) 20 // SDK SimpleLink LPF3 SDK 8.11.00.09 21 // Board LP-EM-CC2340R5 22 // PHY ADC Noise 23 // PHY abbreviation adc_noise 24 // 25 // 26 // VALIDATION WARNINGS 27 // 28 // No warnings 29 30 #ifndef RCLSETTINGSADCNOISE_H 31 #define RCLSETTINGSADCNOISE_H 32 33 #include <ti/devices/DeviceFamily.h> 34 #include <ti/drivers/rcl/LRF.h> 35 #include DeviceFamily_constructPath(inc/hw_fcfg.h) 36 37 38 // LRF data structures 39 extern const LRF_SwConfig LRF_swConfigAdcNoise; 40 extern const LRF_Config LRF_configAdcNoise; 41 42 43 // COMMON register field values 44 45 // Address Module Register Bit(s) Field Value 46 // ----------------------------------------------------------------------------------- 47 // 0x3080 LRFDRFE MAGNTHRCFG [1] SEL 0x0 48 // 0x3088 LRFDRFE RSSIOFFSET [7:0] VAL <TRIM> 49 // 0x30A0 LRFDRFE SPARE2 [15:0] VAL 0xA246 50 // 0x30A4 LRFDRFE SPARE3 [15:0] VAL 0x1F40 51 // 0x30A8 LRFDRFE SPARE4 [15:0] VAL 0x0000 52 // 0x30B0 LRFDRFE LNA [7:4] TRIM <TRIM> 53 // 0x30B0 LRFDRFE LNA [3] BIAS 0x1 54 // 0x30B0 LRFDRFE LNA [2:1] IB 0x1 55 // 0x30B4 LRFDRFE IFAMPRFLDO [15:9] TRIM <TRIM> 56 // 0x30B4 LRFDRFE IFAMPRFLDO [7:4] AAFCAP <TRIM> 57 // 0x30B4 LRFDRFE IFAMPRFLDO [3:1] IFAMPIB 0x3 58 // 0x30B8 LRFDRFE PA0 [4:0] TRIM <TRIM> 59 // 0x30C4 LRFDRFE IFADC0 [14:12] DITHERTRIM <TRIM> 60 // 0x30C4 LRFDRFE IFADC0 [11:10] DITHEREN <TRIM> 61 // 0x30C4 LRFDRFE IFADC0 [7:4] INT2ADJ <TRIM> 62 // 0x30C4 LRFDRFE IFADC0 [3:2] AAFCAP <TRIM> 63 // 0x30C8 LRFDRFE IFADC1 [15] NRZ <TRIM> 64 // 0x30C8 LRFDRFE IFADC1 [14:9] TRIM <TRIM> 65 // 0x30CC LRFDRFE IFADCLF [15:12] FF3 <TRIM> 66 // 0x30CC LRFDRFE IFADCLF [11:8] FF2 <TRIM> 67 // 0x30CC LRFDRFE IFADCLF [7:4] FF1 <TRIM> 68 // 0x30CC LRFDRFE IFADCLF [3:0] INT3 <TRIM> 69 // 0x30D0 LRFDRFE IFADCQUANT [2:0] QUANTTHR <TRIM> 70 // 0x30D4 LRFDRFE IFADCALDO [13:8] TRIMOUT <TRIM> 71 // 0x30D8 LRFDRFE IFADCDLDO [13:8] TRIMOUT <TRIM> 72 // 0x30E4 LRFDRFE ATSTREFH [14:10] IREFTRIM <TRIM> 73 // 0x30E4 LRFDRFE ATSTREFH [9] BIAS 0x1 74 // 0x30E8 LRFDRFE DCO [6:3] TAILRESTRIM <TRIM> 75 // 0x30E8 LRFDRFE DCO [0] CRSCAPCM 0x0 76 // 0x30EC LRFDRFE DIV [15] PDET 0x0 77 // 0x30EC LRFDRFE DIV [14:12] NMIREFTRIM 0x0 78 // 0x30EC LRFDRFE DIV [11:9] PMIREFTRIM 0x0 79 // 0x30EC LRFDRFE DIV [8] TXBBOOST 0x0 80 // 0x30EC LRFDRFE DIV [7] S1GFRC 0x0 81 // 0x30EC LRFDRFE DIV [6:5] BUFGAIN 0x0 82 // 0x30EC LRFDRFE DIV [4] BIAS 0x0 83 // 0x30EC LRFDRFE DIV [3] OUT 0x1 84 // 0x30EC LRFDRFE DIV [2:0] RATIO 0x0 85 // 0x30F0 LRFDRFE DIVLDO [15] SPARE15 0x0 86 // 0x30F0 LRFDRFE DIVLDO [14:8] VOUTTRIM <TRIM> 87 // 0x30F0 LRFDRFE DIVLDO [7] ITST 0x0 88 // 0x30F0 LRFDRFE DIVLDO [6:4] TMUX 0x0 89 // 0x30F0 LRFDRFE DIVLDO [3] SPARE3 0x0 90 // 0x30F0 LRFDRFE DIVLDO [2] MODE 0x0 91 // 0x30F0 LRFDRFE DIVLDO [1] BYPASS 0x0 92 // 0x30F0 LRFDRFE DIVLDO [0] CTL 0x0 93 // 0x30F4 LRFDRFE TDCLDO [14:8] VOUTTRIM <TRIM> 94 // 0x30F8 LRFDRFE DCOLDO0 [13:8] SECONDTRIM <TRIM> 95 // 0x30F8 LRFDRFE DCOLDO0 [7:4] FIRSTTRIM <TRIM> 96 // 0x30FC LRFDRFE DCOLDO1 [10] REFSRC 0x0 97 // 0x30FC LRFDRFE DCOLDO1 [9:8] DIVATST 0x0 98 // 0x3100 LRFDRFE PRE0 [13:8] PLLDIV1 0x07 99 // 0x3100 LRFDRFE PRE0 [5:0] PLLDIV0 0x06 100 // 0x3104 LRFDRFE PRE1 [5:0] HSDDC 0x00 101 // 0x3108 LRFDRFE PRE2 [15:12] MIDCALDIVLSB 0x0 102 // 0x3108 LRFDRFE PRE2 [11:6] CRSCALDIV 0x18 103 // 0x3108 LRFDRFE PRE2 [5:0] FSMDIV 0x05 104 // 0x310C LRFDRFE PRE3 [15:5] FINECALDIV 0x030 105 // 0x310C LRFDRFE PRE3 [4:0] MIDCALDIVMSB 0x03 106 // 0x3110 LRFDRFE CAL0 [14:8] FCSTART 0x40 107 // 0x3110 LRFDRFE CAL0 [3:2] TDCAVG 0x2 108 // 0x3114 LRFDRFE CAL1 [14:8] FCTOP 0x7F 109 // 0x3114 LRFDRFE CAL1 [6:0] FCBOT 0x00 110 // 0x3120 LRFDRFE MISC0 [13] PHCPT 0x0 111 // 0x3120 LRFDRFE MISC0 [12] TDCCALCORR 0x1 112 // 0x3120 LRFDRFE MISC0 [11] TDCMSBCORR 0x1 113 // 0x3120 LRFDRFE MISC0 [5:4] DLYCANCRS 0x2 114 // 0x3130 LRFDRFE PHEDISC [13:10] CNT 0x3 115 // 0x3130 LRFDRFE PHEDISC [9:0] THR 0x007 116 // 0x3138 LRFDRFE PLLMON0 [15:14] PHELOLCNT 0x3 117 // 0x3138 LRFDRFE PLLMON0 [13:8] PHELOLTHR 0x1F 118 // 0x3138 LRFDRFE PLLMON0 [6:0] FCTHR 0x7F 119 // 0x313C LRFDRFE PLLMON1 [12:8] PHELOCKCNT 0x04 120 // 0x313C LRFDRFE PLLMON1 [7:0] PHELOCKTHR 0x7F 121 // 0x3140 LRFDRFE MOD0 [12:11] SCHEME 0x3 122 // 0x3140 LRFDRFE MOD0 [10:8] SYMSHP 0x0 123 // 0x3140 LRFDRFE MOD0 [3:2] INTPFACT 0x1 124 // 0x6804 RFE_COMMON_RAM SYNTHCTL [7] CHRGFILT 0x0 125 // 0x6804 RFE_COMMON_RAM SYNTHCTL [6] VREFBP 0x0 126 // 0x6804 RFE_COMMON_RAM SYNTHCTL [5] TXWAITMOD 0x0 127 // 0x6804 RFE_COMMON_RAM SYNTHCTL [4] PHEDISC 0x1 128 // 0x6804 RFE_COMMON_RAM SYNTHCTL [3] RTRIMTST 0x0 129 // 0x6804 RFE_COMMON_RAM SYNTHCTL [2] IIR 0x0 130 // 0x6804 RFE_COMMON_RAM SYNTHCTL [1] REFDTHR 0x1 131 // 0x6804 RFE_COMMON_RAM SYNTHCTL [0] FCDEM 0x0 132 // 0x6806 RFE_COMMON_RAM TDCCAL0 [10:8] STOP 0x3 133 // 0x6808 RFE_COMMON_RAM TDCCAL1 [7:0] SUB 0x00 134 // 0x680A RFE_COMMON_RAM TDCCAL2 [5:0] AVG 0x10 135 // 0x680C RFE_COMMON_RAM TDCPLL [10:8] STOP 0x4 136 // 0x680E RFE_COMMON_RAM K1LSB [15:0] VAL 0x569B 137 // 0x6810 RFE_COMMON_RAM K1MSB [15:0] VAL 0x010A 138 // 0x6812 RFE_COMMON_RAM K2BL [15] HPM 0x0 139 // 0x6812 RFE_COMMON_RAM K2BL [14:0] VAL 0x012D 140 // 0x6814 RFE_COMMON_RAM K2AL [15] HPM 0x0 141 // 0x6814 RFE_COMMON_RAM K2AL [14:0] VAL 0x0034 142 // 0x6816 RFE_COMMON_RAM K3BL [15:0] VAL 0x132C 143 // 0x6818 RFE_COMMON_RAM K3AL [15:0] VAL 0x07AB 144 // 0x681A RFE_COMMON_RAM K5 [15:0] VAL 0x916F 145 // 0x6820 RFE_COMMON_RAM RTRIMOFF [3:0] VAL 0x0 146 // 0x6822 RFE_COMMON_RAM RTRIMMIN [3:0] VAL 0x0 147 // 0x6824 RFE_COMMON_RAM DIVI [15] PDET 0x0 148 // 0x6824 RFE_COMMON_RAM DIVI [14:12] NMIREFTRIM 0x0 149 // 0x6824 RFE_COMMON_RAM DIVI [11:9] PMIREFTRIM 0x0 150 // 0x6824 RFE_COMMON_RAM DIVI [8] TXBOOST 0x0 151 // 0x6824 RFE_COMMON_RAM DIVI [7] S1GFRC 0x0 152 // 0x6824 RFE_COMMON_RAM DIVI [6:5] BUFGAIN 0x0 153 // 0x6824 RFE_COMMON_RAM DIVI [4] BIAS 0x0 154 // 0x6824 RFE_COMMON_RAM DIVI [3] OUT 0x1 155 // 0x6824 RFE_COMMON_RAM DIVI [2:0] RATIO 0x0 156 // 0x6826 RFE_COMMON_RAM DIVF [15] PDET 0x0 157 // 0x6826 RFE_COMMON_RAM DIVF [14:12] NMIREFTRIM 0x4 158 // 0x6826 RFE_COMMON_RAM DIVF [11:9] PMIREFTRIM 0x4 159 // 0x6826 RFE_COMMON_RAM DIVF [8] TXBOOST 0x0 160 // 0x6826 RFE_COMMON_RAM DIVF [7] S1GFRC 0x0 161 // 0x6826 RFE_COMMON_RAM DIVF [6:5] BUFGAIN 0x0 162 // 0x6826 RFE_COMMON_RAM DIVF [4] BIAS 0x0 163 // 0x6826 RFE_COMMON_RAM DIVF [3] OUT 0x1 164 // 0x6826 RFE_COMMON_RAM DIVF [2:0] RATIO 0x0 165 // 0x6828 RFE_COMMON_RAM DIVLDOI [15] ITEST 0x0 166 // 0x6828 RFE_COMMON_RAM DIVLDOI [14:8] VOUTTRIM 0x00 167 // 0x6828 RFE_COMMON_RAM DIVLDOI [7] ITST 0x0 168 // 0x6828 RFE_COMMON_RAM DIVLDOI [6:4] TMUX 0x0 169 // 0x6828 RFE_COMMON_RAM DIVLDOI [2] MODE 0x0 170 // 0x6828 RFE_COMMON_RAM DIVLDOI [1] BYPASS 0x0 171 // 0x6828 RFE_COMMON_RAM DIVLDOI [0] CTL 0x0 172 // 0x682A RFE_COMMON_RAM DIVLDOF [15] ITEST 0x0 173 // 0x682A RFE_COMMON_RAM DIVLDOF [14:8] VOUTTRIM 0x00 174 // 0x682A RFE_COMMON_RAM DIVLDOF [7] ITST 0x0 175 // 0x682A RFE_COMMON_RAM DIVLDOF [6:4] TMUX 0x0 176 // 0x682A RFE_COMMON_RAM DIVLDOF [2] MODE 0x0 177 // 0x682A RFE_COMMON_RAM DIVLDOF [1] BYPASS 0x0 178 // 0x682A RFE_COMMON_RAM DIVLDOF [0] CTL 0x0 179 // 0x682C RFE_COMMON_RAM DIVLDOIOFF [6:0] VAL 0x14 180 // 0x682E RFE_COMMON_RAM LDOSETTLE [9:0] VAL 0x047 181 // 0x6830 RFE_COMMON_RAM CHRGSETTLE [9:0] VAL 0x02E 182 // 0x6832 RFE_COMMON_RAM DCOSETTLE [9:0] VAL 0x005 183 // 0x6834 RFE_COMMON_RAM IFAMPRFLDOTX [15:9] TRIM 0x7F 184 // 0x6836 RFE_COMMON_RAM IFAMPRFLDODEFAULT [15:9] TRIM 0x00 185 // 0x683E RFE_COMMON_RAM PHYRSSIOFFSET [7:0] VAL 0x50 186 // 0x6840 RFE_COMMON_RAM SPARE0SHADOW [15:0] VAL 0x0022 187 // 0x6842 RFE_COMMON_RAM SPARE1SHADOW [15:0] VAL 0x0045 188 // 0x6844 RFE_COMMON_RAM AGCINFO [0] MODE 0x0 189 190 191 #endif 192
