1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 #ifndef __HW_WDT_H__ 35 #define __HW_WDT_H__ 36 37 //***************************************************************************** 38 // 39 // The following are defines for the WDT register offsets. 40 // 41 //***************************************************************************** 42 #define WDT_O_LOAD 0x00000000 43 #define WDT_O_VALUE 0x00000004 44 #define WDT_O_CTL 0x00000008 45 #define WDT_O_ICR 0x0000000C 46 #define WDT_O_RIS 0x00000010 47 #define WDT_O_MIS 0x00000014 48 #define WDT_O_TEST 0x00000418 49 #define WDT_O_LOCK 0x00000C00 50 51 52 53 //****************************************************************************** 54 // 55 // The following are defines for the bit fields in the WDT_O_LOAD register. 56 // 57 //****************************************************************************** 58 #define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value 59 #define WDT_LOAD_S 0 60 //****************************************************************************** 61 // 62 // The following are defines for the bit fields in the WDT_O_VALUE register. 63 // 64 //****************************************************************************** 65 #define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value 66 #define WDT_VALUE_S 0 67 //****************************************************************************** 68 // 69 // The following are defines for the bit fields in the WDT_O_CTL register. 70 // 71 //****************************************************************************** 72 #define WDT_CTL_WRC 0x80000000 // Write Complete 73 #define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type 74 #define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable. This bit 75 // is not used in cc3xx, WDOG shall 76 // always generate RESET to system 77 // irrespective of this bit setting. 78 #define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable 79 //****************************************************************************** 80 // 81 // The following are defines for the bit fields in the WDT_O_ICR register. 82 // 83 //****************************************************************************** 84 #define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear 85 #define WDT_ICR_S 0 86 //****************************************************************************** 87 // 88 // The following are defines for the bit fields in the WDT_O_RIS register. 89 // 90 //****************************************************************************** 91 #define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status 92 //****************************************************************************** 93 // 94 // The following are defines for the bit fields in the WDT_O_MIS register. 95 // 96 //****************************************************************************** 97 #define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status 98 //****************************************************************************** 99 // 100 // The following are defines for the bit fields in the WDT_O_TEST register. 101 // 102 //****************************************************************************** 103 #define WDT_TEST_STALL_EN_M 0x00000C00 // Watchdog stall enable 104 #define WDT_TEST_STALL_EN_S 10 105 #define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable 106 //****************************************************************************** 107 // 108 // The following are defines for the bit fields in the WDT_O_LOCK register. 109 // 110 //****************************************************************************** 111 #define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock 112 #define WDT_LOCK_S 0 113 #define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked 114 #define WDT_LOCK_LOCKED 0x00000001 // Locked 115 #define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer 116 117 //***************************************************************************** 118 // 119 // The following are defines for the bit fields in the WDT_ISR, WDT_RIS, and 120 // WDT_MIS registers. 121 // 122 //***************************************************************************** 123 #define WDT_INT_TIMEOUT 0x00000001 // Watchdog timer expired 124 125 126 127 128 129 #endif // __HW_WDT_H__ 130
