1 /* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 11 * Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the 14 * distribution. 15 * 16 * Neither the name of Texas Instruments Incorporated nor the names of 17 * its contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34 35 #ifndef __HW_STACK_DIE_CTRL_H__ 36 #define __HW_STACK_DIE_CTRL_H__ 37 38 //***************************************************************************** 39 // 40 // The following are defines for the STACK_DIE_CTRL register offsets. 41 // 42 //***************************************************************************** 43 #define STACK_DIE_CTRL_O_STK_UP_RESET \ 44 0x00000000 // Can be written only by Base 45 // Processor. Writing to this 46 // register will reset the stack 47 // processor reset will be 48 // de-asserted upon clearing this 49 // register. 50 51 #define STACK_DIE_CTRL_O_SR_MASTER_PRIORITY \ 52 0x00000004 // This register defines who among 53 // base processor and stack 54 // processor have highest priority 55 // for Sram Access. Can be written 56 // only by Base Processor. 57 58 #define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 \ 59 0x00000008 // In Spinlock mode this Register 60 // defines who among base processor 61 // and stack processor have access 62 // to Sram Bank2 right now. In 63 // Handshake mode this Register 64 // defines who among base processor 65 // and stack processor have access 66 // to Sram Bank2 and Bank3 right 67 // now. Its Clear only register and 68 // is set by hardware. Lower bit can 69 // be cleared only by Base Processor 70 // and Upper bit Cleared only by the 71 // Stack processor. 72 73 #define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 \ 74 0x0000000C // In Spinlock mode whenever Base 75 // processor wants the access to 76 // Sram Bank2 it should request for 77 // it by writing into this register. 78 // It'll get interrupt whenever it 79 // is granted. In Handshake mode 80 // this bit will be set by Stack 81 // processor. Its a set only bit and 82 // is cleared by HW when the request 83 // is granted. 84 85 #define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 \ 86 0x00000010 // In Spinlock mode Whenever Stack 87 // processor wants the access to 88 // Sram Bank2 it should request for 89 // it by writing into this register. 90 // It'll get interrupt whenever it 91 // is granted. In Handshake mode 92 // this bit will be set by the Base 93 // processor. Its a set only bit and 94 // is cleared by HW when the request 95 // is granted. 96 97 #define STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 \ 98 0x00000014 // Register defines who among base 99 // processor and stack processor 100 // have access to Sram Bank3 right 101 // now. Its Clear only register and 102 // is set by hardware. Lower bit can 103 // be cleared only by Base Processor 104 // and Upper bit Cleared only by the 105 // Stack processor. 106 107 #define STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 \ 108 0x00000018 // In Spinlock mode whenever Base 109 // processor wants the access to 110 // Sram Bank3 it should request for 111 // it by writing into this register. 112 // It'll get interrupt whenever it 113 // is granted. In Handshake mode 114 // this bit will be set by Stack 115 // processor. Its a set only bit and 116 // is cleared by HW when the request 117 // is granted. 118 119 #define STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 \ 120 0x0000001C // In Spinlock mode Whenever Stack 121 // processor wants the access to 122 // Sram Bank3 it should request for 123 // it by writing into this register. 124 // It'll get interrupt whenever it 125 // is granted. In Handshake mode 126 // this bit will be set by the Base 127 // processor. Its a set only bit and 128 // is cleared by HW when the request 129 // is granted. 130 131 #define STACK_DIE_CTRL_O_RDSM_CFG_CPU \ 132 0x00000020 // Read State Machine timing 133 // configuration register. Generally 134 // Bit 4 and 3 will be identical. 135 // For stacked die always 43 are 0 136 // and 6:5 == 1 for 120Mhz. 137 138 #define STACK_DIE_CTRL_O_RDSM_CFG_EE \ 139 0x00000024 // Read State Machine timing 140 // configuration register. Generally 141 // Bit 4 and 3 will be identical. 142 // For stacked die always 43 are 0 143 // and 6:5 == 1 for 120Mhz. 144 145 #define STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG \ 146 0x00000028 // Reading this register Base 147 // procesor will able to know the 148 // reason for the interrupt. This is 149 // clear only register - set by HW 150 // upon an interrupt to Base 151 // processor and can be cleared only 152 // by BASE processor. 153 154 #define STACK_DIE_CTRL_O_STK_UP_IRQ_LOG \ 155 0x0000002C // Reading this register Stack 156 // procesor will able to know the 157 // reason for the interrupt. This is 158 // clear only register - set by HW 159 // upon an interrupt to Stack 160 // processor and can be cleared only 161 // by Stack processor. 162 163 #define STACK_DIE_CTRL_O_STK_CLK_EN \ 164 0x00000030 // Can be written only by base 165 // processor. Controls the enable 166 // pin of the cgcs for the clocks 167 // going to CM3 dft ctrl block and 168 // Sram. 169 170 #define STACK_DIE_CTRL_O_SPIN_LOCK_MODE \ 171 0x00000034 // Can be written only by the base 172 // processor. Decides the ram 173 // sharing mode :: handshake or 174 // Spinlock mode. 175 176 #define STACK_DIE_CTRL_O_BUS_FAULT_ADDR \ 177 0x00000038 // Stores the last bus fault 178 // address. 179 180 #define STACK_DIE_CTRL_O_BUS_FAULT_CLR \ 181 0x0000003C // write only registers on read 182 // returns 0.W Write 1 to clear the 183 // bust fault to store the new bus 184 // fault address 185 186 #define STACK_DIE_CTRL_O_RESET_CAUSE \ 187 0x00000040 // Reset cause value captured from 188 // the ICR_CLKRST block. 189 190 #define STACK_DIE_CTRL_O_WDOG_TIMER_EVENT \ 191 0x00000044 // Watchdog timer event value 192 // captured from the ICR_CLKRST 193 // block 194 195 #define STACK_DIE_CTRL_O_DMA_REQ \ 196 0x00000048 // To send Dma Request to bottom 197 // die. 198 199 #define STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR \ 200 0x0000004C // Address offset within SRAM to 201 // which CM3 should jump after 202 // reset. 203 204 #define STACK_DIE_CTRL_O_SW_REG1 \ 205 0x00000050 // These are sw registers for 206 // topdie processor and bottom die 207 // processor to communicate. Both 208 // can set and read these registers. 209 // In case of write clash bottom 210 // die's processor wins and top die 211 // processor access is ignored. 212 213 #define STACK_DIE_CTRL_O_SW_REG2 \ 214 0x00000054 // These are sw registers for 215 // topdie processor and bottom die 216 // processor to communicate. Both 217 // can set and read these registers. 218 // In case of write clash bottom 219 // die's processor wins and top die 220 // processor access is ignored. 221 222 #define STACK_DIE_CTRL_O_FMC_SLEEP_CTL \ 223 0x00000058 // By posting the request Flash can 224 // be put into low-power mode 225 // (Sleep) without powering down the 226 // Flash. Earlier (in Garnet) this 227 // was fully h/w controlled and the 228 // control for this was coming from 229 // SysCtl while entering into Cortex 230 // Deep-sleep mode. But for our 231 // device the D2D i/f doesnt support 232 // this. The Firmware has to program 233 // the register in the top-die for 234 // entering into this mode and wait 235 // for an interrupt. 236 237 #define STACK_DIE_CTRL_O_MISC_CTL \ 238 0x0000005C // Miscellanious control register. 239 240 #define STACK_DIE_CTRL_O_SW_DFT_CTL \ 241 0x000000FC // DFT control and status bits 242 243 #define STACK_DIE_CTRL_O_PADN_CTL_0 \ 244 0x00000100 // Mainly for For controlling the 245 // pads OEN pins. There are total 60 246 // pads and hence 60 control registe 247 // i.e n value varies from 0 to 59. 248 // Here is the mapping for the 249 // pad_ctl register number and the 250 // functionality : 0 D2DPAD_DMAREQ1 251 // 1 D2DPAD_DMAREQ0 2 252 // D2DPAD_INT2BASE 3 D2DPAD_PIOSC 4 253 // D2DPAD_RST_N 5 D2DPAD_POR_RST_N 6 254 // D2DPAD_HCLK 7 D2DPAD_JTAG_TDO 8 255 // D2DPAD_JTAG_TCK 9 D2DPAD_JTAG_TMS 256 // 10 D2DPAD_JTAG_TDI 11-27 257 // D2DPAD_FROMSTACK[D2D_FROMSTACK_SIZE 258 // -1:0] 28-56 D2DPAD_TOSTACK 259 // [D2D_TOSTACK_SIZE -1:0] 57-59 260 // D2DPAD_SPARE [D2D_SPARE_PAD_SIZE 261 // -1:0] 0:00 262 263 264 265 266 //****************************************************************************** 267 // 268 // The following are defines for the bit fields in the 269 // STACK_DIE_CTRL_O_STK_UP_RESET register. 270 // 271 //****************************************************************************** 272 #define STACK_DIE_CTRL_STK_UP_RESET_UP_RESET \ 273 0x00000001 // 1 :Assert Reset 0 : Deassert the 274 // Reset 275 276 //****************************************************************************** 277 // 278 // The following are defines for the bit fields in the 279 // STACK_DIE_CTRL_O_SR_MASTER_PRIORITY register. 280 // 281 //****************************************************************************** 282 #define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_M \ 283 0x00000003 // 00 : Equal Priority 01 : Stack 284 // Processor have priority 10 : Base 285 // Processor have priority 11 : 286 // Unused 287 288 #define STACK_DIE_CTRL_SR_MASTER_PRIORITY_PRIORITY_S 0 289 //****************************************************************************** 290 // 291 // The following are defines for the bit fields in the 292 // STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK2 register. 293 // 294 //****************************************************************************** 295 #define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_STK_UP_ACCSS \ 296 0x00000002 // Stack Processor should clear it 297 // when it is done with the sram 298 // bank usage. Set by HW It is set 299 // when Stack Processor is granted 300 // the access to this bank 301 302 #define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK2_BASE_UP_ACCSS \ 303 0x00000001 // Base Processor should clear it 304 // when it is done wth the sram 305 // usage. Set by HW It is set when 306 // Base Processor is granted the 307 // access to this bank 308 309 //****************************************************************************** 310 // 311 // The following are defines for the bit fields in the 312 // STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK2 register. 313 // 314 //****************************************************************************** 315 #define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK2_ACCSS_REQ \ 316 0x00000001 // Base Processor will set when 317 // Sram access is needed in Spin 318 // Lock mode. In Handshake mode 319 // Stack Processor will set to 320 // inform Base Processor that it is 321 // done with the processing of data 322 // in SRAM and is now ready to use 323 // by the base processor. 324 325 //****************************************************************************** 326 // 327 // The following are defines for the bit fields in the 328 // STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK2 register. 329 // 330 //****************************************************************************** 331 #define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK2_ACCSS_REQ \ 332 0x00000001 // Stack Processor will set when 333 // Sram access is needed in Spin 334 // Lock mode. In Handshake mode Base 335 // Processor will set to inform 336 // Stack Processor to start 337 // processing the data in the Ram. 338 339 //****************************************************************************** 340 // 341 // The following are defines for the bit fields in the 342 // STACK_DIE_CTRL_O_STK_SR_ACC_CTL_BK3 register. 343 // 344 //****************************************************************************** 345 #define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_STK_UP_ACCSS \ 346 0x00000002 // Stack Processor should clear it 347 // when it is done with the sram 348 // bank usage. Set by HW It is set 349 // when Stack Processor is granted 350 // the access to this bank. 351 352 #define STACK_DIE_CTRL_STK_SR_ACC_CTL_BK3_BASE_UP_ACCSS \ 353 0x00000001 // Base Processor should clear it 354 // when it is done wth the sram 355 // usage. Set by HW it is set when 356 // Base Processor is granted the 357 // access to this bank. 358 359 //****************************************************************************** 360 // 361 // The following are defines for the bit fields in the 362 // STACK_DIE_CTRL_O_BASE_UP_ACC_REQ_BK3 register. 363 // 364 //****************************************************************************** 365 #define STACK_DIE_CTRL_BASE_UP_ACC_REQ_BK3_ACCSS_REQ \ 366 0x00000001 // Base Processor will set when 367 // Sram access is needed in Spin 368 // Lock mode. Not used in handshake 369 // mode. 370 371 //****************************************************************************** 372 // 373 // The following are defines for the bit fields in the 374 // STACK_DIE_CTRL_O_STK_UP_ACC_REQ_BK3 register. 375 // 376 //****************************************************************************** 377 #define STACK_DIE_CTRL_STK_UP_ACC_REQ_BK3_ACCSS_REQ \ 378 0x00000001 // Stack Processor will set when 379 // Sram access is needed in Spin 380 // Lock mode. 381 382 //****************************************************************************** 383 // 384 // The following are defines for the bit fields in the 385 // STACK_DIE_CTRL_O_RDSM_CFG_CPU register. 386 // 387 //****************************************************************************** 388 #define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_M \ 389 0x000000C0 // Bank Clock Hi Time 00 : HCLK 390 // pulse 01 : 1 cycle of HCLK 10 : 391 // 1.5 cycles of HCLK 11 : 2 cycles 392 // of HCLK 393 394 #define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_PULSE_WIDTH_S 6 395 #define STACK_DIE_CTRL_RDSM_CFG_CPU_FLCLK_SENSE \ 396 0x00000020 // FLCLK 0 : indicates flash clock 397 // rise aligns on HCLK rise 1 : 398 // indicates flash clock rise aligns 399 // on HCLK fall 400 401 #define STACK_DIE_CTRL_RDSM_CFG_CPU_PIPELINE_FLDATA \ 402 0x00000010 // 0 : Always register flash rdata 403 // before sending to CPU 1 : Drive 404 // Flash rdata directly out on MISS 405 // (Both ICODE / DCODE) 406 407 #define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_M \ 408 0x0000000F // Number of wait states inserted 409 410 #define STACK_DIE_CTRL_RDSM_CFG_CPU_READ_WAIT_STATE_S 0 411 //****************************************************************************** 412 // 413 // The following are defines for the bit fields in the 414 // STACK_DIE_CTRL_O_RDSM_CFG_EE register. 415 // 416 //****************************************************************************** 417 #define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_M \ 418 0x000000C0 // Bank Clock Hi Time 00 : HCLK 419 // pulse 01 : 1 cycle of HCLK 10 : 420 // 1.5 cycles of HCLK 11 : 2 cycles 421 // of HCLK 422 423 #define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_PULSE_WIDTH_S 6 424 #define STACK_DIE_CTRL_RDSM_CFG_EE_FLCLK_SENSE \ 425 0x00000020 // FLCLK 0 : indicates flash clock 426 // rise aligns on HCLK rise 1 : 427 // indicates flash clock rise aligns 428 // on HCLK fall 429 430 #define STACK_DIE_CTRL_RDSM_CFG_EE_PIPELINE_FLDATA \ 431 0x00000010 // 0 : Always register flash rdata 432 // before sending to CPU 1 : Drive 433 // Flash rdata directly out on MISS 434 // (Both ICODE / DCODE) 435 436 #define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_M \ 437 0x0000000F // Number of wait states inserted 438 439 #define STACK_DIE_CTRL_RDSM_CFG_EE_READ_WAIT_STATE_S 0 440 //****************************************************************************** 441 // 442 // The following are defines for the bit fields in the 443 // STACK_DIE_CTRL_O_BASE_UP_IRQ_LOG register. 444 // 445 //****************************************************************************** 446 #define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_REL \ 447 0x00000010 // Set when Relinquish Interrupt 448 // sent to Base processor for Bank3. 449 450 #define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_RELEASE \ 451 0x00000008 // Set when Relinquish Interrupt 452 // sent to Base processor for Bank2. 453 454 #define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK3_GRANT \ 455 0x00000004 // Set when Bank3 is granted to 456 // Base processor. 457 458 #define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_BK2_GRANT \ 459 0x00000002 // Set when Bank2 is granted to 460 // BAse processor. 461 462 #define STACK_DIE_CTRL_BASE_UP_IRQ_LOG_SR_INVAL_ACCSS \ 463 0x00000001 // Set when there Base processor do 464 // an Invalid access to Sram. Ex : 465 // Accessing the bank which is not 466 // granted for BAse processor. 467 468 //****************************************************************************** 469 // 470 // The following are defines for the bit fields in the 471 // STACK_DIE_CTRL_O_STK_UP_IRQ_LOG register. 472 // 473 //****************************************************************************** 474 #define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_REL \ 475 0x00000008 // Set when Relinquish Interrupt 476 // sent to Stack processor for 477 // Bank3. 478 479 #define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_REL \ 480 0x00000004 // Set when Relinquish Interrupt 481 // sent to Stack processor for 482 // Bank2. 483 484 #define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK3_GRANT \ 485 0x00000002 // Set when Bank3 is granted to 486 // Stack processor. 487 488 #define STACK_DIE_CTRL_STK_UP_IRQ_LOG_SR_BK2_GRANT \ 489 0x00000001 // Set when Bank2 is granted to 490 // Stack processor. 491 492 //****************************************************************************** 493 // 494 // The following are defines for the bit fields in the 495 // STACK_DIE_CTRL_O_STK_CLK_EN register. 496 // 497 //****************************************************************************** 498 #define STACK_DIE_CTRL_STK_CLK_EN_SR_CLK \ 499 0x00000004 // Enable the clock going to sram. 500 501 #define STACK_DIE_CTRL_STK_CLK_EN_DFT_CTRL_CLK \ 502 0x00000002 // Enable the clock going to dft 503 // control block 504 505 #define STACK_DIE_CTRL_STK_CLK_EN_STK_UP_CLK \ 506 0x00000001 // Enable the clock going to Cm3 507 508 //****************************************************************************** 509 // 510 // The following are defines for the bit fields in the 511 // STACK_DIE_CTRL_O_SPIN_LOCK_MODE register. 512 // 513 //****************************************************************************** 514 #define STACK_DIE_CTRL_SPIN_LOCK_MODE_MODE \ 515 0x00000001 // 0 : Handshake Mode 1 : Spinlock 516 // mode. 517 518 //****************************************************************************** 519 // 520 // The following are defines for the bit fields in the 521 // STACK_DIE_CTRL_O_BUS_FAULT_ADDR register. 522 // 523 //****************************************************************************** 524 #define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_M \ 525 0xFFFFFFFF // Fault Address 526 527 #define STACK_DIE_CTRL_BUS_FAULT_ADDR_ADDRESS_S 0 528 //****************************************************************************** 529 // 530 // The following are defines for the bit fields in the 531 // STACK_DIE_CTRL_O_BUS_FAULT_CLR register. 532 // 533 //****************************************************************************** 534 #define STACK_DIE_CTRL_BUS_FAULT_CLR_CLEAR \ 535 0x00000001 // When set it'll clear the bust 536 // fault address register to store 537 // the new bus fault address 538 539 //****************************************************************************** 540 // 541 // The following are defines for the bit fields in the 542 // STACK_DIE_CTRL_O_RESET_CAUSE register. 543 // 544 //****************************************************************************** 545 #define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_M \ 546 0xFFFFFFFF 547 548 #define STACK_DIE_CTRL_RESET_CAUSE_RST_CAUSE_S 0 549 //****************************************************************************** 550 // 551 // The following are defines for the bit fields in the 552 // STACK_DIE_CTRL_O_WDOG_TIMER_EVENT register. 553 // 554 //****************************************************************************** 555 #define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_M \ 556 0xFFFFFFFF 557 558 #define STACK_DIE_CTRL_WDOG_TIMER_EVENT_WDOG_TMR_EVNT_S 0 559 //****************************************************************************** 560 // 561 // The following are defines for the bit fields in the 562 // STACK_DIE_CTRL_O_DMA_REQ register. 563 // 564 //****************************************************************************** 565 #define STACK_DIE_CTRL_DMA_REQ_DMAREQ1 \ 566 0x00000002 // Generate DMAREQ1 on setting this 567 // bit. 568 569 #define STACK_DIE_CTRL_DMA_REQ_DMAREQ0 \ 570 0x00000001 // Generate DMAREQ0 on setting this 571 // bit. 572 573 //****************************************************************************** 574 // 575 // The following are defines for the bit fields in the 576 // STACK_DIE_CTRL_O_SRAM_JUMP_OFFSET_ADDR register. 577 // 578 //****************************************************************************** 579 #define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_M \ 580 0xFFFFFFFF 581 582 #define STACK_DIE_CTRL_SRAM_JUMP_OFFSET_ADDR_ADDR_S 0 583 //****************************************************************************** 584 // 585 // The following are defines for the bit fields in the 586 // STACK_DIE_CTRL_O_SW_REG1 register. 587 // 588 //****************************************************************************** 589 #define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_M \ 590 0xFFFFFFFF 591 592 #define STACK_DIE_CTRL_SW_REG1_NEWBITFIELD1_S 0 593 //****************************************************************************** 594 // 595 // The following are defines for the bit fields in the 596 // STACK_DIE_CTRL_O_SW_REG2 register. 597 // 598 //****************************************************************************** 599 #define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_M \ 600 0xFFFFFFFF 601 602 #define STACK_DIE_CTRL_SW_REG2_NEWBITFIELD1_S 0 603 //****************************************************************************** 604 // 605 // The following are defines for the bit fields in the 606 // STACK_DIE_CTRL_O_FMC_SLEEP_CTL register. 607 // 608 //****************************************************************************** 609 #define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_ACK \ 610 0x00000002 // captures the status of of 611 // fmc_lpm_ack 612 613 #define STACK_DIE_CTRL_FMC_SLEEP_CTL_FMC_LPM_REQ \ 614 0x00000001 // When set assert 615 // iflpe2fmc_lpm_req to FMC. 616 617 //****************************************************************************** 618 // 619 // The following are defines for the bit fields in the 620 // STACK_DIE_CTRL_O_MISC_CTL register. 621 // 622 //****************************************************************************** 623 #define STACK_DIE_CTRL_MISC_CTL_WDOG_RESET \ 624 0x00000080 // 1 : will reset the async wdog 625 // timer runing on piosc clock 626 627 #define STACK_DIE_CTRL_MISC_CTL_FW_IRQ2 \ 628 0x00000020 // Setting this Will send to 629 // interttupt to CM3 630 631 #define STACK_DIE_CTRL_MISC_CTL_FW_IRQ1 \ 632 0x00000010 // Setting this Will send to 633 // interttupt to CM3 634 635 #define STACK_DIE_CTRL_MISC_CTL_FW_IRQ0 \ 636 0x00000008 // Setting this Will send to 637 // interttupt to CM3 638 639 #define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK3 \ 640 0x00000004 // While testing Flash Setting this 641 // bit will Control the 642 // CE/STR/AIN/CLKIN going to flash 643 // banks 12 and 3. 0 : Control 644 // signals coming from FMC for Bank 645 // 3 goes to Bank3 1 : Control 646 // signals coming from FMC for Bank 647 // 0 goes to Bank2 648 649 #define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK2 \ 650 0x00000002 // While testing Flash Setting this 651 // bit will Control the 652 // CE/STR/AIN/CLKIN going to flash 653 // banks 12 and 3. 0 : Control 654 // signals coming from FMC for Bank 655 // 2 goes to Bank2 1 : Control 656 // signals coming from FMC for Bank 657 // 0 goes to Bank2 658 659 #define STACK_DIE_CTRL_MISC_CTL_FLB_TEST_MUX_CTL_BK1 \ 660 0x00000001 // While testing Flash Setting this 661 // bit will Control the 662 // CE/STR/AIN/CLKIN going to flash 663 // banks 12 and 3. 0 : Control 664 // signals coming from FMC for Bank 665 // 1 goes to Bank1 1 : Control 666 // signals coming from FMC for Bank 667 // 0 goes to Bank1 668 669 //****************************************************************************** 670 // 671 // The following are defines for the bit fields in the 672 // STACK_DIE_CTRL_O_SW_DFT_CTL register. 673 // 674 //****************************************************************************** 675 #define STACK_DIE_CTRL_SW_DFT_CTL_FL_CTRL_OWNS \ 676 0x20000000 // when set to '1' all flash 677 // control signals switch over to 678 // CM3 control when '0' it is under 679 // the D2D interface control 680 681 #define STACK_DIE_CTRL_SW_DFT_CTL_SWIF_CPU_READ \ 682 0x10000000 // 1 indicates in SWIF mode the 683 // control signals to flash are from 684 // FMC CPU read controls the clock 685 // and address. that is one can give 686 // address via FMC and read through 687 // IDMEM. 688 689 #define STACK_DIE_CTRL_SW_DFT_CTL_CPU_DONE \ 690 0x00800000 // 'CPU Done' bit for PBIST. Write 691 // '1' to indicate test done. 692 693 #define STACK_DIE_CTRL_SW_DFT_CTL_CPU_FAIL \ 694 0x00400000 // 'CPU Fail' bit for PBIST. Write 695 // '1' to indicate test failed. 696 697 #define STACK_DIE_CTRL_SW_DFT_CTL_FLBK4_OWNS \ 698 0x00001000 // when set to '1' flash bank 4 699 // (EEPROM) is owned by the CM3for 700 // reads over DCODE bus. When '0' 701 // access control given to D2D 702 // interface. 703 704 #define STACK_DIE_CTRL_SW_DFT_CTL_FLBK3_OWNS \ 705 0x00000800 // when set to '1' flash bank 3 is 706 // owned by the CM3for reads over 707 // DCODE bus. When '0' access 708 // control given to D2D interface. 709 710 #define STACK_DIE_CTRL_SW_DFT_CTL_FLBK2_OWNS \ 711 0x00000400 // when set to '1' flash bank 2 is 712 // owned by the CM3for reads over 713 // DCODE bus. When '0' access 714 // control given to D2D interface. 715 716 #define STACK_DIE_CTRL_SW_DFT_CTL_FLBK1_OWNS \ 717 0x00000200 // when set to '1' flash bank 1 is 718 // owned by the CM3for reads over 719 // DCODE bus. When '0' access 720 // control given to D2D interface. 721 722 #define STACK_DIE_CTRL_SW_DFT_CTL_FLBK0_OWNS \ 723 0x00000100 // when set to '1' flash bank 0 is 724 // owned by the CM3 for reads over 725 // DCODE bus. When '0' access 726 // control given to D2D interface. 727 728 //****************************************************************************** 729 // 730 // The following are defines for the bit fields in the 731 // STACK_DIE_CTRL_O_PADN_CTL_0 register. 732 // 733 //****************************************************************************** 734 #define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DOUT \ 735 0x00000008 // This bit is valid for only the 736 // spare pads ie for n=57 to 59. 737 // value to drive at the output of 738 // the pad 739 740 #define STACK_DIE_CTRL_PADN_CTL_0_SPARE_PAD_DIN \ 741 0x00000004 // This bit is valid for only the 742 // spare pads ie for n=57 to 59. 743 // captures the 'Y' pin of the pad 744 // which is the data being driven 745 // into the die 746 747 #define STACK_DIE_CTRL_PADN_CTL_0_OEN2X \ 748 0x00000002 // OEN2X control when '1' enables 749 // the output with 1x. Total drive 750 // strength is decided bu oen1x 751 // setting + oen2x setting. 752 753 #define STACK_DIE_CTRL_PADN_CTL_0_OEN1X \ 754 0x00000001 // OEN1X control when '1' enables 755 // the output with 1x . Total drive 756 // strength is decided bu oen1x 757 // setting + oen2x setting. 758 759 760 761 762 #endif // __HW_STACK_DIE_CTRL_H__ 763
