1 /****************************************************************************** 2 * Filename: hw_prcm_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_PRCM_H__ 38 #define __HW_PRCM_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // PRCM component 44 // 45 //***************************************************************************** 46 // Infrastructure Clock Division Factor For Run Mode 47 #define PRCM_O_INFRCLKDIVR 0x00000000 48 49 // Infrastructure Clock Division Factor For Sleep Mode 50 #define PRCM_O_INFRCLKDIVS 0x00000004 51 52 // Infrastructure Clock Division Factor For DeepSleep Mode 53 #define PRCM_O_INFRCLKDIVDS 0x00000008 54 55 // MCU Voltage Domain Control 56 #define PRCM_O_VDCTL 0x0000000C 57 58 // Load PRCM Settings To CLKCTRL Power Domain 59 #define PRCM_O_CLKLOADCTL 0x00000028 60 61 // RFC Clock Gate 62 #define PRCM_O_RFCCLKG 0x0000002C 63 64 // VIMS Clock Gate 65 #define PRCM_O_VIMSCLKG 0x00000030 66 67 // SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes 68 #define PRCM_O_SECDMACLKGR 0x0000003C 69 70 // SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode 71 #define PRCM_O_SECDMACLKGS 0x00000040 72 73 // SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode 74 #define PRCM_O_SECDMACLKGDS 0x00000044 75 76 // GPIO Clock Gate For Run And All Modes 77 #define PRCM_O_GPIOCLKGR 0x00000048 78 79 // GPIO Clock Gate For Sleep Mode 80 #define PRCM_O_GPIOCLKGS 0x0000004C 81 82 // GPIO Clock Gate For Deep Sleep Mode 83 #define PRCM_O_GPIOCLKGDS 0x00000050 84 85 // GPT Clock Gate For Run And All Modes 86 #define PRCM_O_GPTCLKGR 0x00000054 87 88 // GPT Clock Gate For Sleep Mode 89 #define PRCM_O_GPTCLKGS 0x00000058 90 91 // GPT Clock Gate For Deep Sleep Mode 92 #define PRCM_O_GPTCLKGDS 0x0000005C 93 94 // I2C Clock Gate For Run And All Modes 95 #define PRCM_O_I2CCLKGR 0x00000060 96 97 // I2C Clock Gate For Sleep Mode 98 #define PRCM_O_I2CCLKGS 0x00000064 99 100 // I2C Clock Gate For Deep Sleep Mode 101 #define PRCM_O_I2CCLKGDS 0x00000068 102 103 // UART Clock Gate For Run And All Modes 104 #define PRCM_O_UARTCLKGR 0x0000006C 105 106 // UART Clock Gate For Sleep Mode 107 #define PRCM_O_UARTCLKGS 0x00000070 108 109 // UART Clock Gate For Deep Sleep Mode 110 #define PRCM_O_UARTCLKGDS 0x00000074 111 112 // SSI Clock Gate For Run And All Modes 113 #define PRCM_O_SSICLKGR 0x00000078 114 115 // SSI Clock Gate For Sleep Mode 116 #define PRCM_O_SSICLKGS 0x0000007C 117 118 // SSI Clock Gate For Deep Sleep Mode 119 #define PRCM_O_SSICLKGDS 0x00000080 120 121 // I2S Clock Gate For Run And All Modes 122 #define PRCM_O_I2SCLKGR 0x00000084 123 124 // I2S Clock Gate For Sleep Mode 125 #define PRCM_O_I2SCLKGS 0x00000088 126 127 // I2S Clock Gate For Deep Sleep Mode 128 #define PRCM_O_I2SCLKGDS 0x0000008C 129 130 // Internal 131 #define PRCM_O_SYSBUSCLKDIV 0x000000B4 132 133 // Internal 134 #define PRCM_O_CPUCLKDIV 0x000000B8 135 136 // Internal 137 #define PRCM_O_PERBUSCPUCLKDIV 0x000000BC 138 139 // Internal 140 #define PRCM_O_PERDMACLKDIV 0x000000C4 141 142 // I2S Clock Control 143 #define PRCM_O_I2SBCLKSEL 0x000000C8 144 145 // GPT Scalar 146 #define PRCM_O_GPTCLKDIV 0x000000CC 147 148 // I2S Clock Control 149 #define PRCM_O_I2SCLKCTL 0x000000D0 150 151 // MCLK Division Ratio 152 #define PRCM_O_I2SMCLKDIV 0x000000D4 153 154 // BCLK Division Ratio 155 #define PRCM_O_I2SBCLKDIV 0x000000D8 156 157 // WCLK Division Ratio 158 #define PRCM_O_I2SWCLKDIV 0x000000DC 159 160 // RESET For SEC (PKA And TRNG And CRYPTO) And UDMA 161 #define PRCM_O_RESETSECDMA 0x000000F0 162 163 // RESET For GPIO IPs 164 #define PRCM_O_RESETGPIO 0x000000F4 165 166 // RESET For GPT Ips 167 #define PRCM_O_RESETGPT 0x000000F8 168 169 // RESET For I2C IPs 170 #define PRCM_O_RESETI2C 0x000000FC 171 172 // RESET For UART IPs 173 #define PRCM_O_RESETUART 0x00000100 174 175 // RESET For SSI IPs 176 #define PRCM_O_RESETSSI 0x00000104 177 178 // RESET For I2S IP 179 #define PRCM_O_RESETI2S 0x00000108 180 181 // Power Domain Control 182 #define PRCM_O_PDCTL0 0x0000012C 183 184 // RFC Power Domain Control 185 #define PRCM_O_PDCTL0RFC 0x00000130 186 187 // SERIAL Power Domain Control 188 #define PRCM_O_PDCTL0SERIAL 0x00000134 189 190 // PERIPH Power Domain Control 191 #define PRCM_O_PDCTL0PERIPH 0x00000138 192 193 // Power Domain Status 194 #define PRCM_O_PDSTAT0 0x00000140 195 196 // RFC Power Domain Status 197 #define PRCM_O_PDSTAT0RFC 0x00000144 198 199 // SERIAL Power Domain Status 200 #define PRCM_O_PDSTAT0SERIAL 0x00000148 201 202 // PERIPH Power Domain Status 203 #define PRCM_O_PDSTAT0PERIPH 0x0000014C 204 205 // Power Domain Control 206 #define PRCM_O_PDCTL1 0x0000017C 207 208 // CPU Power Domain Direct Control 209 #define PRCM_O_PDCTL1CPU 0x00000184 210 211 // RFC Power Domain Direct Control 212 #define PRCM_O_PDCTL1RFC 0x00000188 213 214 // VIMS Mode Direct Control 215 #define PRCM_O_PDCTL1VIMS 0x0000018C 216 217 // Power Manager Status 218 #define PRCM_O_PDSTAT1 0x00000194 219 220 // BUS Power Domain Direct Read Status 221 #define PRCM_O_PDSTAT1BUS 0x00000198 222 223 // RFC Power Domain Direct Read Status 224 #define PRCM_O_PDSTAT1RFC 0x0000019C 225 226 // CPU Power Domain Direct Read Status 227 #define PRCM_O_PDSTAT1CPU 0x000001A0 228 229 // VIMS Mode Direct Read Status 230 #define PRCM_O_PDSTAT1VIMS 0x000001A4 231 232 // Control To RFC 233 #define PRCM_O_RFCBITS 0x000001CC 234 235 // Selected RFC Mode 236 #define PRCM_O_RFCMODESEL 0x000001D0 237 238 // Allowed RFC Modes 239 #define PRCM_O_RFCMODEHWOPT 0x000001D4 240 241 // Power Profiler Register 242 #define PRCM_O_PWRPROFSTAT 0x000001E0 243 244 // Memory Retention Control 245 #define PRCM_O_RAMRETEN 0x00000224 246 247 // Oscillator Interrupt Mask Control 248 #define PRCM_O_OSCIMSC 0x00000290 249 250 // Oscillator Raw Interrupt Status 251 #define PRCM_O_OSCRIS 0x00000294 252 253 // Oscillator Raw Interrupt Clear 254 #define PRCM_O_OSCICR 0x00000298 255 256 //***************************************************************************** 257 // 258 // Register: PRCM_O_INFRCLKDIVR 259 // 260 //***************************************************************************** 261 // Field: [1:0] RATIO 262 // 263 // Division rate for clocks driving modules in the MCU_AON domain when system 264 // CPU is in run mode. Division ratio affects both infrastructure clock and 265 // perbusull clock. 266 // ENUMs: 267 // DIV32 Divide by 32 268 // DIV8 Divide by 8 269 // DIV2 Divide by 2 270 // DIV1 Divide by 1 271 #define PRCM_INFRCLKDIVR_RATIO_W 2 272 #define PRCM_INFRCLKDIVR_RATIO_M 0x00000003 273 #define PRCM_INFRCLKDIVR_RATIO_S 0 274 #define PRCM_INFRCLKDIVR_RATIO_DIV32 0x00000003 275 #define PRCM_INFRCLKDIVR_RATIO_DIV8 0x00000002 276 #define PRCM_INFRCLKDIVR_RATIO_DIV2 0x00000001 277 #define PRCM_INFRCLKDIVR_RATIO_DIV1 0x00000000 278 279 //***************************************************************************** 280 // 281 // Register: PRCM_O_INFRCLKDIVS 282 // 283 //***************************************************************************** 284 // Field: [1:0] RATIO 285 // 286 // Division rate for clocks driving modules in the MCU_AON domain when system 287 // CPU is in sleep mode. Division ratio affects both infrastructure clock and 288 // perbusull clock. 289 // ENUMs: 290 // DIV32 Divide by 32 291 // DIV8 Divide by 8 292 // DIV2 Divide by 2 293 // DIV1 Divide by 1 294 #define PRCM_INFRCLKDIVS_RATIO_W 2 295 #define PRCM_INFRCLKDIVS_RATIO_M 0x00000003 296 #define PRCM_INFRCLKDIVS_RATIO_S 0 297 #define PRCM_INFRCLKDIVS_RATIO_DIV32 0x00000003 298 #define PRCM_INFRCLKDIVS_RATIO_DIV8 0x00000002 299 #define PRCM_INFRCLKDIVS_RATIO_DIV2 0x00000001 300 #define PRCM_INFRCLKDIVS_RATIO_DIV1 0x00000000 301 302 //***************************************************************************** 303 // 304 // Register: PRCM_O_INFRCLKDIVDS 305 // 306 //***************************************************************************** 307 // Field: [1:0] RATIO 308 // 309 // Division rate for clocks driving modules in the MCU_AON domain when system 310 // CPU is in seepsleep mode. Division ratio affects both infrastructure clock 311 // and perbusull clock. 312 // ENUMs: 313 // DIV32 Divide by 32 314 // DIV8 Divide by 8 315 // DIV2 Divide by 2 316 // DIV1 Divide by 1 317 #define PRCM_INFRCLKDIVDS_RATIO_W 2 318 #define PRCM_INFRCLKDIVDS_RATIO_M 0x00000003 319 #define PRCM_INFRCLKDIVDS_RATIO_S 0 320 #define PRCM_INFRCLKDIVDS_RATIO_DIV32 0x00000003 321 #define PRCM_INFRCLKDIVDS_RATIO_DIV8 0x00000002 322 #define PRCM_INFRCLKDIVDS_RATIO_DIV2 0x00000001 323 #define PRCM_INFRCLKDIVDS_RATIO_DIV1 0x00000000 324 325 //***************************************************************************** 326 // 327 // Register: PRCM_O_VDCTL 328 // 329 //***************************************************************************** 330 // Field: [0] ULDO 331 // 332 // Request PMCTL to switch to uLDO. 333 // 334 // 0: No request 335 // 1: Assert request when possible 336 // 337 // The bit will have no effect before the following requirements are met: 338 // 1. PDCTL1.CPU_ON = 0 339 // 2. PDCTL1.VIMS_MODE = x0 340 // 3. SECDMACLKGDS.DMA_CLK_EN = 0 and S.CRYPTO_CLK_EN] = 0 and 341 // SECDMACLKGR.DMA_AM_CLK_EN = 0 (Note: Settings must be loaded with 342 // CLKLOADCTL.LOAD) 343 // 4. SECDMACLKGDS.CRYPTO_CLK_EN = 0 and SECDMACLKGR.CRYPTO_AM_CLK_EN = 0 344 // (Note: Settings must be loaded with CLKLOADCTL.LOAD) 345 // 5. I2SCLKGDS.CLK_EN = 0 and I2SCLKGR.AM_CLK_EN = 0 (Note: Settings must be 346 // loaded with CLKLOADCTL.LOAD) 347 // 6. RFC do no request access to BUS 348 // 7. System CPU in deepsleep 349 #define PRCM_VDCTL_ULDO 0x00000001 350 #define PRCM_VDCTL_ULDO_BITN 0 351 #define PRCM_VDCTL_ULDO_M 0x00000001 352 #define PRCM_VDCTL_ULDO_S 0 353 354 //***************************************************************************** 355 // 356 // Register: PRCM_O_CLKLOADCTL 357 // 358 //***************************************************************************** 359 // Field: [1] LOAD_DONE 360 // 361 // Status of LOAD. 362 // Will be cleared to 0 when any of the registers requiring a LOAD is written 363 // to, and be set to 1 when a LOAD is done. 364 // Note that writing no change to a register will result in the LOAD_DONE being 365 // cleared. 366 // 367 // 0 : One or more registers have been write accessed after last LOAD 368 // 1 : No registers are write accessed after last LOAD 369 #define PRCM_CLKLOADCTL_LOAD_DONE 0x00000002 370 #define PRCM_CLKLOADCTL_LOAD_DONE_BITN 1 371 #define PRCM_CLKLOADCTL_LOAD_DONE_M 0x00000002 372 #define PRCM_CLKLOADCTL_LOAD_DONE_S 1 373 374 // Field: [0] LOAD 375 // 376 // 377 // 0: No action 378 // 1: Load settings to CLKCTRL. Bit is HW cleared. 379 // 380 // Multiple changes to settings may be done before LOAD is written once so all 381 // changes takes place at the same time. LOAD can also be done after single 382 // setting updates. 383 // 384 // Registers that needs to be followed by LOAD before settings being applied 385 // are: 386 // - SYSBUSCLKDIV 387 // - CPUCLKDIV 388 // - PERBUSCPUCLKDIV 389 // - PERDMACLKDIV 390 // - PERBUSCPUCLKG 391 // - RFCCLKG 392 // - VIMSCLKG 393 // - SECDMACLKGR 394 // - SECDMACLKGS 395 // - SECDMACLKGDS 396 // - GPIOCLKGR 397 // - GPIOCLKGS 398 // - GPIOCLKGDS 399 // - GPTCLKGR 400 // - GPTCLKGS 401 // - GPTCLKGDS 402 // - GPTCLKDIV 403 // - I2CCLKGR 404 // - I2CCLKGS 405 // - I2CCLKGDS 406 // - SSICLKGR 407 // - SSICLKGS 408 // - SSICLKGDS 409 // - UARTCLKGR 410 // - UARTCLKGS 411 // - UARTCLKGDS 412 // - I2SCLKGR 413 // - I2SCLKGS 414 // - I2SCLKGDS 415 // - I2SBCLKSEL 416 // - I2SCLKCTL 417 // - I2SMCLKDIV 418 // - I2SBCLKDIV 419 // - I2SWCLKDIV 420 #define PRCM_CLKLOADCTL_LOAD 0x00000001 421 #define PRCM_CLKLOADCTL_LOAD_BITN 0 422 #define PRCM_CLKLOADCTL_LOAD_M 0x00000001 423 #define PRCM_CLKLOADCTL_LOAD_S 0 424 425 //***************************************************************************** 426 // 427 // Register: PRCM_O_RFCCLKG 428 // 429 //***************************************************************************** 430 // Field: [0] CLK_EN 431 // 432 // 433 // 0: Disable Clock 434 // 1: Enable clock if RFC power domain is on 435 // 436 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 437 #define PRCM_RFCCLKG_CLK_EN 0x00000001 438 #define PRCM_RFCCLKG_CLK_EN_BITN 0 439 #define PRCM_RFCCLKG_CLK_EN_M 0x00000001 440 #define PRCM_RFCCLKG_CLK_EN_S 0 441 442 //***************************************************************************** 443 // 444 // Register: PRCM_O_VIMSCLKG 445 // 446 //***************************************************************************** 447 // Field: [1:0] CLK_EN 448 // 449 // 00: Disable clock 450 // 01: Disable clock when SYSBUS clock is disabled 451 // 11: Enable clock 452 // 453 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 454 #define PRCM_VIMSCLKG_CLK_EN_W 2 455 #define PRCM_VIMSCLKG_CLK_EN_M 0x00000003 456 #define PRCM_VIMSCLKG_CLK_EN_S 0 457 458 //***************************************************************************** 459 // 460 // Register: PRCM_O_SECDMACLKGR 461 // 462 //***************************************************************************** 463 // Field: [24] DMA_AM_CLK_EN 464 // 465 // 466 // 0: No force 467 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 468 // 469 // Overrides DMA_CLK_EN, SECDMACLKGS.DMA_CLK_EN and SECDMACLKGDS.DMA_CLK_EN 470 // when enabled. 471 // 472 // SYSBUS clock will always run when enabled 473 // 474 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 475 #define PRCM_SECDMACLKGR_DMA_AM_CLK_EN 0x01000000 476 #define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_BITN 24 477 #define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_M 0x01000000 478 #define PRCM_SECDMACLKGR_DMA_AM_CLK_EN_S 24 479 480 // Field: [19] PKA_ZERIOZE_RESET_N 481 // 482 // Zeroization logic hardware reset. 483 // 484 // 0: pka_zeroize logic inactive. 485 // 1: pka_zeroize of memory is enabled. 486 // 487 // This register must remain active until the memory are completely zeroized 488 // which requires 256 periods on systembus clock. 489 #define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N 0x00080000 490 #define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_BITN 19 491 #define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_M 0x00080000 492 #define PRCM_SECDMACLKGR_PKA_ZERIOZE_RESET_N_S 19 493 494 // Field: [18] PKA_AM_CLK_EN 495 // 496 // 497 // 0: No force 498 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 499 // 500 // Overrides PKA_CLK_EN, SECDMACLKGS.PKA_CLK_EN and SECDMACLKGDS.PKA_CLK_EN 501 // when enabled. 502 // 503 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 504 #define PRCM_SECDMACLKGR_PKA_AM_CLK_EN 0x00040000 505 #define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_BITN 18 506 #define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_M 0x00040000 507 #define PRCM_SECDMACLKGR_PKA_AM_CLK_EN_S 18 508 509 // Field: [17] TRNG_AM_CLK_EN 510 // 511 // 512 // 0: No force 513 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 514 // 515 // Overrides TRNG_CLK_EN, SECDMACLKGS.TRNG_CLK_EN and SECDMACLKGDS.TRNG_CLK_EN 516 // when enabled. 517 // 518 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 519 #define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN 0x00020000 520 #define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_BITN 17 521 #define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_M 0x00020000 522 #define PRCM_SECDMACLKGR_TRNG_AM_CLK_EN_S 17 523 524 // Field: [16] CRYPTO_AM_CLK_EN 525 // 526 // 527 // 0: No force 528 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 529 // 530 // Overrides CRYPTO_CLK_EN, SECDMACLKGS.CRYPTO_CLK_EN and 531 // SECDMACLKGDS.CRYPTO_CLK_EN when enabled. 532 // 533 // SYSBUS clock will always run when enabled 534 // 535 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 536 #define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN 0x00010000 537 #define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_BITN 16 538 #define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_M 0x00010000 539 #define PRCM_SECDMACLKGR_CRYPTO_AM_CLK_EN_S 16 540 541 // Field: [8] DMA_CLK_EN 542 // 543 // 544 // 0: Disable clock 545 // 1: Enable clock 546 // 547 // Can be forced on by DMA_AM_CLK_EN 548 // 549 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 550 #define PRCM_SECDMACLKGR_DMA_CLK_EN 0x00000100 551 #define PRCM_SECDMACLKGR_DMA_CLK_EN_BITN 8 552 #define PRCM_SECDMACLKGR_DMA_CLK_EN_M 0x00000100 553 #define PRCM_SECDMACLKGR_DMA_CLK_EN_S 8 554 555 // Field: [2] PKA_CLK_EN 556 // 557 // 558 // 0: Disable clock 559 // 1: Enable clock 560 // 561 // Can be forced on by PKA_AM_CLK_EN 562 // 563 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 564 #define PRCM_SECDMACLKGR_PKA_CLK_EN 0x00000004 565 #define PRCM_SECDMACLKGR_PKA_CLK_EN_BITN 2 566 #define PRCM_SECDMACLKGR_PKA_CLK_EN_M 0x00000004 567 #define PRCM_SECDMACLKGR_PKA_CLK_EN_S 2 568 569 // Field: [1] TRNG_CLK_EN 570 // 571 // 572 // 0: Disable clock 573 // 1: Enable clock 574 // 575 // Can be forced on by TRNG_AM_CLK_EN 576 // 577 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 578 #define PRCM_SECDMACLKGR_TRNG_CLK_EN 0x00000002 579 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_BITN 1 580 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_M 0x00000002 581 #define PRCM_SECDMACLKGR_TRNG_CLK_EN_S 1 582 583 // Field: [0] CRYPTO_CLK_EN 584 // 585 // 586 // 0: Disable clock 587 // 1: Enable clock 588 // 589 // Can be forced on by CRYPTO_AM_CLK_EN 590 // 591 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 592 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN 0x00000001 593 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_BITN 0 594 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_M 0x00000001 595 #define PRCM_SECDMACLKGR_CRYPTO_CLK_EN_S 0 596 597 //***************************************************************************** 598 // 599 // Register: PRCM_O_SECDMACLKGS 600 // 601 //***************************************************************************** 602 // Field: [8] DMA_CLK_EN 603 // 604 // 605 // 0: Disable clock 606 // 1: Enable clock 607 // 608 // Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN 609 // 610 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 611 #define PRCM_SECDMACLKGS_DMA_CLK_EN 0x00000100 612 #define PRCM_SECDMACLKGS_DMA_CLK_EN_BITN 8 613 #define PRCM_SECDMACLKGS_DMA_CLK_EN_M 0x00000100 614 #define PRCM_SECDMACLKGS_DMA_CLK_EN_S 8 615 616 // Field: [2] PKA_CLK_EN 617 // 618 // 619 // 0: Disable clock 620 // 1: Enable clock 621 // 622 // Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN 623 // 624 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 625 #define PRCM_SECDMACLKGS_PKA_CLK_EN 0x00000004 626 #define PRCM_SECDMACLKGS_PKA_CLK_EN_BITN 2 627 #define PRCM_SECDMACLKGS_PKA_CLK_EN_M 0x00000004 628 #define PRCM_SECDMACLKGS_PKA_CLK_EN_S 2 629 630 // Field: [1] TRNG_CLK_EN 631 // 632 // 633 // 0: Disable clock 634 // 1: Enable clock 635 // 636 // Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN 637 // 638 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 639 #define PRCM_SECDMACLKGS_TRNG_CLK_EN 0x00000002 640 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_BITN 1 641 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_M 0x00000002 642 #define PRCM_SECDMACLKGS_TRNG_CLK_EN_S 1 643 644 // Field: [0] CRYPTO_CLK_EN 645 // 646 // 647 // 0: Disable clock 648 // 1: Enable clock 649 // 650 // Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN 651 // 652 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 653 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN 0x00000001 654 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_BITN 0 655 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_M 0x00000001 656 #define PRCM_SECDMACLKGS_CRYPTO_CLK_EN_S 0 657 658 //***************************************************************************** 659 // 660 // Register: PRCM_O_SECDMACLKGDS 661 // 662 //***************************************************************************** 663 // Field: [8] DMA_CLK_EN 664 // 665 // 666 // 0: Disable clock 667 // 1: Enable clock 668 // 669 // Can be forced on by SECDMACLKGR.DMA_AM_CLK_EN 670 // 671 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 672 #define PRCM_SECDMACLKGDS_DMA_CLK_EN 0x00000100 673 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_BITN 8 674 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_M 0x00000100 675 #define PRCM_SECDMACLKGDS_DMA_CLK_EN_S 8 676 677 // Field: [2] PKA_CLK_EN 678 // 679 // 680 // 0: Disable clock 681 // 1: Enable clock 682 // 683 // Can be forced on by SECDMACLKGR.PKA_AM_CLK_EN 684 // 685 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 686 #define PRCM_SECDMACLKGDS_PKA_CLK_EN 0x00000004 687 #define PRCM_SECDMACLKGDS_PKA_CLK_EN_BITN 2 688 #define PRCM_SECDMACLKGDS_PKA_CLK_EN_M 0x00000004 689 #define PRCM_SECDMACLKGDS_PKA_CLK_EN_S 2 690 691 // Field: [1] TRNG_CLK_EN 692 // 693 // 694 // 0: Disable clock 695 // 1: Enable clock 696 // 697 // SYSBUS clock will always run when enabled 698 // 699 // Can be forced on by SECDMACLKGR.TRNG_AM_CLK_EN 700 // 701 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 702 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN 0x00000002 703 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_BITN 1 704 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_M 0x00000002 705 #define PRCM_SECDMACLKGDS_TRNG_CLK_EN_S 1 706 707 // Field: [0] CRYPTO_CLK_EN 708 // 709 // 710 // 0: Disable clock 711 // 1: Enable clock 712 // 713 // SYSBUS clock will always run when enabled 714 // 715 // Can be forced on by SECDMACLKGR.CRYPTO_AM_CLK_EN 716 // 717 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 718 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN 0x00000001 719 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_BITN 0 720 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_M 0x00000001 721 #define PRCM_SECDMACLKGDS_CRYPTO_CLK_EN_S 0 722 723 //***************************************************************************** 724 // 725 // Register: PRCM_O_GPIOCLKGR 726 // 727 //***************************************************************************** 728 // Field: [8] AM_CLK_EN 729 // 730 // 731 // 0: No force 732 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 733 // 734 // Overrides CLK_EN, GPIOCLKGS.CLK_EN and GPIOCLKGDS.CLK_EN when enabled. 735 // 736 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 737 #define PRCM_GPIOCLKGR_AM_CLK_EN 0x00000100 738 #define PRCM_GPIOCLKGR_AM_CLK_EN_BITN 8 739 #define PRCM_GPIOCLKGR_AM_CLK_EN_M 0x00000100 740 #define PRCM_GPIOCLKGR_AM_CLK_EN_S 8 741 742 // Field: [0] CLK_EN 743 // 744 // 745 // 0: Disable clock 746 // 1: Enable clock 747 // 748 // Can be forced on by AM_CLK_EN 749 // 750 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 751 #define PRCM_GPIOCLKGR_CLK_EN 0x00000001 752 #define PRCM_GPIOCLKGR_CLK_EN_BITN 0 753 #define PRCM_GPIOCLKGR_CLK_EN_M 0x00000001 754 #define PRCM_GPIOCLKGR_CLK_EN_S 0 755 756 //***************************************************************************** 757 // 758 // Register: PRCM_O_GPIOCLKGS 759 // 760 //***************************************************************************** 761 // Field: [0] CLK_EN 762 // 763 // 764 // 0: Disable clock 765 // 1: Enable clock 766 // 767 // Can be forced on by GPIOCLKGR.AM_CLK_EN 768 // 769 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 770 #define PRCM_GPIOCLKGS_CLK_EN 0x00000001 771 #define PRCM_GPIOCLKGS_CLK_EN_BITN 0 772 #define PRCM_GPIOCLKGS_CLK_EN_M 0x00000001 773 #define PRCM_GPIOCLKGS_CLK_EN_S 0 774 775 //***************************************************************************** 776 // 777 // Register: PRCM_O_GPIOCLKGDS 778 // 779 //***************************************************************************** 780 // Field: [0] CLK_EN 781 // 782 // 783 // 0: Disable clock 784 // 1: Enable clock 785 // 786 // Can be forced on by GPIOCLKGR.AM_CLK_EN 787 // 788 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 789 #define PRCM_GPIOCLKGDS_CLK_EN 0x00000001 790 #define PRCM_GPIOCLKGDS_CLK_EN_BITN 0 791 #define PRCM_GPIOCLKGDS_CLK_EN_M 0x00000001 792 #define PRCM_GPIOCLKGDS_CLK_EN_S 0 793 794 //***************************************************************************** 795 // 796 // Register: PRCM_O_GPTCLKGR 797 // 798 //***************************************************************************** 799 // Field: [11:8] AM_CLK_EN 800 // 801 // Each bit below has the following meaning: 802 // 803 // 0: No force 804 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 805 // 806 // Overrides CLK_EN, GPTCLKGS.CLK_EN and GPTCLKGDS.CLK_EN when enabled. 807 // 808 // ENUMs can be combined 809 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 810 // ENUMs: 811 // AM_GPT3 Enable clock for GPT3 in all modes 812 // AM_GPT2 Enable clock for GPT2 in all modes 813 // AM_GPT1 Enable clock for GPT1 in all modes 814 // AM_GPT0 Enable clock for GPT0 in all modes 815 #define PRCM_GPTCLKGR_AM_CLK_EN_W 4 816 #define PRCM_GPTCLKGR_AM_CLK_EN_M 0x00000F00 817 #define PRCM_GPTCLKGR_AM_CLK_EN_S 8 818 #define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT3 0x00000800 819 #define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT2 0x00000400 820 #define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT1 0x00000200 821 #define PRCM_GPTCLKGR_AM_CLK_EN_AM_GPT0 0x00000100 822 823 // Field: [3:0] CLK_EN 824 // 825 // Each bit below has the following meaning: 826 // 827 // 0: Disable clock 828 // 1: Enable clock 829 // 830 // Can be forced on by AM_CLK_EN 831 // 832 // ENUMs can be combined 833 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 834 // ENUMs: 835 // GPT3 Enable clock for GPT3 836 // GPT2 Enable clock for GPT2 837 // GPT1 Enable clock for GPT1 838 // GPT0 Enable clock for GPT0 839 #define PRCM_GPTCLKGR_CLK_EN_W 4 840 #define PRCM_GPTCLKGR_CLK_EN_M 0x0000000F 841 #define PRCM_GPTCLKGR_CLK_EN_S 0 842 #define PRCM_GPTCLKGR_CLK_EN_GPT3 0x00000008 843 #define PRCM_GPTCLKGR_CLK_EN_GPT2 0x00000004 844 #define PRCM_GPTCLKGR_CLK_EN_GPT1 0x00000002 845 #define PRCM_GPTCLKGR_CLK_EN_GPT0 0x00000001 846 847 //***************************************************************************** 848 // 849 // Register: PRCM_O_GPTCLKGS 850 // 851 //***************************************************************************** 852 // Field: [3:0] CLK_EN 853 // 854 // Each bit below has the following meaning: 855 // 856 // 0: Disable clock 857 // 1: Enable clock 858 // 859 // Can be forced on by GPTCLKGR.AM_CLK_EN 860 // 861 // ENUMs can be combined 862 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 863 // ENUMs: 864 // GPT3 Enable clock for GPT3 865 // GPT2 Enable clock for GPT2 866 // GPT1 Enable clock for GPT1 867 // GPT0 Enable clock for GPT0 868 #define PRCM_GPTCLKGS_CLK_EN_W 4 869 #define PRCM_GPTCLKGS_CLK_EN_M 0x0000000F 870 #define PRCM_GPTCLKGS_CLK_EN_S 0 871 #define PRCM_GPTCLKGS_CLK_EN_GPT3 0x00000008 872 #define PRCM_GPTCLKGS_CLK_EN_GPT2 0x00000004 873 #define PRCM_GPTCLKGS_CLK_EN_GPT1 0x00000002 874 #define PRCM_GPTCLKGS_CLK_EN_GPT0 0x00000001 875 876 //***************************************************************************** 877 // 878 // Register: PRCM_O_GPTCLKGDS 879 // 880 //***************************************************************************** 881 // Field: [3:0] CLK_EN 882 // 883 // Each bit below has the following meaning: 884 // 885 // 0: Disable clock 886 // 1: Enable clock 887 // 888 // Can be forced on by GPTCLKGR.AM_CLK_EN 889 // 890 // ENUMs can be combined 891 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 892 // ENUMs: 893 // GPT3 Enable clock for GPT3 894 // GPT2 Enable clock for GPT2 895 // GPT1 Enable clock for GPT1 896 // GPT0 Enable clock for GPT0 897 #define PRCM_GPTCLKGDS_CLK_EN_W 4 898 #define PRCM_GPTCLKGDS_CLK_EN_M 0x0000000F 899 #define PRCM_GPTCLKGDS_CLK_EN_S 0 900 #define PRCM_GPTCLKGDS_CLK_EN_GPT3 0x00000008 901 #define PRCM_GPTCLKGDS_CLK_EN_GPT2 0x00000004 902 #define PRCM_GPTCLKGDS_CLK_EN_GPT1 0x00000002 903 #define PRCM_GPTCLKGDS_CLK_EN_GPT0 0x00000001 904 905 //***************************************************************************** 906 // 907 // Register: PRCM_O_I2CCLKGR 908 // 909 //***************************************************************************** 910 // Field: [8] AM_CLK_EN 911 // 912 // 913 // 0: No force 914 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 915 // 916 // Overrides CLK_EN, I2CCLKGS.CLK_EN and I2CCLKGDS.CLK_EN when enabled. 917 // 918 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 919 #define PRCM_I2CCLKGR_AM_CLK_EN 0x00000100 920 #define PRCM_I2CCLKGR_AM_CLK_EN_BITN 8 921 #define PRCM_I2CCLKGR_AM_CLK_EN_M 0x00000100 922 #define PRCM_I2CCLKGR_AM_CLK_EN_S 8 923 924 // Field: [0] CLK_EN 925 // 926 // 927 // 0: Disable clock 928 // 1: Enable clock 929 // 930 // Can be forced on by AM_CLK_EN 931 // 932 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 933 #define PRCM_I2CCLKGR_CLK_EN 0x00000001 934 #define PRCM_I2CCLKGR_CLK_EN_BITN 0 935 #define PRCM_I2CCLKGR_CLK_EN_M 0x00000001 936 #define PRCM_I2CCLKGR_CLK_EN_S 0 937 938 //***************************************************************************** 939 // 940 // Register: PRCM_O_I2CCLKGS 941 // 942 //***************************************************************************** 943 // Field: [0] CLK_EN 944 // 945 // 946 // 0: Disable clock 947 // 1: Enable clock 948 // 949 // Can be forced on by I2CCLKGR.AM_CLK_EN 950 // 951 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 952 #define PRCM_I2CCLKGS_CLK_EN 0x00000001 953 #define PRCM_I2CCLKGS_CLK_EN_BITN 0 954 #define PRCM_I2CCLKGS_CLK_EN_M 0x00000001 955 #define PRCM_I2CCLKGS_CLK_EN_S 0 956 957 //***************************************************************************** 958 // 959 // Register: PRCM_O_I2CCLKGDS 960 // 961 //***************************************************************************** 962 // Field: [0] CLK_EN 963 // 964 // 965 // 0: Disable clock 966 // 1: Enable clock 967 // 968 // Can be forced on by I2CCLKGR.AM_CLK_EN 969 // 970 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 971 #define PRCM_I2CCLKGDS_CLK_EN 0x00000001 972 #define PRCM_I2CCLKGDS_CLK_EN_BITN 0 973 #define PRCM_I2CCLKGDS_CLK_EN_M 0x00000001 974 #define PRCM_I2CCLKGDS_CLK_EN_S 0 975 976 //***************************************************************************** 977 // 978 // Register: PRCM_O_UARTCLKGR 979 // 980 //***************************************************************************** 981 // Field: [9:8] AM_CLK_EN 982 // 983 // 984 // 0: No force 985 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 986 // 987 // Overrides CLK_EN, UARTCLKGS.CLK_EN and UARTCLKGDS.CLK_EN when enabled. 988 // 989 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 990 // ENUMs: 991 // AM_UART1 Enable clock for UART1 992 // AM_UART0 Enable clock for UART0 993 #define PRCM_UARTCLKGR_AM_CLK_EN_W 2 994 #define PRCM_UARTCLKGR_AM_CLK_EN_M 0x00000300 995 #define PRCM_UARTCLKGR_AM_CLK_EN_S 8 996 #define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART1 0x00000200 997 #define PRCM_UARTCLKGR_AM_CLK_EN_AM_UART0 0x00000100 998 999 // Field: [1:0] CLK_EN 1000 // 1001 // 1002 // 0: Disable clock 1003 // 1: Enable clock 1004 // 1005 // Can be forced on by AM_CLK_EN 1006 // 1007 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1008 // ENUMs: 1009 // UART1 Enable clock for UART1 1010 // UART0 Enable clock for UART0 1011 #define PRCM_UARTCLKGR_CLK_EN_W 2 1012 #define PRCM_UARTCLKGR_CLK_EN_M 0x00000003 1013 #define PRCM_UARTCLKGR_CLK_EN_S 0 1014 #define PRCM_UARTCLKGR_CLK_EN_UART1 0x00000002 1015 #define PRCM_UARTCLKGR_CLK_EN_UART0 0x00000001 1016 1017 //***************************************************************************** 1018 // 1019 // Register: PRCM_O_UARTCLKGS 1020 // 1021 //***************************************************************************** 1022 // Field: [1:0] CLK_EN 1023 // 1024 // 1025 // 0: Disable clock 1026 // 1: Enable clock 1027 // 1028 // Can be forced on by UARTCLKGR.AM_CLK_EN 1029 // 1030 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1031 // ENUMs: 1032 // AM_UART1 Enable clock for UART1 1033 // AM_UART0 Enable clock for UART0 1034 #define PRCM_UARTCLKGS_CLK_EN_W 2 1035 #define PRCM_UARTCLKGS_CLK_EN_M 0x00000003 1036 #define PRCM_UARTCLKGS_CLK_EN_S 0 1037 #define PRCM_UARTCLKGS_CLK_EN_AM_UART1 0x00000002 1038 #define PRCM_UARTCLKGS_CLK_EN_AM_UART0 0x00000001 1039 1040 //***************************************************************************** 1041 // 1042 // Register: PRCM_O_UARTCLKGDS 1043 // 1044 //***************************************************************************** 1045 // Field: [1:0] CLK_EN 1046 // 1047 // 1048 // 0: Disable clock 1049 // 1: Enable clock 1050 // 1051 // Can be forced on by UARTCLKGR.AM_CLK_EN 1052 // 1053 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1054 // ENUMs: 1055 // AM_UART1 Enable clock for UART1 1056 // AM_UART0 Enable clock for UART0 1057 #define PRCM_UARTCLKGDS_CLK_EN_W 2 1058 #define PRCM_UARTCLKGDS_CLK_EN_M 0x00000003 1059 #define PRCM_UARTCLKGDS_CLK_EN_S 0 1060 #define PRCM_UARTCLKGDS_CLK_EN_AM_UART1 0x00000002 1061 #define PRCM_UARTCLKGDS_CLK_EN_AM_UART0 0x00000001 1062 1063 //***************************************************************************** 1064 // 1065 // Register: PRCM_O_SSICLKGR 1066 // 1067 //***************************************************************************** 1068 // Field: [9:8] AM_CLK_EN 1069 // 1070 // 1071 // 0: No force 1072 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 1073 // 1074 // Overrides CLK_EN, SSICLKGS.CLK_EN and SSICLKGDS.CLK_EN when enabled. 1075 // 1076 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1077 // ENUMs: 1078 // SSI1 Enable clock for SSI1 1079 // SSI0 Enable clock for SSI0 1080 #define PRCM_SSICLKGR_AM_CLK_EN_W 2 1081 #define PRCM_SSICLKGR_AM_CLK_EN_M 0x00000300 1082 #define PRCM_SSICLKGR_AM_CLK_EN_S 8 1083 #define PRCM_SSICLKGR_AM_CLK_EN_SSI1 0x00000200 1084 #define PRCM_SSICLKGR_AM_CLK_EN_SSI0 0x00000100 1085 1086 // Field: [1:0] CLK_EN 1087 // 1088 // 1089 // 0: Disable clock 1090 // 1: Enable clock 1091 // 1092 // Can be forced on by AM_CLK_EN 1093 // 1094 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1095 // ENUMs: 1096 // SSI1 Enable clock for SSI1 1097 // SSI0 Enable clock for SSI0 1098 #define PRCM_SSICLKGR_CLK_EN_W 2 1099 #define PRCM_SSICLKGR_CLK_EN_M 0x00000003 1100 #define PRCM_SSICLKGR_CLK_EN_S 0 1101 #define PRCM_SSICLKGR_CLK_EN_SSI1 0x00000002 1102 #define PRCM_SSICLKGR_CLK_EN_SSI0 0x00000001 1103 1104 //***************************************************************************** 1105 // 1106 // Register: PRCM_O_SSICLKGS 1107 // 1108 //***************************************************************************** 1109 // Field: [1:0] CLK_EN 1110 // 1111 // 1112 // 0: Disable clock 1113 // 1: Enable clock 1114 // 1115 // Can be forced on by SSICLKGR.AM_CLK_EN 1116 // 1117 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1118 // ENUMs: 1119 // SSI1 Enable clock for SSI1 1120 // SSI0 Enable clock for SSI0 1121 #define PRCM_SSICLKGS_CLK_EN_W 2 1122 #define PRCM_SSICLKGS_CLK_EN_M 0x00000003 1123 #define PRCM_SSICLKGS_CLK_EN_S 0 1124 #define PRCM_SSICLKGS_CLK_EN_SSI1 0x00000002 1125 #define PRCM_SSICLKGS_CLK_EN_SSI0 0x00000001 1126 1127 //***************************************************************************** 1128 // 1129 // Register: PRCM_O_SSICLKGDS 1130 // 1131 //***************************************************************************** 1132 // Field: [1:0] CLK_EN 1133 // 1134 // 1135 // 0: Disable clock 1136 // 1: Enable clock 1137 // 1138 // Can be forced on by SSICLKGR.AM_CLK_EN 1139 // 1140 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1141 // ENUMs: 1142 // SSI1 Enable clock for SSI1 1143 // SSI0 Enable clock for SSI0 1144 #define PRCM_SSICLKGDS_CLK_EN_W 2 1145 #define PRCM_SSICLKGDS_CLK_EN_M 0x00000003 1146 #define PRCM_SSICLKGDS_CLK_EN_S 0 1147 #define PRCM_SSICLKGDS_CLK_EN_SSI1 0x00000002 1148 #define PRCM_SSICLKGDS_CLK_EN_SSI0 0x00000001 1149 1150 //***************************************************************************** 1151 // 1152 // Register: PRCM_O_I2SCLKGR 1153 // 1154 //***************************************************************************** 1155 // Field: [8] AM_CLK_EN 1156 // 1157 // 1158 // 0: No force 1159 // 1: Force clock on for all modes (Run, Sleep and Deep Sleep) 1160 // 1161 // Overrides CLK_EN, I2SCLKGS.CLK_EN and I2SCLKGDS.CLK_EN when enabled. 1162 // SYSBUS clock will always run when enabled 1163 // 1164 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1165 #define PRCM_I2SCLKGR_AM_CLK_EN 0x00000100 1166 #define PRCM_I2SCLKGR_AM_CLK_EN_BITN 8 1167 #define PRCM_I2SCLKGR_AM_CLK_EN_M 0x00000100 1168 #define PRCM_I2SCLKGR_AM_CLK_EN_S 8 1169 1170 // Field: [0] CLK_EN 1171 // 1172 // 1173 // 0: Disable clock 1174 // 1: Enable clock 1175 // 1176 // Can be forced on by AM_CLK_EN 1177 // 1178 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1179 #define PRCM_I2SCLKGR_CLK_EN 0x00000001 1180 #define PRCM_I2SCLKGR_CLK_EN_BITN 0 1181 #define PRCM_I2SCLKGR_CLK_EN_M 0x00000001 1182 #define PRCM_I2SCLKGR_CLK_EN_S 0 1183 1184 //***************************************************************************** 1185 // 1186 // Register: PRCM_O_I2SCLKGS 1187 // 1188 //***************************************************************************** 1189 // Field: [0] CLK_EN 1190 // 1191 // 1192 // 0: Disable clock 1193 // 1: Enable clock 1194 // 1195 // Can be forced on by I2SCLKGR.AM_CLK_EN 1196 // 1197 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1198 #define PRCM_I2SCLKGS_CLK_EN 0x00000001 1199 #define PRCM_I2SCLKGS_CLK_EN_BITN 0 1200 #define PRCM_I2SCLKGS_CLK_EN_M 0x00000001 1201 #define PRCM_I2SCLKGS_CLK_EN_S 0 1202 1203 //***************************************************************************** 1204 // 1205 // Register: PRCM_O_I2SCLKGDS 1206 // 1207 //***************************************************************************** 1208 // Field: [0] CLK_EN 1209 // 1210 // 1211 // 0: Disable clock 1212 // 1: Enable clock 1213 // 1214 // SYSBUS clock will always run when enabled 1215 // 1216 // Can be forced on by I2SCLKGR.AM_CLK_EN 1217 // 1218 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1219 #define PRCM_I2SCLKGDS_CLK_EN 0x00000001 1220 #define PRCM_I2SCLKGDS_CLK_EN_BITN 0 1221 #define PRCM_I2SCLKGDS_CLK_EN_M 0x00000001 1222 #define PRCM_I2SCLKGDS_CLK_EN_S 0 1223 1224 //***************************************************************************** 1225 // 1226 // Register: PRCM_O_SYSBUSCLKDIV 1227 // 1228 //***************************************************************************** 1229 // Field: [2:0] RATIO 1230 // 1231 // Internal. Only to be used through TI provided API. 1232 // ENUMs: 1233 // DIV2 Internal. Only to be used through TI provided API. 1234 // DIV1 Internal. Only to be used through TI provided API. 1235 #define PRCM_SYSBUSCLKDIV_RATIO_W 3 1236 #define PRCM_SYSBUSCLKDIV_RATIO_M 0x00000007 1237 #define PRCM_SYSBUSCLKDIV_RATIO_S 0 1238 #define PRCM_SYSBUSCLKDIV_RATIO_DIV2 0x00000001 1239 #define PRCM_SYSBUSCLKDIV_RATIO_DIV1 0x00000000 1240 1241 //***************************************************************************** 1242 // 1243 // Register: PRCM_O_CPUCLKDIV 1244 // 1245 //***************************************************************************** 1246 // Field: [0] RATIO 1247 // 1248 // Internal. Only to be used through TI provided API. 1249 // ENUMs: 1250 // DIV2 Internal. Only to be used through TI provided API. 1251 // DIV1 Internal. Only to be used through TI provided API. 1252 #define PRCM_CPUCLKDIV_RATIO 0x00000001 1253 #define PRCM_CPUCLKDIV_RATIO_BITN 0 1254 #define PRCM_CPUCLKDIV_RATIO_M 0x00000001 1255 #define PRCM_CPUCLKDIV_RATIO_S 0 1256 #define PRCM_CPUCLKDIV_RATIO_DIV2 0x00000001 1257 #define PRCM_CPUCLKDIV_RATIO_DIV1 0x00000000 1258 1259 //***************************************************************************** 1260 // 1261 // Register: PRCM_O_PERBUSCPUCLKDIV 1262 // 1263 //***************************************************************************** 1264 // Field: [3:0] RATIO 1265 // 1266 // Internal. Only to be used through TI provided API. 1267 // ENUMs: 1268 // DIV256 Internal. Only to be used through TI provided API. 1269 // DIV128 Internal. Only to be used through TI provided API. 1270 // DIV64 Internal. Only to be used through TI provided API. 1271 // DIV32 Internal. Only to be used through TI provided API. 1272 // DIV16 Internal. Only to be used through TI provided API. 1273 // DIV8 Internal. Only to be used through TI provided API. 1274 // DIV4 Internal. Only to be used through TI provided API. 1275 // DIV2 Internal. Only to be used through TI provided API. 1276 // DIV1 Internal. Only to be used through TI provided API. 1277 #define PRCM_PERBUSCPUCLKDIV_RATIO_W 4 1278 #define PRCM_PERBUSCPUCLKDIV_RATIO_M 0x0000000F 1279 #define PRCM_PERBUSCPUCLKDIV_RATIO_S 0 1280 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV256 0x00000008 1281 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV128 0x00000007 1282 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV64 0x00000006 1283 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV32 0x00000005 1284 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV16 0x00000004 1285 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV8 0x00000003 1286 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV4 0x00000002 1287 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV2 0x00000001 1288 #define PRCM_PERBUSCPUCLKDIV_RATIO_DIV1 0x00000000 1289 1290 //***************************************************************************** 1291 // 1292 // Register: PRCM_O_PERDMACLKDIV 1293 // 1294 //***************************************************************************** 1295 // Field: [3:0] RATIO 1296 // 1297 // Internal. Only to be used through TI provided API. 1298 // ENUMs: 1299 // DIV256 Internal. Only to be used through TI provided API. 1300 // DIV128 Internal. Only to be used through TI provided API. 1301 // DIV64 Internal. Only to be used through TI provided API. 1302 // DIV32 Internal. Only to be used through TI provided API. 1303 // DIV16 Internal. Only to be used through TI provided API. 1304 // DIV8 Internal. Only to be used through TI provided API. 1305 // DIV4 Internal. Only to be used through TI provided API. 1306 // DIV2 Internal. Only to be used through TI provided API. 1307 // DIV1 Internal. Only to be used through TI provided API. 1308 #define PRCM_PERDMACLKDIV_RATIO_W 4 1309 #define PRCM_PERDMACLKDIV_RATIO_M 0x0000000F 1310 #define PRCM_PERDMACLKDIV_RATIO_S 0 1311 #define PRCM_PERDMACLKDIV_RATIO_DIV256 0x00000008 1312 #define PRCM_PERDMACLKDIV_RATIO_DIV128 0x00000007 1313 #define PRCM_PERDMACLKDIV_RATIO_DIV64 0x00000006 1314 #define PRCM_PERDMACLKDIV_RATIO_DIV32 0x00000005 1315 #define PRCM_PERDMACLKDIV_RATIO_DIV16 0x00000004 1316 #define PRCM_PERDMACLKDIV_RATIO_DIV8 0x00000003 1317 #define PRCM_PERDMACLKDIV_RATIO_DIV4 0x00000002 1318 #define PRCM_PERDMACLKDIV_RATIO_DIV2 0x00000001 1319 #define PRCM_PERDMACLKDIV_RATIO_DIV1 0x00000000 1320 1321 //***************************************************************************** 1322 // 1323 // Register: PRCM_O_I2SBCLKSEL 1324 // 1325 //***************************************************************************** 1326 // Field: [0] SRC 1327 // 1328 // BCLK source selector 1329 // 1330 // 0: Use external BCLK 1331 // 1: Use internally generated clock 1332 // 1333 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1334 #define PRCM_I2SBCLKSEL_SRC 0x00000001 1335 #define PRCM_I2SBCLKSEL_SRC_BITN 0 1336 #define PRCM_I2SBCLKSEL_SRC_M 0x00000001 1337 #define PRCM_I2SBCLKSEL_SRC_S 0 1338 1339 //***************************************************************************** 1340 // 1341 // Register: PRCM_O_GPTCLKDIV 1342 // 1343 //***************************************************************************** 1344 // Field: [3:0] RATIO 1345 // 1346 // Scalar used for GPTs. The division rate will be constant and ungated for Run 1347 // / Sleep / DeepSleep mode. For changes to take effect, CLKLOADCTL.LOAD 1348 // needs to be written Other values are not supported. 1349 // ENUMs: 1350 // DIV256 Divide by 256 1351 // DIV128 Divide by 128 1352 // DIV64 Divide by 64 1353 // DIV32 Divide by 32 1354 // DIV16 Divide by 16 1355 // DIV8 Divide by 8 1356 // DIV4 Divide by 4 1357 // DIV2 Divide by 2 1358 // DIV1 Divide by 1 1359 #define PRCM_GPTCLKDIV_RATIO_W 4 1360 #define PRCM_GPTCLKDIV_RATIO_M 0x0000000F 1361 #define PRCM_GPTCLKDIV_RATIO_S 0 1362 #define PRCM_GPTCLKDIV_RATIO_DIV256 0x00000008 1363 #define PRCM_GPTCLKDIV_RATIO_DIV128 0x00000007 1364 #define PRCM_GPTCLKDIV_RATIO_DIV64 0x00000006 1365 #define PRCM_GPTCLKDIV_RATIO_DIV32 0x00000005 1366 #define PRCM_GPTCLKDIV_RATIO_DIV16 0x00000004 1367 #define PRCM_GPTCLKDIV_RATIO_DIV8 0x00000003 1368 #define PRCM_GPTCLKDIV_RATIO_DIV4 0x00000002 1369 #define PRCM_GPTCLKDIV_RATIO_DIV2 0x00000001 1370 #define PRCM_GPTCLKDIV_RATIO_DIV1 0x00000000 1371 1372 //***************************************************************************** 1373 // 1374 // Register: PRCM_O_I2SCLKCTL 1375 // 1376 //***************************************************************************** 1377 // Field: [3] SMPL_ON_POSEDGE 1378 // 1379 // On the I2S serial interface, data and WCLK is sampled and clocked out on 1380 // opposite edges of BCLK. 1381 // 1382 // 0 - data and WCLK are sampled on the negative edge and clocked out on the 1383 // positive edge. 1384 // 1 - data and WCLK are sampled on the positive edge and clocked out on the 1385 // negative edge. 1386 // 1387 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1388 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE 0x00000008 1389 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_BITN 3 1390 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_M 0x00000008 1391 #define PRCM_I2SCLKCTL_SMPL_ON_POSEDGE_S 3 1392 1393 // Field: [2:1] WCLK_PHASE 1394 // 1395 // Decides how the WCLK division ratio is calculated and used to generate 1396 // different duty cycles (See I2SWCLKDIV.WDIV). 1397 // 1398 // 0: Single phase 1399 // 1: Dual phase 1400 // 2: User Defined 1401 // 3: Reserved/Undefined 1402 // 1403 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1404 #define PRCM_I2SCLKCTL_WCLK_PHASE_W 2 1405 #define PRCM_I2SCLKCTL_WCLK_PHASE_M 0x00000006 1406 #define PRCM_I2SCLKCTL_WCLK_PHASE_S 1 1407 1408 // Field: [0] EN 1409 // 1410 // 1411 // 0: MCLK, BCLK and WCLK will be static low 1412 // 1: Enables the generation of MCLK, BCLK and WCLK 1413 // 1414 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1415 #define PRCM_I2SCLKCTL_EN 0x00000001 1416 #define PRCM_I2SCLKCTL_EN_BITN 0 1417 #define PRCM_I2SCLKCTL_EN_M 0x00000001 1418 #define PRCM_I2SCLKCTL_EN_S 0 1419 1420 //***************************************************************************** 1421 // 1422 // Register: PRCM_O_I2SMCLKDIV 1423 // 1424 //***************************************************************************** 1425 // Field: [9:0] MDIV 1426 // 1427 // An unsigned factor of the division ratio used to generate MCLK [2-1024]: 1428 // 1429 // MCLK = MCUCLK/MDIV[Hz] 1430 // MCUCLK is 48MHz. 1431 // 1432 // A value of 0 is interpreted as 1024. 1433 // A value of 1 is invalid. 1434 // If MDIV is odd the low phase of the clock is one MCUCLK period longer than 1435 // the high phase. 1436 // 1437 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1438 #define PRCM_I2SMCLKDIV_MDIV_W 10 1439 #define PRCM_I2SMCLKDIV_MDIV_M 0x000003FF 1440 #define PRCM_I2SMCLKDIV_MDIV_S 0 1441 1442 //***************************************************************************** 1443 // 1444 // Register: PRCM_O_I2SBCLKDIV 1445 // 1446 //***************************************************************************** 1447 // Field: [9:0] BDIV 1448 // 1449 // An unsigned factor of the division ratio used to generate I2S BCLK [2-1024]: 1450 // 1451 // BCLK = MCUCLK/BDIV[Hz] 1452 // MCUCLK is 48MHz. 1453 // 1454 // A value of 0 is interpreted as 1024. 1455 // A value of 1 is invalid. 1456 // If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 0, the low phase of the clock 1457 // is one MCUCLK period longer than the high phase. 1458 // If BDIV is odd and I2SCLKCTL.SMPL_ON_POSEDGE = 1 , the high phase of the 1459 // clock is one MCUCLK period longer than the low phase. 1460 // 1461 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1462 #define PRCM_I2SBCLKDIV_BDIV_W 10 1463 #define PRCM_I2SBCLKDIV_BDIV_M 0x000003FF 1464 #define PRCM_I2SBCLKDIV_BDIV_S 0 1465 1466 //***************************************************************************** 1467 // 1468 // Register: PRCM_O_I2SWCLKDIV 1469 // 1470 //***************************************************************************** 1471 // Field: [15:0] WDIV 1472 // 1473 // If I2SCLKCTL.WCLK_PHASE = 0, Single phase. 1474 // WCLK is high one BCLK period and low WDIV[9:0] (unsigned, [1-1023]) BCLK 1475 // periods. 1476 // 1477 // WCLK = MCUCLK / BDIV*(WDIV[9:0] + 1) [Hz] 1478 // MCUCLK is 48MHz. 1479 // 1480 // If I2SCLKCTL.WCLK_PHASE = 1, Dual phase. 1481 // Each phase on WCLK (50% duty cycle) is WDIV[9:0] (unsigned, [1-1023]) BCLK 1482 // periods. 1483 // 1484 // WCLK = MCUCLK / BDIV*(2*WDIV[9:0]) [Hz] 1485 // 1486 // If I2SCLKCTL.WCLK_PHASE = 2, User defined. 1487 // WCLK is high WDIV[7:0] (unsigned, [1-255]) BCLK periods and low WDIV[15:8] 1488 // (unsigned, [1-255]) BCLK periods. 1489 // 1490 // WCLK = MCUCLK / (BDIV*(WDIV[7:0] + WDIV[15:8]) [Hz] 1491 // 1492 // For changes to take effect, CLKLOADCTL.LOAD needs to be written 1493 #define PRCM_I2SWCLKDIV_WDIV_W 16 1494 #define PRCM_I2SWCLKDIV_WDIV_M 0x0000FFFF 1495 #define PRCM_I2SWCLKDIV_WDIV_S 0 1496 1497 //***************************************************************************** 1498 // 1499 // Register: PRCM_O_RESETSECDMA 1500 // 1501 //***************************************************************************** 1502 // Field: [8] DMA 1503 // 1504 // Write 1 to reset. HW cleared. 1505 // Acess will only have effect when PERIPH power domain is on, 1506 // PDSTAT0.PERIPH_ON = 1 1507 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1508 // activated while executing from flash. This means one cannot execute from 1509 // flash when using the SW reset. 1510 #define PRCM_RESETSECDMA_DMA 0x00000100 1511 #define PRCM_RESETSECDMA_DMA_BITN 8 1512 #define PRCM_RESETSECDMA_DMA_M 0x00000100 1513 #define PRCM_RESETSECDMA_DMA_S 8 1514 1515 // Field: [2] PKA 1516 // 1517 // Write 1 to reset. HW cleared. 1518 // Acess will only have effect when PERIPH power domain is on, 1519 // PDSTAT0.PERIPH_ON = 1 1520 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1521 // activated while executing from flash. This means one cannot execute from 1522 // flash when using the SW reset. 1523 #define PRCM_RESETSECDMA_PKA 0x00000004 1524 #define PRCM_RESETSECDMA_PKA_BITN 2 1525 #define PRCM_RESETSECDMA_PKA_M 0x00000004 1526 #define PRCM_RESETSECDMA_PKA_S 2 1527 1528 // Field: [1] TRNG 1529 // 1530 // Write 1 to reset. HW cleared. 1531 // Acess will only have effect when PERIPH power domain is on, 1532 // PDSTAT0.PERIPH_ON = 1 1533 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1534 // activated while executing from flash. This means one cannot execute from 1535 // flash when using the SW reset. 1536 #define PRCM_RESETSECDMA_TRNG 0x00000002 1537 #define PRCM_RESETSECDMA_TRNG_BITN 1 1538 #define PRCM_RESETSECDMA_TRNG_M 0x00000002 1539 #define PRCM_RESETSECDMA_TRNG_S 1 1540 1541 // Field: [0] CRYPTO 1542 // 1543 // Write 1 to reset. HW cleared. 1544 // Acess will only have effect when PERIPH power domain is on, 1545 // PDSTAT0.PERIPH_ON = 1 1546 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1547 // activated while executing from flash. This means one cannot execute from 1548 // flash when using the SW reset. 1549 #define PRCM_RESETSECDMA_CRYPTO 0x00000001 1550 #define PRCM_RESETSECDMA_CRYPTO_BITN 0 1551 #define PRCM_RESETSECDMA_CRYPTO_M 0x00000001 1552 #define PRCM_RESETSECDMA_CRYPTO_S 0 1553 1554 //***************************************************************************** 1555 // 1556 // Register: PRCM_O_RESETGPIO 1557 // 1558 //***************************************************************************** 1559 // Field: [0] GPIO 1560 // 1561 // 1562 // 0: No action 1563 // 1: Reset GPIO. HW cleared. 1564 // 1565 // Acess will only have effect when PERIPH power domain is on, 1566 // PDSTAT0.PERIPH_ON = 1 1567 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1568 // activated while executing from flash. This means one cannot execute from 1569 // flash when using the SW reset. 1570 #define PRCM_RESETGPIO_GPIO 0x00000001 1571 #define PRCM_RESETGPIO_GPIO_BITN 0 1572 #define PRCM_RESETGPIO_GPIO_M 0x00000001 1573 #define PRCM_RESETGPIO_GPIO_S 0 1574 1575 //***************************************************************************** 1576 // 1577 // Register: PRCM_O_RESETGPT 1578 // 1579 //***************************************************************************** 1580 // Field: [0] GPT 1581 // 1582 // 1583 // 0: No action 1584 // 1: Reset all GPTs. HW cleared. 1585 // 1586 // Acess will only have effect when PERIPH power domain is on, 1587 // PDSTAT0.PERIPH_ON = 1 1588 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1589 // activated while executing from flash. This means one cannot execute from 1590 // flash when using the SW reset. 1591 #define PRCM_RESETGPT_GPT 0x00000001 1592 #define PRCM_RESETGPT_GPT_BITN 0 1593 #define PRCM_RESETGPT_GPT_M 0x00000001 1594 #define PRCM_RESETGPT_GPT_S 0 1595 1596 //***************************************************************************** 1597 // 1598 // Register: PRCM_O_RESETI2C 1599 // 1600 //***************************************************************************** 1601 // Field: [0] I2C 1602 // 1603 // 1604 // 0: No action 1605 // 1: Reset I2C. HW cleared. 1606 // 1607 // Acess will only have effect when SERIAL power domain is on, 1608 // PDSTAT0.SERIAL_ON = 1 1609 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1610 // activated while executing from flash. This means one cannot execute from 1611 // flash when using the SW reset. 1612 #define PRCM_RESETI2C_I2C 0x00000001 1613 #define PRCM_RESETI2C_I2C_BITN 0 1614 #define PRCM_RESETI2C_I2C_M 0x00000001 1615 #define PRCM_RESETI2C_I2C_S 0 1616 1617 //***************************************************************************** 1618 // 1619 // Register: PRCM_O_RESETUART 1620 // 1621 //***************************************************************************** 1622 // Field: [1] UART1 1623 // 1624 // 1625 // 0: No action 1626 // 1: Reset UART1. HW cleared. 1627 // 1628 // Acess will only have effect when PERIPH power domain is on, 1629 // PDSTAT0.PERIPH_ON = 1 1630 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1631 // activated while executing from flash. This means one cannot execute from 1632 // flash when using the SW reset. 1633 #define PRCM_RESETUART_UART1 0x00000002 1634 #define PRCM_RESETUART_UART1_BITN 1 1635 #define PRCM_RESETUART_UART1_M 0x00000002 1636 #define PRCM_RESETUART_UART1_S 1 1637 1638 // Field: [0] UART0 1639 // 1640 // 1641 // 0: No action 1642 // 1: Reset UART0. HW cleared. 1643 // 1644 // Acess will only have effect when SERIAL power domain is on, 1645 // PDSTAT0.SERIAL_ON = 1 1646 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1647 // activated while executing from flash. This means one cannot execute from 1648 // flash when using the SW reset. 1649 #define PRCM_RESETUART_UART0 0x00000001 1650 #define PRCM_RESETUART_UART0_BITN 0 1651 #define PRCM_RESETUART_UART0_M 0x00000001 1652 #define PRCM_RESETUART_UART0_S 0 1653 1654 //***************************************************************************** 1655 // 1656 // Register: PRCM_O_RESETSSI 1657 // 1658 //***************************************************************************** 1659 // Field: [1:0] SSI 1660 // 1661 // SSI 0: 1662 // 1663 // 0: No action 1664 // 1: Reset SSI. HW cleared. 1665 // 1666 // Acess will only have effect when SERIAL power domain is on, 1667 // PDSTAT0.SERIAL_ON = 1 1668 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1669 // activated while executing from flash. This means one cannot execute from 1670 // flash when using the SW reset. 1671 // 1672 // SSI 1: 1673 // 1674 // 0: No action 1675 // 1: Reset SSI. HW cleared. 1676 // 1677 // Acess will only have effect when PERIPH power domain is on, 1678 // PDSTAT0.PERIPH_ON = 1 1679 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1680 // activated while executing from flash. This means one cannot execute from 1681 // flash when using the SW reset. 1682 #define PRCM_RESETSSI_SSI_W 2 1683 #define PRCM_RESETSSI_SSI_M 0x00000003 1684 #define PRCM_RESETSSI_SSI_S 0 1685 1686 //***************************************************************************** 1687 // 1688 // Register: PRCM_O_RESETI2S 1689 // 1690 //***************************************************************************** 1691 // Field: [0] I2S 1692 // 1693 // 1694 // 0: No action 1695 // 1: Reset module. HW cleared. 1696 // 1697 // Acess will only have effect when PERIPH power domain is on, 1698 // PDSTAT0.PERIPH_ON = 1 1699 // Before writing set FLASH:CFG.DIS_READACCESS = 1 to ensure the reset is not 1700 // activated while executing from flash. This means one cannot execute from 1701 // flash when using the SW reset. 1702 #define PRCM_RESETI2S_I2S 0x00000001 1703 #define PRCM_RESETI2S_I2S_BITN 0 1704 #define PRCM_RESETI2S_I2S_M 0x00000001 1705 #define PRCM_RESETI2S_I2S_S 0 1706 1707 //***************************************************************************** 1708 // 1709 // Register: PRCM_O_PDCTL0 1710 // 1711 //***************************************************************************** 1712 // Field: [2] PERIPH_ON 1713 // 1714 // PERIPH Power domain. 1715 // 1716 // 0: PERIPH power domain is powered down 1717 // 1: PERIPH power domain is powered up 1718 #define PRCM_PDCTL0_PERIPH_ON 0x00000004 1719 #define PRCM_PDCTL0_PERIPH_ON_BITN 2 1720 #define PRCM_PDCTL0_PERIPH_ON_M 0x00000004 1721 #define PRCM_PDCTL0_PERIPH_ON_S 2 1722 1723 // Field: [1] SERIAL_ON 1724 // 1725 // SERIAL Power domain. 1726 // 1727 // 0: SERIAL power domain is powered down 1728 // 1: SERIAL power domain is powered up 1729 #define PRCM_PDCTL0_SERIAL_ON 0x00000002 1730 #define PRCM_PDCTL0_SERIAL_ON_BITN 1 1731 #define PRCM_PDCTL0_SERIAL_ON_M 0x00000002 1732 #define PRCM_PDCTL0_SERIAL_ON_S 1 1733 1734 // Field: [0] RFC_ON 1735 // 1736 // 1737 // 0: RFC power domain powered off if also PDCTL1.RFC_ON = 0 1738 // 1: RFC power domain powered on 1739 #define PRCM_PDCTL0_RFC_ON 0x00000001 1740 #define PRCM_PDCTL0_RFC_ON_BITN 0 1741 #define PRCM_PDCTL0_RFC_ON_M 0x00000001 1742 #define PRCM_PDCTL0_RFC_ON_S 0 1743 1744 //***************************************************************************** 1745 // 1746 // Register: PRCM_O_PDCTL0RFC 1747 // 1748 //***************************************************************************** 1749 // Field: [0] ON 1750 // 1751 // Alias for PDCTL0.RFC_ON 1752 #define PRCM_PDCTL0RFC_ON 0x00000001 1753 #define PRCM_PDCTL0RFC_ON_BITN 0 1754 #define PRCM_PDCTL0RFC_ON_M 0x00000001 1755 #define PRCM_PDCTL0RFC_ON_S 0 1756 1757 //***************************************************************************** 1758 // 1759 // Register: PRCM_O_PDCTL0SERIAL 1760 // 1761 //***************************************************************************** 1762 // Field: [0] ON 1763 // 1764 // Alias for PDCTL0.SERIAL_ON 1765 #define PRCM_PDCTL0SERIAL_ON 0x00000001 1766 #define PRCM_PDCTL0SERIAL_ON_BITN 0 1767 #define PRCM_PDCTL0SERIAL_ON_M 0x00000001 1768 #define PRCM_PDCTL0SERIAL_ON_S 0 1769 1770 //***************************************************************************** 1771 // 1772 // Register: PRCM_O_PDCTL0PERIPH 1773 // 1774 //***************************************************************************** 1775 // Field: [0] ON 1776 // 1777 // Alias for PDCTL0.PERIPH_ON 1778 #define PRCM_PDCTL0PERIPH_ON 0x00000001 1779 #define PRCM_PDCTL0PERIPH_ON_BITN 0 1780 #define PRCM_PDCTL0PERIPH_ON_M 0x00000001 1781 #define PRCM_PDCTL0PERIPH_ON_S 0 1782 1783 //***************************************************************************** 1784 // 1785 // Register: PRCM_O_PDSTAT0 1786 // 1787 //***************************************************************************** 1788 // Field: [2] PERIPH_ON 1789 // 1790 // PERIPH Power domain. 1791 // 1792 // 0: Domain may be powered down 1793 // 1: Domain powered up (guaranteed) 1794 #define PRCM_PDSTAT0_PERIPH_ON 0x00000004 1795 #define PRCM_PDSTAT0_PERIPH_ON_BITN 2 1796 #define PRCM_PDSTAT0_PERIPH_ON_M 0x00000004 1797 #define PRCM_PDSTAT0_PERIPH_ON_S 2 1798 1799 // Field: [1] SERIAL_ON 1800 // 1801 // SERIAL Power domain. 1802 // 1803 // 0: Domain may be powered down 1804 // 1: Domain powered up (guaranteed) 1805 #define PRCM_PDSTAT0_SERIAL_ON 0x00000002 1806 #define PRCM_PDSTAT0_SERIAL_ON_BITN 1 1807 #define PRCM_PDSTAT0_SERIAL_ON_M 0x00000002 1808 #define PRCM_PDSTAT0_SERIAL_ON_S 1 1809 1810 // Field: [0] RFC_ON 1811 // 1812 // RFC Power domain 1813 // 1814 // 0: Domain may be powered down 1815 // 1: Domain powered up (guaranteed) 1816 #define PRCM_PDSTAT0_RFC_ON 0x00000001 1817 #define PRCM_PDSTAT0_RFC_ON_BITN 0 1818 #define PRCM_PDSTAT0_RFC_ON_M 0x00000001 1819 #define PRCM_PDSTAT0_RFC_ON_S 0 1820 1821 //***************************************************************************** 1822 // 1823 // Register: PRCM_O_PDSTAT0RFC 1824 // 1825 //***************************************************************************** 1826 // Field: [0] ON 1827 // 1828 // Alias for PDSTAT0.RFC_ON 1829 #define PRCM_PDSTAT0RFC_ON 0x00000001 1830 #define PRCM_PDSTAT0RFC_ON_BITN 0 1831 #define PRCM_PDSTAT0RFC_ON_M 0x00000001 1832 #define PRCM_PDSTAT0RFC_ON_S 0 1833 1834 //***************************************************************************** 1835 // 1836 // Register: PRCM_O_PDSTAT0SERIAL 1837 // 1838 //***************************************************************************** 1839 // Field: [0] ON 1840 // 1841 // Alias for PDSTAT0.SERIAL_ON 1842 #define PRCM_PDSTAT0SERIAL_ON 0x00000001 1843 #define PRCM_PDSTAT0SERIAL_ON_BITN 0 1844 #define PRCM_PDSTAT0SERIAL_ON_M 0x00000001 1845 #define PRCM_PDSTAT0SERIAL_ON_S 0 1846 1847 //***************************************************************************** 1848 // 1849 // Register: PRCM_O_PDSTAT0PERIPH 1850 // 1851 //***************************************************************************** 1852 // Field: [0] ON 1853 // 1854 // Alias for PDSTAT0.PERIPH_ON 1855 #define PRCM_PDSTAT0PERIPH_ON 0x00000001 1856 #define PRCM_PDSTAT0PERIPH_ON_BITN 0 1857 #define PRCM_PDSTAT0PERIPH_ON_M 0x00000001 1858 #define PRCM_PDSTAT0PERIPH_ON_S 0 1859 1860 //***************************************************************************** 1861 // 1862 // Register: PRCM_O_PDCTL1 1863 // 1864 //***************************************************************************** 1865 // Field: [4:3] VIMS_MODE 1866 // 1867 // 1868 // 00: VIMS power domain is only powered when CPU power domain is powered. 1869 // 01: VIMS power domain is powered whenever the BUS power domain is powered. 1870 // 1X: Block power up of VIMS power domain at next wake up. This mode only has 1871 // effect when VIMS power domain is not powered. Used for Autonomous RF Core. 1872 #define PRCM_PDCTL1_VIMS_MODE_W 2 1873 #define PRCM_PDCTL1_VIMS_MODE_M 0x00000018 1874 #define PRCM_PDCTL1_VIMS_MODE_S 3 1875 1876 // Field: [2] RFC_ON 1877 // 1878 // 0: RFC power domain powered off if also PDCTL0.RFC_ON = 0 1: RFC power 1879 // domain powered on Bit shall be used by RFC in autonomous mode but there is 1880 // no HW restrictions fom system CPU to access the bit. 1881 #define PRCM_PDCTL1_RFC_ON 0x00000004 1882 #define PRCM_PDCTL1_RFC_ON_BITN 2 1883 #define PRCM_PDCTL1_RFC_ON_M 0x00000004 1884 #define PRCM_PDCTL1_RFC_ON_S 2 1885 1886 // Field: [1] CPU_ON 1887 // 1888 // 1889 // 0: Causes a power down of the CPU power domain when system CPU indicates it 1890 // is idle. 1891 // 1: Initiates power-on of the CPU power domain. 1892 // 1893 // This bit is automatically set by a WIC power-on event. 1894 #define PRCM_PDCTL1_CPU_ON 0x00000002 1895 #define PRCM_PDCTL1_CPU_ON_BITN 1 1896 #define PRCM_PDCTL1_CPU_ON_M 0x00000002 1897 #define PRCM_PDCTL1_CPU_ON_S 1 1898 1899 //***************************************************************************** 1900 // 1901 // Register: PRCM_O_PDCTL1CPU 1902 // 1903 //***************************************************************************** 1904 // Field: [0] ON 1905 // 1906 // This is an alias for PDCTL1.CPU_ON 1907 #define PRCM_PDCTL1CPU_ON 0x00000001 1908 #define PRCM_PDCTL1CPU_ON_BITN 0 1909 #define PRCM_PDCTL1CPU_ON_M 0x00000001 1910 #define PRCM_PDCTL1CPU_ON_S 0 1911 1912 //***************************************************************************** 1913 // 1914 // Register: PRCM_O_PDCTL1RFC 1915 // 1916 //***************************************************************************** 1917 // Field: [0] ON 1918 // 1919 // This is an alias for PDCTL1.RFC_ON 1920 #define PRCM_PDCTL1RFC_ON 0x00000001 1921 #define PRCM_PDCTL1RFC_ON_BITN 0 1922 #define PRCM_PDCTL1RFC_ON_M 0x00000001 1923 #define PRCM_PDCTL1RFC_ON_S 0 1924 1925 //***************************************************************************** 1926 // 1927 // Register: PRCM_O_PDCTL1VIMS 1928 // 1929 //***************************************************************************** 1930 // Field: [1:0] MODE 1931 // 1932 // This is an alias for PDCTL1.VIMS_MODE 1933 #define PRCM_PDCTL1VIMS_MODE_W 2 1934 #define PRCM_PDCTL1VIMS_MODE_M 0x00000003 1935 #define PRCM_PDCTL1VIMS_MODE_S 0 1936 1937 //***************************************************************************** 1938 // 1939 // Register: PRCM_O_PDSTAT1 1940 // 1941 //***************************************************************************** 1942 // Field: [4] BUS_ON 1943 // 1944 // 1945 // 0: BUS domain not accessible 1946 // 1: BUS domain is currently accessible 1947 #define PRCM_PDSTAT1_BUS_ON 0x00000010 1948 #define PRCM_PDSTAT1_BUS_ON_BITN 4 1949 #define PRCM_PDSTAT1_BUS_ON_M 0x00000010 1950 #define PRCM_PDSTAT1_BUS_ON_S 4 1951 1952 // Field: [3] VIMS_ON 1953 // 1954 // 1955 // 0: VIMS domain not accessible 1956 // 1: VIMS domain is currently accessible 1957 #define PRCM_PDSTAT1_VIMS_ON 0x00000008 1958 #define PRCM_PDSTAT1_VIMS_ON_BITN 3 1959 #define PRCM_PDSTAT1_VIMS_ON_M 0x00000008 1960 #define PRCM_PDSTAT1_VIMS_ON_S 3 1961 1962 // Field: [2] RFC_ON 1963 // 1964 // 1965 // 0: RFC domain not accessible 1966 // 1: RFC domain is currently accessible 1967 #define PRCM_PDSTAT1_RFC_ON 0x00000004 1968 #define PRCM_PDSTAT1_RFC_ON_BITN 2 1969 #define PRCM_PDSTAT1_RFC_ON_M 0x00000004 1970 #define PRCM_PDSTAT1_RFC_ON_S 2 1971 1972 // Field: [1] CPU_ON 1973 // 1974 // 1975 // 0: CPU and BUS domain not accessible 1976 // 1: CPU and BUS domains are both currently accessible 1977 #define PRCM_PDSTAT1_CPU_ON 0x00000002 1978 #define PRCM_PDSTAT1_CPU_ON_BITN 1 1979 #define PRCM_PDSTAT1_CPU_ON_M 0x00000002 1980 #define PRCM_PDSTAT1_CPU_ON_S 1 1981 1982 //***************************************************************************** 1983 // 1984 // Register: PRCM_O_PDSTAT1BUS 1985 // 1986 //***************************************************************************** 1987 // Field: [0] ON 1988 // 1989 // This is an alias for PDSTAT1.BUS_ON 1990 #define PRCM_PDSTAT1BUS_ON 0x00000001 1991 #define PRCM_PDSTAT1BUS_ON_BITN 0 1992 #define PRCM_PDSTAT1BUS_ON_M 0x00000001 1993 #define PRCM_PDSTAT1BUS_ON_S 0 1994 1995 //***************************************************************************** 1996 // 1997 // Register: PRCM_O_PDSTAT1RFC 1998 // 1999 //***************************************************************************** 2000 // Field: [0] ON 2001 // 2002 // This is an alias for PDSTAT1.RFC_ON 2003 #define PRCM_PDSTAT1RFC_ON 0x00000001 2004 #define PRCM_PDSTAT1RFC_ON_BITN 0 2005 #define PRCM_PDSTAT1RFC_ON_M 0x00000001 2006 #define PRCM_PDSTAT1RFC_ON_S 0 2007 2008 //***************************************************************************** 2009 // 2010 // Register: PRCM_O_PDSTAT1CPU 2011 // 2012 //***************************************************************************** 2013 // Field: [0] ON 2014 // 2015 // This is an alias for PDSTAT1.CPU_ON 2016 #define PRCM_PDSTAT1CPU_ON 0x00000001 2017 #define PRCM_PDSTAT1CPU_ON_BITN 0 2018 #define PRCM_PDSTAT1CPU_ON_M 0x00000001 2019 #define PRCM_PDSTAT1CPU_ON_S 0 2020 2021 //***************************************************************************** 2022 // 2023 // Register: PRCM_O_PDSTAT1VIMS 2024 // 2025 //***************************************************************************** 2026 // Field: [0] ON 2027 // 2028 // This is an alias for PDSTAT1.VIMS_ON 2029 #define PRCM_PDSTAT1VIMS_ON 0x00000001 2030 #define PRCM_PDSTAT1VIMS_ON_BITN 0 2031 #define PRCM_PDSTAT1VIMS_ON_M 0x00000001 2032 #define PRCM_PDSTAT1VIMS_ON_S 0 2033 2034 //***************************************************************************** 2035 // 2036 // Register: PRCM_O_RFCBITS 2037 // 2038 //***************************************************************************** 2039 // Field: [31:0] READ 2040 // 2041 // Control bits for RFC. The RF core CPE processor will automatically check 2042 // this register when it boots, and it can be used to immediately instruct CPE 2043 // to perform some tasks at its start-up. The supported functionality is 2044 // ROM-defined and may vary. See the technical reference manual for more 2045 // details. 2046 #define PRCM_RFCBITS_READ_W 32 2047 #define PRCM_RFCBITS_READ_M 0xFFFFFFFF 2048 #define PRCM_RFCBITS_READ_S 0 2049 2050 //***************************************************************************** 2051 // 2052 // Register: PRCM_O_RFCMODESEL 2053 // 2054 //***************************************************************************** 2055 // Field: [2:0] CURR 2056 // 2057 // Selects the set of commands that the RFC will accept. Only modes permitted 2058 // by RFCMODEHWOPT.AVAIL are writeable. See the technical reference manual for 2059 // details. 2060 // ENUMs: 2061 // MODE7 Select Mode 7 2062 // MODE6 Select Mode 6 2063 // MODE5 Select Mode 5 2064 // MODE4 Select Mode 4 2065 // MODE3 Select Mode 3 2066 // MODE2 Select Mode 2 2067 // MODE1 Select Mode 1 2068 // MODE0 Select Mode 0 2069 #define PRCM_RFCMODESEL_CURR_W 3 2070 #define PRCM_RFCMODESEL_CURR_M 0x00000007 2071 #define PRCM_RFCMODESEL_CURR_S 0 2072 #define PRCM_RFCMODESEL_CURR_MODE7 0x00000007 2073 #define PRCM_RFCMODESEL_CURR_MODE6 0x00000006 2074 #define PRCM_RFCMODESEL_CURR_MODE5 0x00000005 2075 #define PRCM_RFCMODESEL_CURR_MODE4 0x00000004 2076 #define PRCM_RFCMODESEL_CURR_MODE3 0x00000003 2077 #define PRCM_RFCMODESEL_CURR_MODE2 0x00000002 2078 #define PRCM_RFCMODESEL_CURR_MODE1 0x00000001 2079 #define PRCM_RFCMODESEL_CURR_MODE0 0x00000000 2080 2081 //***************************************************************************** 2082 // 2083 // Register: PRCM_O_RFCMODEHWOPT 2084 // 2085 //***************************************************************************** 2086 // Field: [7:0] AVAIL 2087 // 2088 // Permitted RFC modes. More than one mode can be permitted. 2089 // ENUMs: 2090 // MODE7 Mode 7 permitted 2091 // MODE6 Mode 6 permitted 2092 // MODE5 Mode 5 permitted 2093 // MODE4 Mode 4 permitted 2094 // MODE3 Mode 3 permitted 2095 // MODE2 Mode 2 permitted 2096 // MODE1 Mode 1 permitted 2097 // MODE0 Mode 0 permitted 2098 #define PRCM_RFCMODEHWOPT_AVAIL_W 8 2099 #define PRCM_RFCMODEHWOPT_AVAIL_M 0x000000FF 2100 #define PRCM_RFCMODEHWOPT_AVAIL_S 0 2101 #define PRCM_RFCMODEHWOPT_AVAIL_MODE7 0x00000080 2102 #define PRCM_RFCMODEHWOPT_AVAIL_MODE6 0x00000040 2103 #define PRCM_RFCMODEHWOPT_AVAIL_MODE5 0x00000020 2104 #define PRCM_RFCMODEHWOPT_AVAIL_MODE4 0x00000010 2105 #define PRCM_RFCMODEHWOPT_AVAIL_MODE3 0x00000008 2106 #define PRCM_RFCMODEHWOPT_AVAIL_MODE2 0x00000004 2107 #define PRCM_RFCMODEHWOPT_AVAIL_MODE1 0x00000002 2108 #define PRCM_RFCMODEHWOPT_AVAIL_MODE0 0x00000001 2109 2110 //***************************************************************************** 2111 // 2112 // Register: PRCM_O_PWRPROFSTAT 2113 // 2114 //***************************************************************************** 2115 // Field: [7:0] VALUE 2116 // 2117 // SW can use these bits to timestamp the application. These bits are also 2118 // available through the testtap and can thus be used by the emulator to 2119 // profile in real time. 2120 #define PRCM_PWRPROFSTAT_VALUE_W 8 2121 #define PRCM_PWRPROFSTAT_VALUE_M 0x000000FF 2122 #define PRCM_PWRPROFSTAT_VALUE_S 0 2123 2124 //***************************************************************************** 2125 // 2126 // Register: PRCM_O_RAMRETEN 2127 // 2128 //***************************************************************************** 2129 // Field: [3] RFCULL 2130 // 2131 // 0: Retention for RFC ULL SRAM disabled 2132 // 1: Retention for RFC ULL SRAM enabled 2133 // 2134 // Memories controlled: 2135 // CPEULLRAM 2136 #define PRCM_RAMRETEN_RFCULL 0x00000008 2137 #define PRCM_RAMRETEN_RFCULL_BITN 3 2138 #define PRCM_RAMRETEN_RFCULL_M 0x00000008 2139 #define PRCM_RAMRETEN_RFCULL_S 3 2140 2141 // Field: [2] RFC 2142 // 2143 // 0: Retention for RFC SRAM disabled 2144 // 1: Retention for RFC SRAM enabled 2145 // 2146 // Memories controlled: CPERAM MCERAM RFERAM DSBRAM 2147 #define PRCM_RAMRETEN_RFC 0x00000004 2148 #define PRCM_RAMRETEN_RFC_BITN 2 2149 #define PRCM_RAMRETEN_RFC_M 0x00000004 2150 #define PRCM_RAMRETEN_RFC_S 2 2151 2152 // Field: [1:0] VIMS 2153 // 2154 // 2155 // 0: Memory retention disabled 2156 // 1: Memory retention enabled 2157 // 2158 // Bit 0: VIMS_TRAM 2159 // Bit 1: VIMS_CRAM 2160 // 2161 // Legal modes depend on settings in VIMS:CTL.MODE 2162 // 2163 // 00: VIMS:CTL.MODE must be OFF before DEEPSLEEP is asserted - must be set to 2164 // CACHE or SPLIT mode after waking up again 2165 // 01: VIMS:CTL.MODE must be GPRAM before DEEPSLEEP is asserted. Must remain in 2166 // GPRAM mode after wake up, alternatively select OFF mode first and then CACHE 2167 // or SPILT mode. 2168 // 10: Illegal mode 2169 // 11: No restrictions 2170 #define PRCM_RAMRETEN_VIMS_W 2 2171 #define PRCM_RAMRETEN_VIMS_M 0x00000003 2172 #define PRCM_RAMRETEN_VIMS_S 0 2173 2174 //***************************************************************************** 2175 // 2176 // Register: PRCM_O_OSCIMSC 2177 // 2178 //***************************************************************************** 2179 // Field: [7] HFSRCPENDIM 2180 // 2181 // 0: Disable interrupt generation when HFSRCPEND is qualified 2182 // 1: Enable interrupt generation when HFSRCPEND is qualified 2183 #define PRCM_OSCIMSC_HFSRCPENDIM 0x00000080 2184 #define PRCM_OSCIMSC_HFSRCPENDIM_BITN 7 2185 #define PRCM_OSCIMSC_HFSRCPENDIM_M 0x00000080 2186 #define PRCM_OSCIMSC_HFSRCPENDIM_S 7 2187 2188 // Field: [6] LFSRCDONEIM 2189 // 2190 // 0: Disable interrupt generation when LFSRCDONE is qualified 2191 // 1: Enable interrupt generation when LFSRCDONE is qualified 2192 #define PRCM_OSCIMSC_LFSRCDONEIM 0x00000040 2193 #define PRCM_OSCIMSC_LFSRCDONEIM_BITN 6 2194 #define PRCM_OSCIMSC_LFSRCDONEIM_M 0x00000040 2195 #define PRCM_OSCIMSC_LFSRCDONEIM_S 6 2196 2197 // Field: [5] XOSCDLFIM 2198 // 2199 // 0: Disable interrupt generation when XOSCDLF is qualified 2200 // 1: Enable interrupt generation when XOSCDLF is qualified 2201 #define PRCM_OSCIMSC_XOSCDLFIM 0x00000020 2202 #define PRCM_OSCIMSC_XOSCDLFIM_BITN 5 2203 #define PRCM_OSCIMSC_XOSCDLFIM_M 0x00000020 2204 #define PRCM_OSCIMSC_XOSCDLFIM_S 5 2205 2206 // Field: [4] XOSCLFIM 2207 // 2208 // 0: Disable interrupt generation when XOSCLF is qualified 2209 // 1: Enable interrupt generation when XOSCLF is qualified 2210 #define PRCM_OSCIMSC_XOSCLFIM 0x00000010 2211 #define PRCM_OSCIMSC_XOSCLFIM_BITN 4 2212 #define PRCM_OSCIMSC_XOSCLFIM_M 0x00000010 2213 #define PRCM_OSCIMSC_XOSCLFIM_S 4 2214 2215 // Field: [3] RCOSCDLFIM 2216 // 2217 // 0: Disable interrupt generation when RCOSCDLF is qualified 2218 // 1: Enable interrupt generation when RCOSCDLF is qualified 2219 #define PRCM_OSCIMSC_RCOSCDLFIM 0x00000008 2220 #define PRCM_OSCIMSC_RCOSCDLFIM_BITN 3 2221 #define PRCM_OSCIMSC_RCOSCDLFIM_M 0x00000008 2222 #define PRCM_OSCIMSC_RCOSCDLFIM_S 3 2223 2224 // Field: [2] RCOSCLFIM 2225 // 2226 // 0: Disable interrupt generation when RCOSCLF is qualified 2227 // 1: Enable interrupt generation when RCOSCLF is qualified 2228 #define PRCM_OSCIMSC_RCOSCLFIM 0x00000004 2229 #define PRCM_OSCIMSC_RCOSCLFIM_BITN 2 2230 #define PRCM_OSCIMSC_RCOSCLFIM_M 0x00000004 2231 #define PRCM_OSCIMSC_RCOSCLFIM_S 2 2232 2233 // Field: [1] XOSCHFIM 2234 // 2235 // 0: Disable interrupt generation when XOSCHF is qualified 2236 // 1: Enable interrupt generation when XOSCHF is qualified 2237 #define PRCM_OSCIMSC_XOSCHFIM 0x00000002 2238 #define PRCM_OSCIMSC_XOSCHFIM_BITN 1 2239 #define PRCM_OSCIMSC_XOSCHFIM_M 0x00000002 2240 #define PRCM_OSCIMSC_XOSCHFIM_S 1 2241 2242 // Field: [0] RCOSCHFIM 2243 // 2244 // 0: Disable interrupt generation when RCOSCHF is qualified 2245 // 1: Enable interrupt generation when RCOSCHF is qualified 2246 #define PRCM_OSCIMSC_RCOSCHFIM 0x00000001 2247 #define PRCM_OSCIMSC_RCOSCHFIM_BITN 0 2248 #define PRCM_OSCIMSC_RCOSCHFIM_M 0x00000001 2249 #define PRCM_OSCIMSC_RCOSCHFIM_S 0 2250 2251 //***************************************************************************** 2252 // 2253 // Register: PRCM_O_OSCRIS 2254 // 2255 //***************************************************************************** 2256 // Field: [7] HFSRCPENDRIS 2257 // 2258 // SCLK_HF source switch pending interrupt. 2259 // 2260 // After a write to DDI_0_OSC:CTL0.SCLK_HF_SRC_SEL leads to a SCLK_HF source 2261 // change request, then the requested SCLK_HF source will be enabled and 2262 // qualified. When the new source is ready to be used as a clock source, then 2263 // the interrupt HSSRCPENDRIS will go high. When the Flash allows SCLK_HF 2264 // source switching to take place after flash memory read access is disabled. 2265 // At this time the actual SCLK_HF clock source switch will be performed, and 2266 // the interrupt status HSSRCPENDRIS will go low. 2267 // 2268 // 0: Indicates SCLK_HF source is not ready to be switched 2269 // 1: Indicates SCLK_HF source is ready to be switched 2270 // 2271 // Interrupt is qualified regardless of OSCIMSC.HFSRCPENDIM setting. The order 2272 // of qualifying raw interrupt and enable of interrupt mask is indifferent for 2273 // generating an OSC Interrupt. 2274 // 2275 // Set by HW. Cleared by writing to OSCICR.HFSRCPENDC 2276 #define PRCM_OSCRIS_HFSRCPENDRIS 0x00000080 2277 #define PRCM_OSCRIS_HFSRCPENDRIS_BITN 7 2278 #define PRCM_OSCRIS_HFSRCPENDRIS_M 0x00000080 2279 #define PRCM_OSCRIS_HFSRCPENDRIS_S 7 2280 2281 // Field: [6] LFSRCDONERIS 2282 // 2283 // SCLK_LF source switch done. 2284 // 2285 // The DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL register field is used to request that 2286 // the SCLK_LF source shall be changed. After an SCLK_LF clock source change is 2287 // requested, the new source may need to be enabled and qualified before 2288 // switching of clock source can be done. The interrupt LFRSRCDONERIS goes high 2289 // to indicate that the SCLK_LF clock source switching has been performed. 2290 // LFRSRCDONERIS will go low again when the next clock source change is 2291 // requested by writing to DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL . 2292 // 2293 // 0: Indicates SCLK_LF source switch has not completed 2294 // 1: Indicates SCLK_LF source switch has completed 2295 // 2296 // Interrupt is qualified regardless of OSCIMSC.LFSRCDONEIM setting. The order 2297 // of qualifying raw interrupt and enable of interrupt mask is indifferent for 2298 // generating an OSC Interrupt. 2299 // 2300 // Set by HW. Cleared by writing to OSCICR.LFSRCDONEC 2301 #define PRCM_OSCRIS_LFSRCDONERIS 0x00000040 2302 #define PRCM_OSCRIS_LFSRCDONERIS_BITN 6 2303 #define PRCM_OSCRIS_LFSRCDONERIS_M 0x00000040 2304 #define PRCM_OSCRIS_LFSRCDONERIS_S 6 2305 2306 // Field: [5] XOSCDLFRIS 2307 // 2308 // The XOSCDLFRIS interrupt indicates when the XOSC_HF oscillator is ready to 2309 // be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. 2310 // When XOSCDLFRIS is high, XOSC_HF will be used as source for SCLK_LF when 2311 // selected. When none of the system clocks have XOSC_HF selected as clock 2312 // source, the XOSC_HF source is automatically disabled and the XOSCDLFRIS 2313 // interrupt status will go low. 2314 // 2315 // 0: XOSCDLF has not been qualified 2316 // 1: XOSCDLF has been qualified 2317 // 2318 // Interrupt is qualified regardless of OSCIMSC.XOSCDLFIM setting. The order of 2319 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2320 // generating an OSC Interrupt. 2321 // 2322 // Set by HW. Cleared by writing to OSCICR.XOSCDLFC 2323 #define PRCM_OSCRIS_XOSCDLFRIS 0x00000020 2324 #define PRCM_OSCRIS_XOSCDLFRIS_BITN 5 2325 #define PRCM_OSCRIS_XOSCDLFRIS_M 0x00000020 2326 #define PRCM_OSCRIS_XOSCDLFRIS_S 5 2327 2328 // Field: [4] XOSCLFRIS 2329 // 2330 // The XOSCLFRIS interrupt indicates when the output of the XOSC_LF oscillator 2331 // has been qualified with respect to frequency. The XOSCLFRIS interrupt status 2332 // goes high when the XOSC_LF oscillator is ready to be used as a clock source. 2333 // After the clock qualification is successful, XOSCLFRIS interrupt status 2334 // remains high, and further qualification is turned off until the XOSC_LF 2335 // oscillator is disabled. XOSCLFRIS interrupt status will go low only at 2336 // initial power-on, or after the XOSC_LF oscillator has been disabled when 2337 // being deselected as a clock source. 2338 // 2339 // 0: XOSCLF has not been qualified 2340 // 1: XOSCLF has been qualified 2341 // 2342 // Interrupt is qualified regardless of OSCIMSC.XOSCLFIM setting. The order of 2343 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2344 // generating an OSC Interrupt. 2345 // 2346 // Set by HW. Cleared by writing to OSCICR.XOSCLFC 2347 #define PRCM_OSCRIS_XOSCLFRIS 0x00000010 2348 #define PRCM_OSCRIS_XOSCLFRIS_BITN 4 2349 #define PRCM_OSCRIS_XOSCLFRIS_M 0x00000010 2350 #define PRCM_OSCRIS_XOSCLFRIS_S 4 2351 2352 // Field: [3] RCOSCDLFRIS 2353 // 2354 // The RCOSCDLFRIS interrupt indicates when the RCOSC_HF oscillator is ready to 2355 // be used as a derived low-frequency clock source for SCLK_LF or ACLK_REF. 2356 // When RCOSCDLFRIS is high, RCOSC_HF will be used as source for SCLK_LF when 2357 // selected. When none of the system clocks have RCOSC_HF selected as clock 2358 // source, the RCOSC_HF source is automatically disabled and the RCOSCDLFRIS 2359 // interrupt status will go low. 2360 // If the SCLK_LF or ACLK_REF source is changed from RCOSC_HF derived to 2361 // XOSC_HF derived low-frequency clock and the new source has not been 2362 // qualified, then the clock will remain running on the original source. The 2363 // RCOSCDLFRIS interrupt will then remain high. 2364 // 2365 // 0: RCOSCDLF has not been qualified 2366 // 1: RCOSCDLF has been qualified 2367 // 2368 // Interrupt is qualified regardless of OSCIMSC.RCOSCDLFIM setting. The order 2369 // of qualifying raw interrupt and enable of interrupt mask is indifferent for 2370 // generating an OSC Interrupt. 2371 // 2372 // Set by HW. Cleared by writing to OSCICR.RCOSCDLFC 2373 #define PRCM_OSCRIS_RCOSCDLFRIS 0x00000008 2374 #define PRCM_OSCRIS_RCOSCDLFRIS_BITN 3 2375 #define PRCM_OSCRIS_RCOSCDLFRIS_M 0x00000008 2376 #define PRCM_OSCRIS_RCOSCDLFRIS_S 3 2377 2378 // Field: [2] RCOSCLFRIS 2379 // 2380 // The RCOSCLFRIS interrupt indicates when the output of the RCOSC_LF 2381 // oscillator has been qualified with respect to frequency. The RCOSCLFRIS 2382 // interrupt status goes high when the RCOSC_LF oscillator is ready to be used 2383 // as a clock source. 2384 // After the clock qualification is successful, RCOSCLFRIS interrupt status 2385 // remains high, and further qualification is turned off until the RCOSC_LF 2386 // oscillator is disabled. RCOSCLFRIS interrupt status will go low only at 2387 // initial power-on, or after the RCOSC_LF oscillator has been disabled when 2388 // being deselected as a clock source. 2389 // 2390 // 0: RCOSCLF has not been qualified 2391 // 1: RCOSCLF has been qualified 2392 // 2393 // Interrupt is qualified regardless of OSCIMSC.RCOSCLFIM setting. The order of 2394 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2395 // generating an OSC Interrupt. 2396 // 2397 // Set by HW. Cleared by writing to OSCICR.RCOSCLFC 2398 #define PRCM_OSCRIS_RCOSCLFRIS 0x00000004 2399 #define PRCM_OSCRIS_RCOSCLFRIS_BITN 2 2400 #define PRCM_OSCRIS_RCOSCLFRIS_M 0x00000004 2401 #define PRCM_OSCRIS_RCOSCLFRIS_S 2 2402 2403 // Field: [1] XOSCHFRIS 2404 // 2405 // The XOSCHFRIS interrupt indicates when the XOSC_HF oscillator has been 2406 // qualified for use as a clock source. XOSCHFRIS is also used in TCXO mode 2407 // (when DDI_0_OSC:XOSCHFCTL.TCXO_MODE is 1). 2408 // When the XOSCHFRIS interrupt is high, the oscillator is qualified and will 2409 // be used as a clock source when selected. The XOSCHFRIS interrupt goes low 2410 // when the oscillator is disabled after being deselected as a clock source. 2411 // 2412 // 2413 // 0: XOSC_HF has not been qualified 2414 // 1: XOSC_HF has been qualified 2415 // 2416 // Interrupt is qualified regardless of OSCIMSC.XOSCHFIM setting. The order of 2417 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2418 // generating an OSC Interrupt. 2419 // 2420 // Set by HW. Cleared by writing to OSCICR.XOSCHFC 2421 #define PRCM_OSCRIS_XOSCHFRIS 0x00000002 2422 #define PRCM_OSCRIS_XOSCHFRIS_BITN 1 2423 #define PRCM_OSCRIS_XOSCHFRIS_M 0x00000002 2424 #define PRCM_OSCRIS_XOSCHFRIS_S 1 2425 2426 // Field: [0] RCOSCHFRIS 2427 // 2428 // The RCOSCHFRIS interrupt indicates when the RCOSC_HF oscillator has been 2429 // qualified for use as a clock source When the RCOSCHFRIS interrupt is high, 2430 // the oscillator is qualified and will be used as a clock source when 2431 // selected. The RCOSCHFRIS interrupt goes low when the oscillator is disabled 2432 // after being deselected as a clock source. 2433 // 2434 // 0: RCOSC_HF has not been qualified 2435 // 1: RCOSC_HF has been qualified 2436 // 2437 // Interrupt is qualified regardless of OSCIMSC.RCOSCHFIM setting. The order of 2438 // qualifying raw interrupt and enable of interrupt mask is indifferent for 2439 // generating an OSC Interrupt. 2440 // 2441 // Set by HW. Cleared by writing to OSCICR.RCOSCHFC 2442 #define PRCM_OSCRIS_RCOSCHFRIS 0x00000001 2443 #define PRCM_OSCRIS_RCOSCHFRIS_BITN 0 2444 #define PRCM_OSCRIS_RCOSCHFRIS_M 0x00000001 2445 #define PRCM_OSCRIS_RCOSCHFRIS_S 0 2446 2447 //***************************************************************************** 2448 // 2449 // Register: PRCM_O_OSCICR 2450 // 2451 //***************************************************************************** 2452 // Field: [7] HFSRCPENDC 2453 // 2454 // Writing 1 to this field clears the HFSRCPEND raw interrupt status. Writing 0 2455 // has no effect. 2456 #define PRCM_OSCICR_HFSRCPENDC 0x00000080 2457 #define PRCM_OSCICR_HFSRCPENDC_BITN 7 2458 #define PRCM_OSCICR_HFSRCPENDC_M 0x00000080 2459 #define PRCM_OSCICR_HFSRCPENDC_S 7 2460 2461 // Field: [6] LFSRCDONEC 2462 // 2463 // Writing 1 to this field clears the LFSRCDONE raw interrupt status. Writing 0 2464 // has no effect. 2465 #define PRCM_OSCICR_LFSRCDONEC 0x00000040 2466 #define PRCM_OSCICR_LFSRCDONEC_BITN 6 2467 #define PRCM_OSCICR_LFSRCDONEC_M 0x00000040 2468 #define PRCM_OSCICR_LFSRCDONEC_S 6 2469 2470 // Field: [5] XOSCDLFC 2471 // 2472 // Writing 1 to this field clears the XOSCDLF raw interrupt status. Writing 0 2473 // has no effect. 2474 #define PRCM_OSCICR_XOSCDLFC 0x00000020 2475 #define PRCM_OSCICR_XOSCDLFC_BITN 5 2476 #define PRCM_OSCICR_XOSCDLFC_M 0x00000020 2477 #define PRCM_OSCICR_XOSCDLFC_S 5 2478 2479 // Field: [4] XOSCLFC 2480 // 2481 // Writing 1 to this field clears the XOSCLF raw interrupt status. Writing 0 2482 // has no effect. 2483 #define PRCM_OSCICR_XOSCLFC 0x00000010 2484 #define PRCM_OSCICR_XOSCLFC_BITN 4 2485 #define PRCM_OSCICR_XOSCLFC_M 0x00000010 2486 #define PRCM_OSCICR_XOSCLFC_S 4 2487 2488 // Field: [3] RCOSCDLFC 2489 // 2490 // Writing 1 to this field clears the RCOSCDLF raw interrupt status. Writing 0 2491 // has no effect. 2492 #define PRCM_OSCICR_RCOSCDLFC 0x00000008 2493 #define PRCM_OSCICR_RCOSCDLFC_BITN 3 2494 #define PRCM_OSCICR_RCOSCDLFC_M 0x00000008 2495 #define PRCM_OSCICR_RCOSCDLFC_S 3 2496 2497 // Field: [2] RCOSCLFC 2498 // 2499 // Writing 1 to this field clears the RCOSCLF raw interrupt status. Writing 0 2500 // has no effect. 2501 #define PRCM_OSCICR_RCOSCLFC 0x00000004 2502 #define PRCM_OSCICR_RCOSCLFC_BITN 2 2503 #define PRCM_OSCICR_RCOSCLFC_M 0x00000004 2504 #define PRCM_OSCICR_RCOSCLFC_S 2 2505 2506 // Field: [1] XOSCHFC 2507 // 2508 // Writing 1 to this field clears the XOSCHF raw interrupt status. Writing 0 2509 // has no effect. 2510 #define PRCM_OSCICR_XOSCHFC 0x00000002 2511 #define PRCM_OSCICR_XOSCHFC_BITN 1 2512 #define PRCM_OSCICR_XOSCHFC_M 0x00000002 2513 #define PRCM_OSCICR_XOSCHFC_S 1 2514 2515 // Field: [0] RCOSCHFC 2516 // 2517 // Writing 1 to this field clears the RCOSCHF raw interrupt status. Writing 0 2518 // has no effect. 2519 #define PRCM_OSCICR_RCOSCHFC 0x00000001 2520 #define PRCM_OSCICR_RCOSCHFC_BITN 0 2521 #define PRCM_OSCICR_RCOSCHFC_M 0x00000001 2522 #define PRCM_OSCICR_RCOSCHFC_S 0 2523 2524 2525 #endif // __PRCM__ 2526
