1 /****************************************************************************** 2 * Filename: hw_pka_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_PKA_H__ 38 #define __HW_PKA_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // PKA component 44 // 45 //***************************************************************************** 46 // PKA Vector A Address 47 #define PKA_O_APTR 0x00000000 48 49 // PKA Vector B Address 50 #define PKA_O_BPTR 0x00000004 51 52 // PKA Vector C Address 53 #define PKA_O_CPTR 0x00000008 54 55 // PKA Vector D Address 56 #define PKA_O_DPTR 0x0000000C 57 58 // PKA Vector A Length 59 #define PKA_O_ALENGTH 0x00000010 60 61 // PKA Vector B Length 62 #define PKA_O_BLENGTH 0x00000014 63 64 // PKA Bit Shift Value 65 #define PKA_O_SHIFT 0x00000018 66 67 // PKA Function 68 #define PKA_O_FUNCTION 0x0000001C 69 70 // PKA compare result 71 #define PKA_O_COMPARE 0x00000020 72 73 // PKA most-significant-word of result vector 74 #define PKA_O_MSW 0x00000024 75 76 // PKA most-significant-word of divide remainder 77 #define PKA_O_DIVMSW 0x00000028 78 79 // PKA sequencer control and status register 80 #define PKA_O_SEQCTRL 0x000000C8 81 82 // PKA hardware options register 83 #define PKA_O_OPTIONS 0x000000F4 84 85 // PKA firmware revision and capabilities register 86 #define PKA_O_FWREV 0x000000F8 87 88 // PKA hardware revision register 89 #define PKA_O_HWREV 0x000000FC 90 91 //***************************************************************************** 92 // 93 // Register: PKA_O_APTR 94 // 95 //***************************************************************************** 96 // Field: [10:0] APTR 97 // 98 // This register specifies the location of vector A within the PKA RAM. Vectors 99 // are identified through the location of their least-significant 32-bit word. 100 // Note that bit [0] must be zero to ensure that the vector starts at an 8-byte 101 // boundary. 102 #define PKA_APTR_APTR_W 11 103 #define PKA_APTR_APTR_M 0x000007FF 104 #define PKA_APTR_APTR_S 0 105 106 //***************************************************************************** 107 // 108 // Register: PKA_O_BPTR 109 // 110 //***************************************************************************** 111 // Field: [10:0] BPTR 112 // 113 // This register specifies the location of vector B within the PKA RAM. Vectors 114 // are identified through the location of their least-significant 32-bit word. 115 // Note that bit [0] must be zero to ensure that the vector starts at an 8-byte 116 // boundary. 117 #define PKA_BPTR_BPTR_W 11 118 #define PKA_BPTR_BPTR_M 0x000007FF 119 #define PKA_BPTR_BPTR_S 0 120 121 //***************************************************************************** 122 // 123 // Register: PKA_O_CPTR 124 // 125 //***************************************************************************** 126 // Field: [10:0] CPTR 127 // 128 // This register specifies the location of vector C within the PKA RAM. Vectors 129 // are identified through the location of their least-significant 32-bit word. 130 // Note that bit [0] must be zero to ensure that the vector starts at an 8-byte 131 // boundary. 132 #define PKA_CPTR_CPTR_W 11 133 #define PKA_CPTR_CPTR_M 0x000007FF 134 #define PKA_CPTR_CPTR_S 0 135 136 //***************************************************************************** 137 // 138 // Register: PKA_O_DPTR 139 // 140 //***************************************************************************** 141 // Field: [10:0] DPTR 142 // 143 // This register specifies the location of vector D within the PKA RAM. Vectors 144 // are identified through the location of their least-significant 32-bit word. 145 // Note that bit [0] must be zero to ensure that the vector starts at an 8-byte 146 // boundary. 147 #define PKA_DPTR_DPTR_W 11 148 #define PKA_DPTR_DPTR_M 0x000007FF 149 #define PKA_DPTR_DPTR_S 0 150 151 //***************************************************************************** 152 // 153 // Register: PKA_O_ALENGTH 154 // 155 //***************************************************************************** 156 // Field: [8:0] ALENGTH 157 // 158 // This register specifies the length (in 32-bit words) of Vector A. 159 #define PKA_ALENGTH_ALENGTH_W 9 160 #define PKA_ALENGTH_ALENGTH_M 0x000001FF 161 #define PKA_ALENGTH_ALENGTH_S 0 162 163 //***************************************************************************** 164 // 165 // Register: PKA_O_BLENGTH 166 // 167 //***************************************************************************** 168 // Field: [8:0] BLENGTH 169 // 170 // This register specifies the length (in 32-bit words) of Vector B. 171 #define PKA_BLENGTH_BLENGTH_W 9 172 #define PKA_BLENGTH_BLENGTH_M 0x000001FF 173 #define PKA_BLENGTH_BLENGTH_S 0 174 175 //***************************************************************************** 176 // 177 // Register: PKA_O_SHIFT 178 // 179 //***************************************************************************** 180 // Field: [4:0] NUM_BITS_TO_SHIFT 181 // 182 // This register specifies the number of bits to shift the input vector (in the 183 // range 0-31) during a Rshift or Lshift operation. 184 #define PKA_SHIFT_NUM_BITS_TO_SHIFT_W 5 185 #define PKA_SHIFT_NUM_BITS_TO_SHIFT_M 0x0000001F 186 #define PKA_SHIFT_NUM_BITS_TO_SHIFT_S 0 187 188 //***************************************************************************** 189 // 190 // Register: PKA_O_FUNCTION 191 // 192 //***************************************************************************** 193 // Field: [24] STALL_RESULT 194 // 195 // When written with a 1b, updating of the COMPARE bit, MSW and DIVMSW 196 // registers, as well as resetting the run bit is stalled beyond the point that 197 // a running operation is actually finished. Use this to allow software enough 198 // time to read results from a previous operation when the newly started 199 // operation is known to take only a short amount of time. If a result is 200 // waiting, the result registers is updated and the run bit is reset in the 201 // clock cycle following writing the stall result bit back to 0b. The Stall 202 // result function may only be used for basic PKCP operations. 203 #define PKA_FUNCTION_STALL_RESULT 0x01000000 204 #define PKA_FUNCTION_STALL_RESULT_BITN 24 205 #define PKA_FUNCTION_STALL_RESULT_M 0x01000000 206 #define PKA_FUNCTION_STALL_RESULT_S 24 207 208 // Field: [15] RUN 209 // 210 // The host sets this bit to instruct the PKA module to begin processing the 211 // basic PKCP or complex sequencer operation. This bit is reset low 212 // automatically when the operation is complete. 213 // After a reset, the run bit is always set to 1b. Depending on the option, 214 // program ROM or program RAM, the following applies: 215 // Program ROM - The first sequencer instruction sets the bit to 0b. This is 216 // done immediately after the hardware reset is released. 217 // Program RAM - The sequencer must set the bit to 0b. As a valid firmware may 218 // not have been loaded, the sequencer is held in software reset after the 219 // hardware reset is released (the SEQCTRL.RESET bit is set to 1b). After the 220 // FW image is loaded and the Reset bit is cleared, the sequencer starts to 221 // execute the FW. The first instruction clears the run bit. 222 // In both cases a few clock cycles are needed before the first instruction is 223 // executed and the run bit state has been propagated. 224 #define PKA_FUNCTION_RUN 0x00008000 225 #define PKA_FUNCTION_RUN_BITN 15 226 #define PKA_FUNCTION_RUN_M 0x00008000 227 #define PKA_FUNCTION_RUN_S 15 228 229 // Field: [14:12] SEQUENCER_OPERATIONS 230 // 231 // These bits select the complex sequencer operation to perform: 232 // 0x0: None 233 // 0x1: ExpMod-CRT 234 // 0x2: ECmontMUL 235 // 0x3: ECC-ADD (if available in firmware, otherwise reserved) 236 // 0x4: ExpMod-ACT2 237 // 0x5: ECC-MUL (if available in firmware, otherwise reserved) 238 // 0x6: ExpMod-variable 239 // 0x7: ModInv (if available in firmware, otherwise reserved) 240 // The encoding of these operations is determined by sequencer firmware. 241 #define PKA_FUNCTION_SEQUENCER_OPERATIONS_W 3 242 #define PKA_FUNCTION_SEQUENCER_OPERATIONS_M 0x00007000 243 #define PKA_FUNCTION_SEQUENCER_OPERATIONS_S 12 244 245 // Field: [11] COPY 246 // 247 // Perform copy operation 248 #define PKA_FUNCTION_COPY 0x00000800 249 #define PKA_FUNCTION_COPY_BITN 11 250 #define PKA_FUNCTION_COPY_M 0x00000800 251 #define PKA_FUNCTION_COPY_S 11 252 253 // Field: [10] COMPARE 254 // 255 // Perform compare operation 256 #define PKA_FUNCTION_COMPARE 0x00000400 257 #define PKA_FUNCTION_COMPARE_BITN 10 258 #define PKA_FUNCTION_COMPARE_M 0x00000400 259 #define PKA_FUNCTION_COMPARE_S 10 260 261 // Field: [9] MODULO 262 // 263 // Perform modulo operation 264 #define PKA_FUNCTION_MODULO 0x00000200 265 #define PKA_FUNCTION_MODULO_BITN 9 266 #define PKA_FUNCTION_MODULO_M 0x00000200 267 #define PKA_FUNCTION_MODULO_S 9 268 269 // Field: [8] DIVIDE 270 // 271 // Perform divide operation 272 #define PKA_FUNCTION_DIVIDE 0x00000100 273 #define PKA_FUNCTION_DIVIDE_BITN 8 274 #define PKA_FUNCTION_DIVIDE_M 0x00000100 275 #define PKA_FUNCTION_DIVIDE_S 8 276 277 // Field: [7] LSHIFT 278 // 279 // Perform left shift operation 280 #define PKA_FUNCTION_LSHIFT 0x00000080 281 #define PKA_FUNCTION_LSHIFT_BITN 7 282 #define PKA_FUNCTION_LSHIFT_M 0x00000080 283 #define PKA_FUNCTION_LSHIFT_S 7 284 285 // Field: [6] RSHIFT 286 // 287 // Perform right shift operation 288 #define PKA_FUNCTION_RSHIFT 0x00000040 289 #define PKA_FUNCTION_RSHIFT_BITN 6 290 #define PKA_FUNCTION_RSHIFT_M 0x00000040 291 #define PKA_FUNCTION_RSHIFT_S 6 292 293 // Field: [5] SUBTRACT 294 // 295 // Perform subtract operation 296 #define PKA_FUNCTION_SUBTRACT 0x00000020 297 #define PKA_FUNCTION_SUBTRACT_BITN 5 298 #define PKA_FUNCTION_SUBTRACT_M 0x00000020 299 #define PKA_FUNCTION_SUBTRACT_S 5 300 301 // Field: [4] ADD 302 // 303 // Perform add operation 304 #define PKA_FUNCTION_ADD 0x00000010 305 #define PKA_FUNCTION_ADD_BITN 4 306 #define PKA_FUNCTION_ADD_M 0x00000010 307 #define PKA_FUNCTION_ADD_S 4 308 309 // Field: [3] MS_ONE 310 // 311 // Loads the location of the Most Significant one bit within the result word 312 // indicated in the MSW register into bits [4:0] of the DIVMSW.MSW_ADDRESS 313 // register - can only be used with basic PKCP operations, except for Divide, 314 // Modulo and Compare. 315 #define PKA_FUNCTION_MS_ONE 0x00000008 316 #define PKA_FUNCTION_MS_ONE_BITN 3 317 #define PKA_FUNCTION_MS_ONE_M 0x00000008 318 #define PKA_FUNCTION_MS_ONE_S 3 319 320 // Field: [1] ADDSUB 321 // 322 // Perform combined add/subtract operation 323 #define PKA_FUNCTION_ADDSUB 0x00000002 324 #define PKA_FUNCTION_ADDSUB_BITN 1 325 #define PKA_FUNCTION_ADDSUB_M 0x00000002 326 #define PKA_FUNCTION_ADDSUB_S 1 327 328 // Field: [0] MULTIPLY 329 // 330 // Perform multiply operation 331 #define PKA_FUNCTION_MULTIPLY 0x00000001 332 #define PKA_FUNCTION_MULTIPLY_BITN 0 333 #define PKA_FUNCTION_MULTIPLY_M 0x00000001 334 #define PKA_FUNCTION_MULTIPLY_S 0 335 336 //***************************************************************************** 337 // 338 // Register: PKA_O_COMPARE 339 // 340 //***************************************************************************** 341 // Field: [2] A_GREATER_THAN_B 342 // 343 // Vector_A is greater than Vector_B 344 #define PKA_COMPARE_A_GREATER_THAN_B 0x00000004 345 #define PKA_COMPARE_A_GREATER_THAN_B_BITN 2 346 #define PKA_COMPARE_A_GREATER_THAN_B_M 0x00000004 347 #define PKA_COMPARE_A_GREATER_THAN_B_S 2 348 349 // Field: [1] A_LESS_THAN_B 350 // 351 // Vector_A is less than Vector_B 352 #define PKA_COMPARE_A_LESS_THAN_B 0x00000002 353 #define PKA_COMPARE_A_LESS_THAN_B_BITN 1 354 #define PKA_COMPARE_A_LESS_THAN_B_M 0x00000002 355 #define PKA_COMPARE_A_LESS_THAN_B_S 1 356 357 // Field: [0] A_EQUALS_B 358 // 359 // Vector_A is equal to Vector_B 360 #define PKA_COMPARE_A_EQUALS_B 0x00000001 361 #define PKA_COMPARE_A_EQUALS_B_BITN 0 362 #define PKA_COMPARE_A_EQUALS_B_M 0x00000001 363 #define PKA_COMPARE_A_EQUALS_B_S 0 364 365 //***************************************************************************** 366 // 367 // Register: PKA_O_MSW 368 // 369 //***************************************************************************** 370 // Field: [15] RESULT_IS_ZERO 371 // 372 // The result vector is all zeroes, ignore the address returned in bits [10:0] 373 #define PKA_MSW_RESULT_IS_ZERO 0x00008000 374 #define PKA_MSW_RESULT_IS_ZERO_BITN 15 375 #define PKA_MSW_RESULT_IS_ZERO_M 0x00008000 376 #define PKA_MSW_RESULT_IS_ZERO_S 15 377 378 // Field: [10:0] MSW_ADDRESS 379 // 380 // Address of the most-significant nonzero 32-bit word of the result vector in 381 // PKA RAM 382 #define PKA_MSW_MSW_ADDRESS_W 11 383 #define PKA_MSW_MSW_ADDRESS_M 0x000007FF 384 #define PKA_MSW_MSW_ADDRESS_S 0 385 386 //***************************************************************************** 387 // 388 // Register: PKA_O_DIVMSW 389 // 390 //***************************************************************************** 391 // Field: [15] RESULT_IS_ZERO 392 // 393 // The result vector is all zeroes, ignore the address returned in bits [10:0] 394 #define PKA_DIVMSW_RESULT_IS_ZERO 0x00008000 395 #define PKA_DIVMSW_RESULT_IS_ZERO_BITN 15 396 #define PKA_DIVMSW_RESULT_IS_ZERO_M 0x00008000 397 #define PKA_DIVMSW_RESULT_IS_ZERO_S 15 398 399 // Field: [10:0] MSW_ADDRESS 400 // 401 // Address of the most significant nonzero 32-bit word of the remainder result 402 // vector in PKA RAM 403 #define PKA_DIVMSW_MSW_ADDRESS_W 11 404 #define PKA_DIVMSW_MSW_ADDRESS_M 0x000007FF 405 #define PKA_DIVMSW_MSW_ADDRESS_S 0 406 407 //***************************************************************************** 408 // 409 // Register: PKA_O_SEQCTRL 410 // 411 //***************************************************************************** 412 // Field: [31] RESET 413 // 414 // Option program ROM: Reset value = 0. Read/Write, reset value 0b (ZERO). 415 // Writing 1b resets the sequencer, write to 0b to restart operations again. As 416 // the reset value is 0b, the sequencer will automatically start operations 417 // executing from program ROM. This bit should always be written with zero and 418 // ignored when reading this register. 419 // 420 // Option Program RAM: Reset value =1. Read/Write, reset value 1b (ONE). When 421 // 1b, the sequencer is held in a reset state and the PKA_PROGRAM area is 422 // accessible for loading the sequencer program (while the PKA_DATA_RAM is 423 // inaccessible), write to 0b to (re)start sequencer operations and disable 424 // PKA_PROGRAM area accessibility (also enables the PKA_DATA_RAM accesses). 425 // Resetting the sequencer (in order to load other firmware) should only be 426 // done when the PKA Engine is not performing any operations (i.e. the 427 // FUNCTION.RUN bit should be zero). 428 #define PKA_SEQCTRL_RESET 0x80000000 429 #define PKA_SEQCTRL_RESET_BITN 31 430 #define PKA_SEQCTRL_RESET_M 0x80000000 431 #define PKA_SEQCTRL_RESET_S 31 432 433 // Field: [15:8] SEQUENCER_STAT 434 // 435 // These read-only bits can be used by the sequencer to communicate status to 436 // the outside world. Bit [8] is also used as sequencer interrupt, with the 437 // complement of this bit ORed into the FUNCTION.RUN bit. This field should 438 // always be written with zeroes and ignored when reading this register. 439 #define PKA_SEQCTRL_SEQUENCER_STAT_W 8 440 #define PKA_SEQCTRL_SEQUENCER_STAT_M 0x0000FF00 441 #define PKA_SEQCTRL_SEQUENCER_STAT_S 8 442 443 // Field: [7:0] SW_CONTROL_STAT 444 // 445 // These bits can be used by software to trigger sequencer operations. External 446 // logic can set these bits by writing 1b, cannot reset them by writing 0b. The 447 // sequencer can reset these bits by writing 0b, cannot set them by writing 1b. 448 // Setting the FUNCTION.RUN bit together with a nonzero sequencer operations 449 // field automatically sets bit [0] here. This field should always be written 450 // with zeroes and ignored when reading this register. 451 #define PKA_SEQCTRL_SW_CONTROL_STAT_W 8 452 #define PKA_SEQCTRL_SW_CONTROL_STAT_M 0x000000FF 453 #define PKA_SEQCTRL_SW_CONTROL_STAT_S 0 454 455 //***************************************************************************** 456 // 457 // Register: PKA_O_OPTIONS 458 // 459 //***************************************************************************** 460 // Field: [11] INT_MASKING 461 // 462 // Interrupt Masking 463 // 0x0: indicates that the main interrupt output (bit [1] of the interrupts 464 // output bus) is the direct complement of the run bit in the PKA_CONTROL 465 // register, 0x1 : indicates 466 // that interrupt masking logic is present for this output. 467 // Note: Reset value is undefined 468 #define PKA_OPTIONS_INT_MASKING 0x00000800 469 #define PKA_OPTIONS_INT_MASKING_BITN 11 470 #define PKA_OPTIONS_INT_MASKING_M 0x00000800 471 #define PKA_OPTIONS_INT_MASKING_S 11 472 473 // Field: [10:8] PROTECTION_OPTION 474 // 475 // Protection Option 476 // 0x0: indicates no additional protection against side channel attacks, 477 // 478 // 0x1: indicates the SCAP option 479 // 0x2: Reserved 480 // 0x3: indicates the PROT option; 481 // Note: Reset value is undefined 482 #define PKA_OPTIONS_PROTECTION_OPTION_W 3 483 #define PKA_OPTIONS_PROTECTION_OPTION_M 0x00000700 484 #define PKA_OPTIONS_PROTECTION_OPTION_S 8 485 486 // Field: [7] PROGRAM_RAM 487 // 488 // Program RAM 489 // 0x1: indicates sequencer program storage in RAM, 0x0: 490 // indicates sequencer program storage in ROM. 491 // Note: Reset value is undefined 492 #define PKA_OPTIONS_PROGRAM_RAM 0x00000080 493 #define PKA_OPTIONS_PROGRAM_RAM_BITN 7 494 #define PKA_OPTIONS_PROGRAM_RAM_M 0x00000080 495 #define PKA_OPTIONS_PROGRAM_RAM_S 7 496 497 // Field: [6:5] SEQUENCER_CONFIGURATION 498 // 499 // Sequencer Configuration 500 // 0x0: Reserved 501 // 0x1 : Indicates a standard sequencer 502 // 0x2: Reserved 503 // 0x3: Reserved 504 #define PKA_OPTIONS_SEQUENCER_CONFIGURATION_W 2 505 #define PKA_OPTIONS_SEQUENCER_CONFIGURATION_M 0x00000060 506 #define PKA_OPTIONS_SEQUENCER_CONFIGURATION_S 5 507 508 // Field: [1:0] PKCP_CONFIGURATION 509 // 510 // PKCP Configuration 0x0 511 // : Reserved 512 // 0x1 : Indicates a PKCP with a 16x16 multiplier, 0x2: 513 // indicates a PKCP with a 32x32 multiplier, 0x3 : Reserved 514 // Note: Reset value is undefined. 515 #define PKA_OPTIONS_PKCP_CONFIGURATION_W 2 516 #define PKA_OPTIONS_PKCP_CONFIGURATION_M 0x00000003 517 #define PKA_OPTIONS_PKCP_CONFIGURATION_S 0 518 519 //***************************************************************************** 520 // 521 // Register: PKA_O_FWREV 522 // 523 //***************************************************************************** 524 // Field: [31:28] FW_CAPABILITIES 525 // 526 // Firmware Capabilities 527 // 528 // 4-bit binary encoding for the functionality implemented 529 // in the firmware. 530 // 0x0: indicates basic ModExp with/without CRT. 0x1: 531 // adds Modular Inversion, 0x2: value 532 // 2 adds Modular Inversion and ECC operations. 533 // 0x3-0xF : Reserved. 534 #define PKA_FWREV_FW_CAPABILITIES_W 4 535 #define PKA_FWREV_FW_CAPABILITIES_M 0xF0000000 536 #define PKA_FWREV_FW_CAPABILITIES_S 28 537 538 // Field: [27:24] MAJOR_FW_REVISION 539 // 540 // 4-bit binary encoding of the major firmware revision number 541 #define PKA_FWREV_MAJOR_FW_REVISION_W 4 542 #define PKA_FWREV_MAJOR_FW_REVISION_M 0x0F000000 543 #define PKA_FWREV_MAJOR_FW_REVISION_S 24 544 545 // Field: [23:20] MINOR_FW_REVISION 546 // 547 // 4-bit binary encoding of the minor firmware revision number 548 #define PKA_FWREV_MINOR_FW_REVISION_W 4 549 #define PKA_FWREV_MINOR_FW_REVISION_M 0x00F00000 550 #define PKA_FWREV_MINOR_FW_REVISION_S 20 551 552 // Field: [19:16] FW_PATCH_LEVEL 553 // 554 // 4-bit binary encoding of the firmware patch level, initial release will 555 // carry value zero 556 // Patches are used to remove bugs without changing the functionality or 557 // interface of a module. 558 #define PKA_FWREV_FW_PATCH_LEVEL_W 4 559 #define PKA_FWREV_FW_PATCH_LEVEL_M 0x000F0000 560 #define PKA_FWREV_FW_PATCH_LEVEL_S 16 561 562 //***************************************************************************** 563 // 564 // Register: PKA_O_HWREV 565 // 566 //***************************************************************************** 567 // Field: [27:24] MAJOR_HW_REVISION 568 // 569 // 4-bit binary encoding of the major hardware revision number 570 #define PKA_HWREV_MAJOR_HW_REVISION_W 4 571 #define PKA_HWREV_MAJOR_HW_REVISION_M 0x0F000000 572 #define PKA_HWREV_MAJOR_HW_REVISION_S 24 573 574 // Field: [23:20] MINOR_HW_REVISION 575 // 576 // 4-bit binary encoding of the minor hardware revision number 577 #define PKA_HWREV_MINOR_HW_REVISION_W 4 578 #define PKA_HWREV_MINOR_HW_REVISION_M 0x00F00000 579 #define PKA_HWREV_MINOR_HW_REVISION_S 20 580 581 // Field: [19:16] HW_PATCH_LEVEL 582 // 583 // 4-bit binary encoding of the hardware patch level, initial release will 584 // carry value zero 585 // Patches are used to remove bugs without changing the functionality or 586 // interface of a module. 587 #define PKA_HWREV_HW_PATCH_LEVEL_W 4 588 #define PKA_HWREV_HW_PATCH_LEVEL_M 0x000F0000 589 #define PKA_HWREV_HW_PATCH_LEVEL_S 16 590 591 // Field: [15:8] COMPLEMENT_OF_BASIC_EIP_NUMBER 592 // 593 // Bit-by-bit logic complement of bits [7:0], EIP-28 gives 0xE3 594 #define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_W 8 595 #define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_M 0x0000FF00 596 #define PKA_HWREV_COMPLEMENT_OF_BASIC_EIP_NUMBER_S 8 597 598 // Field: [7:0] BASIC_EIP_NUMBER 599 // 600 // 8-bit binary encoding of the EIP number, EIP-28 gives 0x1C 601 #define PKA_HWREV_BASIC_EIP_NUMBER_W 8 602 #define PKA_HWREV_BASIC_EIP_NUMBER_M 0x000000FF 603 #define PKA_HWREV_BASIC_EIP_NUMBER_S 0 604 605 606 #endif // __PKA__ 607
