1 /****************************************************************************** 2 * Filename: hw_nvic.h 3 * 4 * Copyright (c) 2015 - 2022, Texas Instruments Incorporated 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1) Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2) Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 18 * be used to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 ******************************************************************************/ 34 35 #ifndef __HW_NVIC_H__ 36 #define __HW_NVIC_H__ 37 38 //***************************************************************************** 39 // 40 // The following are defines for the NVIC register addresses. 41 // 42 //***************************************************************************** 43 #define NVIC_INT_TYPE 0xE000E004 // Interrupt Controller Type Reg 44 #define NVIC_ACTLR 0xE000E008 // Auxiliary Control 45 #define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status 46 // Register 47 #define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register 48 #define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register 49 #define NVIC_ST_CAL 0xE000E01C // SysTick Calibration Value Reg 50 #define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable 51 #define NVIC_EN1 0xE000E104 // Interrupt 32-54 Set Enable 52 #define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable 53 #define NVIC_DIS1 0xE000E184 // Interrupt 32-54 Clear Enable 54 #define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending 55 #define NVIC_PEND1 0xE000E204 // Interrupt 32-54 Set Pending 56 #define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending 57 #define NVIC_UNPEND1 0xE000E284 // Interrupt 32-54 Clear Pending 58 #define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit 59 #define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-54 Active Bit 60 #define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority 61 #define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority 62 #define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority 63 #define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority 64 #define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority 65 #define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority 66 #define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority 67 #define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority 68 #define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority 69 #define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority 70 #define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority 71 #define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority 72 #define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority 73 #define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority 74 #define NVIC_CPUID 0xE000ED00 // CPU ID Base 75 #define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State 76 #define NVIC_VTABLE 0xE000ED08 // Vector Table Offset 77 #define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset 78 // Control 79 #define NVIC_SYS_CTRL 0xE000ED10 // System Control 80 #define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control 81 #define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1 82 #define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2 83 #define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3 84 #define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State 85 #define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status 86 #define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status 87 #define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register 88 #define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address 89 #define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address 90 #define NVIC_MPU_TYPE 0xE000ED90 // MPU Type 91 #define NVIC_MPU_CTRL 0xE000ED94 // MPU Control 92 #define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number 93 #define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address 94 #define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size 95 #define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1 96 #define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size 97 // Alias 1 98 #define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2 99 #define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size 100 // Alias 2 101 #define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3 102 #define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size 103 // Alias 3 104 #define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg 105 #define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select 106 #define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data 107 #define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control 108 #define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt 109 110 //***************************************************************************** 111 // 112 // The following are defines for the bit fields in the NVIC_INT_TYPE register. 113 // 114 //***************************************************************************** 115 #define NVIC_INT_TYPE_LINES_M 0x0000001F // Number of interrupt lines (x32) 116 #define NVIC_INT_TYPE_LINES_S 0 117 118 //***************************************************************************** 119 // 120 // The following are defines for the bit fields in the NVIC_ACTLR register. 121 // 122 //***************************************************************************** 123 #define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding 124 #define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer 125 #define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple 126 // Cycle Instructions 127 128 //***************************************************************************** 129 // 130 // The following are defines for the bit fields in the NVIC_ST_CTRL register. 131 // 132 //***************************************************************************** 133 #define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag 134 #define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source 135 #define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable 136 #define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable 137 138 //***************************************************************************** 139 // 140 // The following are defines for the bit fields in the NVIC_ST_RELOAD register. 141 // 142 //***************************************************************************** 143 #define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value 144 #define NVIC_ST_RELOAD_S 0 145 146 //***************************************************************************** 147 // 148 // The following are defines for the bit fields in the NVIC_ST_CURRENT 149 // register. 150 // 151 //***************************************************************************** 152 #define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value 153 #define NVIC_ST_CURRENT_S 0 154 155 //***************************************************************************** 156 // 157 // The following are defines for the bit fields in the NVIC_ST_CAL register. 158 // 159 //***************************************************************************** 160 #define NVIC_ST_CAL_NOREF 0x80000000 // No reference clock 161 #define NVIC_ST_CAL_SKEW 0x40000000 // Clock skew 162 #define NVIC_ST_CAL_ONEMS_M 0x00FFFFFF // 1ms reference value 163 #define NVIC_ST_CAL_ONEMS_S 0 164 165 //***************************************************************************** 166 // 167 // The following are defines for the bit fields in the NVIC_EN0 register. 168 // 169 //***************************************************************************** 170 #define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable 171 #define NVIC_EN0_INT0 0x00000001 // Interrupt 0 enable 172 #define NVIC_EN0_INT1 0x00000002 // Interrupt 1 enable 173 #define NVIC_EN0_INT2 0x00000004 // Interrupt 2 enable 174 #define NVIC_EN0_INT3 0x00000008 // Interrupt 3 enable 175 #define NVIC_EN0_INT4 0x00000010 // Interrupt 4 enable 176 #define NVIC_EN0_INT5 0x00000020 // Interrupt 5 enable 177 #define NVIC_EN0_INT6 0x00000040 // Interrupt 6 enable 178 #define NVIC_EN0_INT7 0x00000080 // Interrupt 7 enable 179 #define NVIC_EN0_INT8 0x00000100 // Interrupt 8 enable 180 #define NVIC_EN0_INT9 0x00000200 // Interrupt 9 enable 181 #define NVIC_EN0_INT10 0x00000400 // Interrupt 10 enable 182 #define NVIC_EN0_INT11 0x00000800 // Interrupt 11 enable 183 #define NVIC_EN0_INT12 0x00001000 // Interrupt 12 enable 184 #define NVIC_EN0_INT13 0x00002000 // Interrupt 13 enable 185 #define NVIC_EN0_INT14 0x00004000 // Interrupt 14 enable 186 #define NVIC_EN0_INT15 0x00008000 // Interrupt 15 enable 187 #define NVIC_EN0_INT16 0x00010000 // Interrupt 16 enable 188 #define NVIC_EN0_INT17 0x00020000 // Interrupt 17 enable 189 #define NVIC_EN0_INT18 0x00040000 // Interrupt 18 enable 190 #define NVIC_EN0_INT19 0x00080000 // Interrupt 19 enable 191 #define NVIC_EN0_INT20 0x00100000 // Interrupt 20 enable 192 #define NVIC_EN0_INT21 0x00200000 // Interrupt 21 enable 193 #define NVIC_EN0_INT22 0x00400000 // Interrupt 22 enable 194 #define NVIC_EN0_INT23 0x00800000 // Interrupt 23 enable 195 #define NVIC_EN0_INT24 0x01000000 // Interrupt 24 enable 196 #define NVIC_EN0_INT25 0x02000000 // Interrupt 25 enable 197 #define NVIC_EN0_INT26 0x04000000 // Interrupt 26 enable 198 #define NVIC_EN0_INT27 0x08000000 // Interrupt 27 enable 199 #define NVIC_EN0_INT28 0x10000000 // Interrupt 28 enable 200 #define NVIC_EN0_INT29 0x20000000 // Interrupt 29 enable 201 #define NVIC_EN0_INT30 0x40000000 // Interrupt 30 enable 202 #define NVIC_EN0_INT31 0x80000000 // Interrupt 31 enable 203 204 //***************************************************************************** 205 // 206 // The following are defines for the bit fields in the NVIC_EN1 register. 207 // 208 //***************************************************************************** 209 #define NVIC_EN1_INT_M 0x007FFFFF // Interrupt Enable 210 #define NVIC_EN1_INT32 0x00000001 // Interrupt 32 enable 211 #define NVIC_EN1_INT33 0x00000002 // Interrupt 33 enable 212 #define NVIC_EN1_INT34 0x00000004 // Interrupt 34 enable 213 #define NVIC_EN1_INT35 0x00000008 // Interrupt 35 enable 214 #define NVIC_EN1_INT36 0x00000010 // Interrupt 36 enable 215 #define NVIC_EN1_INT37 0x00000020 // Interrupt 37 enable 216 #define NVIC_EN1_INT38 0x00000040 // Interrupt 38 enable 217 #define NVIC_EN1_INT39 0x00000080 // Interrupt 39 enable 218 #define NVIC_EN1_INT40 0x00000100 // Interrupt 40 enable 219 #define NVIC_EN1_INT41 0x00000200 // Interrupt 41 enable 220 #define NVIC_EN1_INT42 0x00000400 // Interrupt 42 enable 221 #define NVIC_EN1_INT43 0x00000800 // Interrupt 43 enable 222 #define NVIC_EN1_INT44 0x00001000 // Interrupt 44 enable 223 #define NVIC_EN1_INT45 0x00002000 // Interrupt 45 enable 224 #define NVIC_EN1_INT46 0x00004000 // Interrupt 46 enable 225 #define NVIC_EN1_INT47 0x00008000 // Interrupt 47 enable 226 #define NVIC_EN1_INT48 0x00010000 // Interrupt 48 enable 227 #define NVIC_EN1_INT49 0x00020000 // Interrupt 49 enable 228 #define NVIC_EN1_INT50 0x00040000 // Interrupt 50 enable 229 #define NVIC_EN1_INT51 0x00080000 // Interrupt 51 enable 230 #define NVIC_EN1_INT52 0x00100000 // Interrupt 52 enable 231 #define NVIC_EN1_INT53 0x00200000 // Interrupt 53 enable 232 #define NVIC_EN1_INT54 0x00400000 // Interrupt 54 enable 233 234 //***************************************************************************** 235 // 236 // The following are defines for the bit fields in the NVIC_DIS0 register. 237 // 238 //***************************************************************************** 239 #define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable 240 #define NVIC_DIS0_INT0 0x00000001 // Interrupt 0 disable 241 #define NVIC_DIS0_INT1 0x00000002 // Interrupt 1 disable 242 #define NVIC_DIS0_INT2 0x00000004 // Interrupt 2 disable 243 #define NVIC_DIS0_INT3 0x00000008 // Interrupt 3 disable 244 #define NVIC_DIS0_INT4 0x00000010 // Interrupt 4 disable 245 #define NVIC_DIS0_INT5 0x00000020 // Interrupt 5 disable 246 #define NVIC_DIS0_INT6 0x00000040 // Interrupt 6 disable 247 #define NVIC_DIS0_INT7 0x00000080 // Interrupt 7 disable 248 #define NVIC_DIS0_INT8 0x00000100 // Interrupt 8 disable 249 #define NVIC_DIS0_INT9 0x00000200 // Interrupt 9 disable 250 #define NVIC_DIS0_INT10 0x00000400 // Interrupt 10 disable 251 #define NVIC_DIS0_INT11 0x00000800 // Interrupt 11 disable 252 #define NVIC_DIS0_INT12 0x00001000 // Interrupt 12 disable 253 #define NVIC_DIS0_INT13 0x00002000 // Interrupt 13 disable 254 #define NVIC_DIS0_INT14 0x00004000 // Interrupt 14 disable 255 #define NVIC_DIS0_INT15 0x00008000 // Interrupt 15 disable 256 #define NVIC_DIS0_INT16 0x00010000 // Interrupt 16 disable 257 #define NVIC_DIS0_INT17 0x00020000 // Interrupt 17 disable 258 #define NVIC_DIS0_INT18 0x00040000 // Interrupt 18 disable 259 #define NVIC_DIS0_INT19 0x00080000 // Interrupt 19 disable 260 #define NVIC_DIS0_INT20 0x00100000 // Interrupt 20 disable 261 #define NVIC_DIS0_INT21 0x00200000 // Interrupt 21 disable 262 #define NVIC_DIS0_INT22 0x00400000 // Interrupt 22 disable 263 #define NVIC_DIS0_INT23 0x00800000 // Interrupt 23 disable 264 #define NVIC_DIS0_INT24 0x01000000 // Interrupt 24 disable 265 #define NVIC_DIS0_INT25 0x02000000 // Interrupt 25 disable 266 #define NVIC_DIS0_INT26 0x04000000 // Interrupt 26 disable 267 #define NVIC_DIS0_INT27 0x08000000 // Interrupt 27 disable 268 #define NVIC_DIS0_INT28 0x10000000 // Interrupt 28 disable 269 #define NVIC_DIS0_INT29 0x20000000 // Interrupt 29 disable 270 #define NVIC_DIS0_INT30 0x40000000 // Interrupt 30 disable 271 #define NVIC_DIS0_INT31 0x80000000 // Interrupt 31 disable 272 273 //***************************************************************************** 274 // 275 // The following are defines for the bit fields in the NVIC_DIS1 register. 276 // 277 //***************************************************************************** 278 #define NVIC_DIS1_INT_M 0x007FFFFF // Interrupt Disable 279 #define NVIC_DIS1_INT32 0x00000001 // Interrupt 32 disable 280 #define NVIC_DIS1_INT33 0x00000002 // Interrupt 33 disable 281 #define NVIC_DIS1_INT34 0x00000004 // Interrupt 34 disable 282 #define NVIC_DIS1_INT35 0x00000008 // Interrupt 35 disable 283 #define NVIC_DIS1_INT36 0x00000010 // Interrupt 36 disable 284 #define NVIC_DIS1_INT37 0x00000020 // Interrupt 37 disable 285 #define NVIC_DIS1_INT38 0x00000040 // Interrupt 38 disable 286 #define NVIC_DIS1_INT39 0x00000080 // Interrupt 39 disable 287 #define NVIC_DIS1_INT40 0x00000100 // Interrupt 40 disable 288 #define NVIC_DIS1_INT41 0x00000200 // Interrupt 41 disable 289 #define NVIC_DIS1_INT42 0x00000400 // Interrupt 42 disable 290 #define NVIC_DIS1_INT43 0x00000800 // Interrupt 43 disable 291 #define NVIC_DIS1_INT44 0x00001000 // Interrupt 44 disable 292 #define NVIC_DIS1_INT45 0x00002000 // Interrupt 45 disable 293 #define NVIC_DIS1_INT46 0x00004000 // Interrupt 46 disable 294 #define NVIC_DIS1_INT47 0x00008000 // Interrupt 47 disable 295 #define NVIC_DIS1_INT48 0x00010000 // Interrupt 48 disable 296 #define NVIC_DIS1_INT49 0x00020000 // Interrupt 49 disable 297 #define NVIC_DIS1_INT50 0x00040000 // Interrupt 50 disable 298 #define NVIC_DIS1_INT51 0x00080000 // Interrupt 51 disable 299 #define NVIC_DIS1_INT52 0x00100000 // Interrupt 52 disable 300 #define NVIC_DIS1_INT53 0x00200000 // Interrupt 53 disable 301 #define NVIC_DIS1_INT54 0x00400000 // Interrupt 54 disable 302 303 //***************************************************************************** 304 // 305 // The following are defines for the bit fields in the NVIC_PEND0 register. 306 // 307 //***************************************************************************** 308 #define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending 309 #define NVIC_PEND0_INT0 0x00000001 // Interrupt 0 pend 310 #define NVIC_PEND0_INT1 0x00000002 // Interrupt 1 pend 311 #define NVIC_PEND0_INT2 0x00000004 // Interrupt 2 pend 312 #define NVIC_PEND0_INT3 0x00000008 // Interrupt 3 pend 313 #define NVIC_PEND0_INT4 0x00000010 // Interrupt 4 pend 314 #define NVIC_PEND0_INT5 0x00000020 // Interrupt 5 pend 315 #define NVIC_PEND0_INT6 0x00000040 // Interrupt 6 pend 316 #define NVIC_PEND0_INT7 0x00000080 // Interrupt 7 pend 317 #define NVIC_PEND0_INT8 0x00000100 // Interrupt 8 pend 318 #define NVIC_PEND0_INT9 0x00000200 // Interrupt 9 pend 319 #define NVIC_PEND0_INT10 0x00000400 // Interrupt 10 pend 320 #define NVIC_PEND0_INT11 0x00000800 // Interrupt 11 pend 321 #define NVIC_PEND0_INT12 0x00001000 // Interrupt 12 pend 322 #define NVIC_PEND0_INT13 0x00002000 // Interrupt 13 pend 323 #define NVIC_PEND0_INT14 0x00004000 // Interrupt 14 pend 324 #define NVIC_PEND0_INT15 0x00008000 // Interrupt 15 pend 325 #define NVIC_PEND0_INT16 0x00010000 // Interrupt 16 pend 326 #define NVIC_PEND0_INT17 0x00020000 // Interrupt 17 pend 327 #define NVIC_PEND0_INT18 0x00040000 // Interrupt 18 pend 328 #define NVIC_PEND0_INT19 0x00080000 // Interrupt 19 pend 329 #define NVIC_PEND0_INT20 0x00100000 // Interrupt 20 pend 330 #define NVIC_PEND0_INT21 0x00200000 // Interrupt 21 pend 331 #define NVIC_PEND0_INT22 0x00400000 // Interrupt 22 pend 332 #define NVIC_PEND0_INT23 0x00800000 // Interrupt 23 pend 333 #define NVIC_PEND0_INT24 0x01000000 // Interrupt 24 pend 334 #define NVIC_PEND0_INT25 0x02000000 // Interrupt 25 pend 335 #define NVIC_PEND0_INT26 0x04000000 // Interrupt 26 pend 336 #define NVIC_PEND0_INT27 0x08000000 // Interrupt 27 pend 337 #define NVIC_PEND0_INT28 0x10000000 // Interrupt 28 pend 338 #define NVIC_PEND0_INT29 0x20000000 // Interrupt 29 pend 339 #define NVIC_PEND0_INT30 0x40000000 // Interrupt 30 pend 340 #define NVIC_PEND0_INT31 0x80000000 // Interrupt 31 pend 341 342 //***************************************************************************** 343 // 344 // The following are defines for the bit fields in the NVIC_PEND1 register. 345 // 346 //***************************************************************************** 347 #define NVIC_PEND1_INT_M 0x007FFFFF // Interrupt Set Pending 348 #define NVIC_PEND1_INT32 0x00000001 // Interrupt 32 pend 349 #define NVIC_PEND1_INT33 0x00000002 // Interrupt 33 pend 350 #define NVIC_PEND1_INT34 0x00000004 // Interrupt 34 pend 351 #define NVIC_PEND1_INT35 0x00000008 // Interrupt 35 pend 352 #define NVIC_PEND1_INT36 0x00000010 // Interrupt 36 pend 353 #define NVIC_PEND1_INT37 0x00000020 // Interrupt 37 pend 354 #define NVIC_PEND1_INT38 0x00000040 // Interrupt 38 pend 355 #define NVIC_PEND1_INT39 0x00000080 // Interrupt 39 pend 356 #define NVIC_PEND1_INT40 0x00000100 // Interrupt 40 pend 357 #define NVIC_PEND1_INT41 0x00000200 // Interrupt 41 pend 358 #define NVIC_PEND1_INT42 0x00000400 // Interrupt 42 pend 359 #define NVIC_PEND1_INT43 0x00000800 // Interrupt 43 pend 360 #define NVIC_PEND1_INT44 0x00001000 // Interrupt 44 pend 361 #define NVIC_PEND1_INT45 0x00002000 // Interrupt 45 pend 362 #define NVIC_PEND1_INT46 0x00004000 // Interrupt 46 pend 363 #define NVIC_PEND1_INT47 0x00008000 // Interrupt 47 pend 364 #define NVIC_PEND1_INT48 0x00010000 // Interrupt 48 pend 365 #define NVIC_PEND1_INT49 0x00020000 // Interrupt 49 pend 366 #define NVIC_PEND1_INT50 0x00040000 // Interrupt 50 pend 367 #define NVIC_PEND1_INT51 0x00080000 // Interrupt 51 pend 368 #define NVIC_PEND1_INT52 0x00100000 // Interrupt 52 pend 369 #define NVIC_PEND1_INT53 0x00200000 // Interrupt 53 pend 370 #define NVIC_PEND1_INT54 0x00400000 // Interrupt 54 pend 371 372 //***************************************************************************** 373 // 374 // The following are defines for the bit fields in the NVIC_UNPEND0 register. 375 // 376 //***************************************************************************** 377 #define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending 378 #define NVIC_UNPEND0_INT0 0x00000001 // Interrupt 0 unpend 379 #define NVIC_UNPEND0_INT1 0x00000002 // Interrupt 1 unpend 380 #define NVIC_UNPEND0_INT2 0x00000004 // Interrupt 2 unpend 381 #define NVIC_UNPEND0_INT3 0x00000008 // Interrupt 3 unpend 382 #define NVIC_UNPEND0_INT4 0x00000010 // Interrupt 4 unpend 383 #define NVIC_UNPEND0_INT5 0x00000020 // Interrupt 5 unpend 384 #define NVIC_UNPEND0_INT6 0x00000040 // Interrupt 6 unpend 385 #define NVIC_UNPEND0_INT7 0x00000080 // Interrupt 7 unpend 386 #define NVIC_UNPEND0_INT8 0x00000100 // Interrupt 8 unpend 387 #define NVIC_UNPEND0_INT9 0x00000200 // Interrupt 9 unpend 388 #define NVIC_UNPEND0_INT10 0x00000400 // Interrupt 10 unpend 389 #define NVIC_UNPEND0_INT11 0x00000800 // Interrupt 11 unpend 390 #define NVIC_UNPEND0_INT12 0x00001000 // Interrupt 12 unpend 391 #define NVIC_UNPEND0_INT13 0x00002000 // Interrupt 13 unpend 392 #define NVIC_UNPEND0_INT14 0x00004000 // Interrupt 14 unpend 393 #define NVIC_UNPEND0_INT15 0x00008000 // Interrupt 15 unpend 394 #define NVIC_UNPEND0_INT16 0x00010000 // Interrupt 16 unpend 395 #define NVIC_UNPEND0_INT17 0x00020000 // Interrupt 17 unpend 396 #define NVIC_UNPEND0_INT18 0x00040000 // Interrupt 18 unpend 397 #define NVIC_UNPEND0_INT19 0x00080000 // Interrupt 19 unpend 398 #define NVIC_UNPEND0_INT20 0x00100000 // Interrupt 20 unpend 399 #define NVIC_UNPEND0_INT21 0x00200000 // Interrupt 21 unpend 400 #define NVIC_UNPEND0_INT22 0x00400000 // Interrupt 22 unpend 401 #define NVIC_UNPEND0_INT23 0x00800000 // Interrupt 23 unpend 402 #define NVIC_UNPEND0_INT24 0x01000000 // Interrupt 24 unpend 403 #define NVIC_UNPEND0_INT25 0x02000000 // Interrupt 25 unpend 404 #define NVIC_UNPEND0_INT26 0x04000000 // Interrupt 26 unpend 405 #define NVIC_UNPEND0_INT27 0x08000000 // Interrupt 27 unpend 406 #define NVIC_UNPEND0_INT28 0x10000000 // Interrupt 28 unpend 407 #define NVIC_UNPEND0_INT29 0x20000000 // Interrupt 29 unpend 408 #define NVIC_UNPEND0_INT30 0x40000000 // Interrupt 30 unpend 409 #define NVIC_UNPEND0_INT31 0x80000000 // Interrupt 31 unpend 410 411 //***************************************************************************** 412 // 413 // The following are defines for the bit fields in the NVIC_UNPEND1 register. 414 // 415 //***************************************************************************** 416 #define NVIC_UNPEND1_INT_M 0x007FFFFF // Interrupt Clear Pending 417 #define NVIC_UNPEND1_INT32 0x00000001 // Interrupt 32 unpend 418 #define NVIC_UNPEND1_INT33 0x00000002 // Interrupt 33 unpend 419 #define NVIC_UNPEND1_INT34 0x00000004 // Interrupt 34 unpend 420 #define NVIC_UNPEND1_INT35 0x00000008 // Interrupt 35 unpend 421 #define NVIC_UNPEND1_INT36 0x00000010 // Interrupt 36 unpend 422 #define NVIC_UNPEND1_INT37 0x00000020 // Interrupt 37 unpend 423 #define NVIC_UNPEND1_INT38 0x00000040 // Interrupt 38 unpend 424 #define NVIC_UNPEND1_INT39 0x00000080 // Interrupt 39 unpend 425 #define NVIC_UNPEND1_INT40 0x00000100 // Interrupt 40 unpend 426 #define NVIC_UNPEND1_INT41 0x00000200 // Interrupt 41 unpend 427 #define NVIC_UNPEND1_INT42 0x00000400 // Interrupt 42 unpend 428 #define NVIC_UNPEND1_INT43 0x00000800 // Interrupt 43 unpend 429 #define NVIC_UNPEND1_INT44 0x00001000 // Interrupt 44 unpend 430 #define NVIC_UNPEND1_INT45 0x00002000 // Interrupt 45 unpend 431 #define NVIC_UNPEND1_INT46 0x00004000 // Interrupt 46 unpend 432 #define NVIC_UNPEND1_INT47 0x00008000 // Interrupt 47 unpend 433 #define NVIC_UNPEND1_INT48 0x00010000 // Interrupt 48 unpend 434 #define NVIC_UNPEND1_INT49 0x00020000 // Interrupt 49 unpend 435 #define NVIC_UNPEND1_INT50 0x00040000 // Interrupt 50 unpend 436 #define NVIC_UNPEND1_INT51 0x00080000 // Interrupt 51 unpend 437 #define NVIC_UNPEND1_INT52 0x00100000 // Interrupt 52 unpend 438 #define NVIC_UNPEND1_INT53 0x00200000 // Interrupt 53 unpend 439 #define NVIC_UNPEND1_INT54 0x00400000 // Interrupt 54 unpend 440 441 //***************************************************************************** 442 // 443 // The following are defines for the bit fields in the NVIC_ACTIVE0 register. 444 // 445 //***************************************************************************** 446 #define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active 447 #define NVIC_ACTIVE0_INT0 0x00000001 // Interrupt 0 active 448 #define NVIC_ACTIVE0_INT1 0x00000002 // Interrupt 1 active 449 #define NVIC_ACTIVE0_INT2 0x00000004 // Interrupt 2 active 450 #define NVIC_ACTIVE0_INT3 0x00000008 // Interrupt 3 active 451 #define NVIC_ACTIVE0_INT4 0x00000010 // Interrupt 4 active 452 #define NVIC_ACTIVE0_INT5 0x00000020 // Interrupt 5 active 453 #define NVIC_ACTIVE0_INT6 0x00000040 // Interrupt 6 active 454 #define NVIC_ACTIVE0_INT7 0x00000080 // Interrupt 7 active 455 #define NVIC_ACTIVE0_INT8 0x00000100 // Interrupt 8 active 456 #define NVIC_ACTIVE0_INT9 0x00000200 // Interrupt 9 active 457 #define NVIC_ACTIVE0_INT10 0x00000400 // Interrupt 10 active 458 #define NVIC_ACTIVE0_INT11 0x00000800 // Interrupt 11 active 459 #define NVIC_ACTIVE0_INT12 0x00001000 // Interrupt 12 active 460 #define NVIC_ACTIVE0_INT13 0x00002000 // Interrupt 13 active 461 #define NVIC_ACTIVE0_INT14 0x00004000 // Interrupt 14 active 462 #define NVIC_ACTIVE0_INT15 0x00008000 // Interrupt 15 active 463 #define NVIC_ACTIVE0_INT16 0x00010000 // Interrupt 16 active 464 #define NVIC_ACTIVE0_INT17 0x00020000 // Interrupt 17 active 465 #define NVIC_ACTIVE0_INT18 0x00040000 // Interrupt 18 active 466 #define NVIC_ACTIVE0_INT19 0x00080000 // Interrupt 19 active 467 #define NVIC_ACTIVE0_INT20 0x00100000 // Interrupt 20 active 468 #define NVIC_ACTIVE0_INT21 0x00200000 // Interrupt 21 active 469 #define NVIC_ACTIVE0_INT22 0x00400000 // Interrupt 22 active 470 #define NVIC_ACTIVE0_INT23 0x00800000 // Interrupt 23 active 471 #define NVIC_ACTIVE0_INT24 0x01000000 // Interrupt 24 active 472 #define NVIC_ACTIVE0_INT25 0x02000000 // Interrupt 25 active 473 #define NVIC_ACTIVE0_INT26 0x04000000 // Interrupt 26 active 474 #define NVIC_ACTIVE0_INT27 0x08000000 // Interrupt 27 active 475 #define NVIC_ACTIVE0_INT28 0x10000000 // Interrupt 28 active 476 #define NVIC_ACTIVE0_INT29 0x20000000 // Interrupt 29 active 477 #define NVIC_ACTIVE0_INT30 0x40000000 // Interrupt 30 active 478 #define NVIC_ACTIVE0_INT31 0x80000000 // Interrupt 31 active 479 480 //***************************************************************************** 481 // 482 // The following are defines for the bit fields in the NVIC_ACTIVE1 register. 483 // 484 //***************************************************************************** 485 #define NVIC_ACTIVE1_INT_M 0x007FFFFF // Interrupt Active 486 #define NVIC_ACTIVE1_INT32 0x00000001 // Interrupt 32 active 487 #define NVIC_ACTIVE1_INT33 0x00000002 // Interrupt 33 active 488 #define NVIC_ACTIVE1_INT34 0x00000004 // Interrupt 34 active 489 #define NVIC_ACTIVE1_INT35 0x00000008 // Interrupt 35 active 490 #define NVIC_ACTIVE1_INT36 0x00000010 // Interrupt 36 active 491 #define NVIC_ACTIVE1_INT37 0x00000020 // Interrupt 37 active 492 #define NVIC_ACTIVE1_INT38 0x00000040 // Interrupt 38 active 493 #define NVIC_ACTIVE1_INT39 0x00000080 // Interrupt 39 active 494 #define NVIC_ACTIVE1_INT40 0x00000100 // Interrupt 40 active 495 #define NVIC_ACTIVE1_INT41 0x00000200 // Interrupt 41 active 496 #define NVIC_ACTIVE1_INT42 0x00000400 // Interrupt 42 active 497 #define NVIC_ACTIVE1_INT43 0x00000800 // Interrupt 43 active 498 #define NVIC_ACTIVE1_INT44 0x00001000 // Interrupt 44 active 499 #define NVIC_ACTIVE1_INT45 0x00002000 // Interrupt 45 active 500 #define NVIC_ACTIVE1_INT46 0x00004000 // Interrupt 46 active 501 #define NVIC_ACTIVE1_INT47 0x00008000 // Interrupt 47 active 502 #define NVIC_ACTIVE1_INT48 0x00010000 // Interrupt 48 active 503 #define NVIC_ACTIVE1_INT49 0x00020000 // Interrupt 49 active 504 #define NVIC_ACTIVE1_INT50 0x00040000 // Interrupt 50 active 505 #define NVIC_ACTIVE1_INT51 0x00080000 // Interrupt 51 active 506 #define NVIC_ACTIVE1_INT52 0x00100000 // Interrupt 52 active 507 #define NVIC_ACTIVE1_INT53 0x00200000 // Interrupt 53 active 508 #define NVIC_ACTIVE1_INT54 0x00400000 // Interrupt 54 active 509 510 //***************************************************************************** 511 // 512 // The following are defines for the bit fields in the NVIC_PRI0 register. 513 // 514 //***************************************************************************** 515 #define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask 516 #define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask 517 #define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask 518 #define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask 519 #define NVIC_PRI0_INT3_S 29 520 #define NVIC_PRI0_INT2_S 21 521 #define NVIC_PRI0_INT1_S 13 522 #define NVIC_PRI0_INT0_S 5 523 524 //***************************************************************************** 525 // 526 // The following are defines for the bit fields in the NVIC_PRI1 register. 527 // 528 //***************************************************************************** 529 #define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask 530 #define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask 531 #define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask 532 #define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask 533 #define NVIC_PRI1_INT7_S 29 534 #define NVIC_PRI1_INT6_S 21 535 #define NVIC_PRI1_INT5_S 13 536 #define NVIC_PRI1_INT4_S 5 537 538 //***************************************************************************** 539 // 540 // The following are defines for the bit fields in the NVIC_PRI2 register. 541 // 542 //***************************************************************************** 543 #define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask 544 #define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask 545 #define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask 546 #define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask 547 #define NVIC_PRI2_INT11_S 29 548 #define NVIC_PRI2_INT10_S 21 549 #define NVIC_PRI2_INT9_S 13 550 #define NVIC_PRI2_INT8_S 5 551 552 //***************************************************************************** 553 // 554 // The following are defines for the bit fields in the NVIC_PRI3 register. 555 // 556 //***************************************************************************** 557 #define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask 558 #define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask 559 #define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask 560 #define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask 561 #define NVIC_PRI3_INT15_S 29 562 #define NVIC_PRI3_INT14_S 21 563 #define NVIC_PRI3_INT13_S 13 564 #define NVIC_PRI3_INT12_S 5 565 566 //***************************************************************************** 567 // 568 // The following are defines for the bit fields in the NVIC_PRI4 register. 569 // 570 //***************************************************************************** 571 #define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask 572 #define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask 573 #define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask 574 #define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask 575 #define NVIC_PRI4_INT19_S 29 576 #define NVIC_PRI4_INT18_S 21 577 #define NVIC_PRI4_INT17_S 13 578 #define NVIC_PRI4_INT16_S 5 579 580 //***************************************************************************** 581 // 582 // The following are defines for the bit fields in the NVIC_PRI5 register. 583 // 584 //***************************************************************************** 585 #define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask 586 #define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask 587 #define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask 588 #define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask 589 #define NVIC_PRI5_INT23_S 29 590 #define NVIC_PRI5_INT22_S 21 591 #define NVIC_PRI5_INT21_S 13 592 #define NVIC_PRI5_INT20_S 5 593 594 //***************************************************************************** 595 // 596 // The following are defines for the bit fields in the NVIC_PRI6 register. 597 // 598 //***************************************************************************** 599 #define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask 600 #define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask 601 #define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask 602 #define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask 603 #define NVIC_PRI6_INT27_S 29 604 #define NVIC_PRI6_INT26_S 21 605 #define NVIC_PRI6_INT25_S 13 606 #define NVIC_PRI6_INT24_S 5 607 608 //***************************************************************************** 609 // 610 // The following are defines for the bit fields in the NVIC_PRI7 register. 611 // 612 //***************************************************************************** 613 #define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask 614 #define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask 615 #define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask 616 #define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask 617 #define NVIC_PRI7_INT31_S 29 618 #define NVIC_PRI7_INT30_S 21 619 #define NVIC_PRI7_INT29_S 13 620 #define NVIC_PRI7_INT28_S 5 621 622 //***************************************************************************** 623 // 624 // The following are defines for the bit fields in the NVIC_PRI8 register. 625 // 626 //***************************************************************************** 627 #define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask 628 #define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask 629 #define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask 630 #define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask 631 #define NVIC_PRI8_INT35_S 29 632 #define NVIC_PRI8_INT34_S 21 633 #define NVIC_PRI8_INT33_S 13 634 #define NVIC_PRI8_INT32_S 5 635 636 //***************************************************************************** 637 // 638 // The following are defines for the bit fields in the NVIC_PRI9 register. 639 // 640 //***************************************************************************** 641 #define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask 642 #define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask 643 #define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask 644 #define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask 645 #define NVIC_PRI9_INT39_S 29 646 #define NVIC_PRI9_INT38_S 21 647 #define NVIC_PRI9_INT37_S 13 648 #define NVIC_PRI9_INT36_S 5 649 650 //***************************************************************************** 651 // 652 // The following are defines for the bit fields in the NVIC_PRI10 register. 653 // 654 //***************************************************************************** 655 #define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask 656 #define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask 657 #define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask 658 #define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask 659 #define NVIC_PRI10_INT43_S 29 660 #define NVIC_PRI10_INT42_S 21 661 #define NVIC_PRI10_INT41_S 13 662 #define NVIC_PRI10_INT40_S 5 663 664 //***************************************************************************** 665 // 666 // The following are defines for the bit fields in the NVIC_PRI11 register. 667 // 668 //***************************************************************************** 669 #define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask 670 #define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask 671 #define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask 672 #define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask 673 #define NVIC_PRI11_INT47_S 29 674 #define NVIC_PRI11_INT46_S 21 675 #define NVIC_PRI11_INT45_S 13 676 #define NVIC_PRI11_INT44_S 5 677 678 //***************************************************************************** 679 // 680 // The following are defines for the bit fields in the NVIC_PRI12 register. 681 // 682 //***************************************************************************** 683 #define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask 684 #define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask 685 #define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask 686 #define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask 687 #define NVIC_PRI12_INT51_S 29 688 #define NVIC_PRI12_INT50_S 21 689 #define NVIC_PRI12_INT49_S 13 690 #define NVIC_PRI12_INT48_S 5 691 692 //***************************************************************************** 693 // 694 // The following are defines for the bit fields in the NVIC_PRI13 register. 695 // 696 //***************************************************************************** 697 #define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask 698 #define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask 699 #define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask 700 #define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask 701 #define NVIC_PRI13_INT55_S 29 702 #define NVIC_PRI13_INT54_S 21 703 #define NVIC_PRI13_INT53_S 13 704 #define NVIC_PRI13_INT52_S 5 705 706 //***************************************************************************** 707 // 708 // The following are defines for the bit fields in the NVIC_CPUID register. 709 // 710 //***************************************************************************** 711 #define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code 712 #define NVIC_CPUID_IMP_ARM 0x41000000 // ARM 713 #define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number 714 #define NVIC_CPUID_CON_M 0x000F0000 // Constant 715 #define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number 716 #define NVIC_CPUID_PARTNO_CM3 0x0000C230 // Cortex-M3 processor 717 #define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor 718 #define NVIC_CPUID_REV_M 0x0000000F // Revision Number 719 720 //***************************************************************************** 721 // 722 // The following are defines for the bit fields in the NVIC_INT_CTRL register. 723 // 724 //***************************************************************************** 725 #define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending 726 #define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending 727 #define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending 728 #define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending 729 #define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending 730 #define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling 731 #define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending 732 #define NVIC_INT_CTRL_VEC_PEN_M 0x0007F000 // Interrupt Pending Vector Number 733 #undef NVIC_INT_CTRL_VEC_PEN_M 734 #define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number 735 #define NVIC_INT_CTRL_VEC_PEN_NMI \ 736 0x00002000 // NMI 737 #define NVIC_INT_CTRL_VEC_PEN_HARD \ 738 0x00003000 // Hard fault 739 #define NVIC_INT_CTRL_VEC_PEN_MEM \ 740 0x00004000 // Memory management fault 741 #define NVIC_INT_CTRL_VEC_PEN_BUS \ 742 0x00005000 // Bus fault 743 #define NVIC_INT_CTRL_VEC_PEN_USG \ 744 0x00006000 // Usage fault 745 #define NVIC_INT_CTRL_VEC_PEN_SVC \ 746 0x0000B000 // SVCall 747 #define NVIC_INT_CTRL_VEC_PEN_PNDSV \ 748 0x0000E000 // PendSV 749 #define NVIC_INT_CTRL_VEC_PEN_TICK \ 750 0x0000F000 // SysTick 751 #define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base 752 #define NVIC_INT_CTRL_VEC_ACT_M 0x0000007F // Interrupt Pending Vector Number 753 #undef NVIC_INT_CTRL_VEC_ACT_M 754 #define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number 755 #define NVIC_INT_CTRL_VEC_PEN_S 12 756 #define NVIC_INT_CTRL_VEC_ACT_S 0 757 758 //***************************************************************************** 759 // 760 // The following are defines for the bit fields in the NVIC_VTABLE register. 761 // 762 //***************************************************************************** 763 #define NVIC_VTABLE_BASE 0x20000000 // Vector Table Base 764 #define NVIC_VTABLE_OFFSET_M 0x1FFFFE00 // Vector Table Offset 765 #undef NVIC_VTABLE_OFFSET_M 766 #define NVIC_VTABLE_OFFSET_M 0x1FFFFC00 // Vector Table Offset 767 #define NVIC_VTABLE_OFFSET_S 9 768 #undef NVIC_VTABLE_OFFSET_S 769 #define NVIC_VTABLE_OFFSET_S 10 770 771 //***************************************************************************** 772 // 773 // The following are defines for the bit fields in the NVIC_APINT register. 774 // 775 //***************************************************************************** 776 #define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key 777 #define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key 778 #define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess 779 #define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping 780 #define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split 781 #define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split 782 #define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split 783 #define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split 784 #define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split 785 #define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split 786 #define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split 787 #define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split 788 #define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request 789 #define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault 790 #define NVIC_APINT_VECT_RESET 0x00000001 // System Reset 791 792 //***************************************************************************** 793 // 794 // The following are defines for the bit fields in the NVIC_SYS_CTRL register. 795 // 796 //***************************************************************************** 797 #define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending 798 #define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable 799 #define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit 800 801 //***************************************************************************** 802 // 803 // The following are defines for the bit fields in the NVIC_CFG_CTRL register. 804 // 805 //***************************************************************************** 806 #define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception 807 // Entry 808 #define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and 809 // Fault 810 #define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0 811 #define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access 812 #define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger 813 #define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control 814 815 //***************************************************************************** 816 // 817 // The following are defines for the bit fields in the NVIC_SYS_PRI1 register. 818 // 819 //***************************************************************************** 820 #define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority 821 #define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority 822 #define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority 823 #define NVIC_SYS_PRI1_USAGE_S 21 824 #define NVIC_SYS_PRI1_BUS_S 13 825 #define NVIC_SYS_PRI1_MEM_S 5 826 827 //***************************************************************************** 828 // 829 // The following are defines for the bit fields in the NVIC_SYS_PRI2 register. 830 // 831 //***************************************************************************** 832 #define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority 833 #define NVIC_SYS_PRI2_SVC_S 29 834 835 //***************************************************************************** 836 // 837 // The following are defines for the bit fields in the NVIC_SYS_PRI3 register. 838 // 839 //***************************************************************************** 840 #define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority 841 #define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority 842 #define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority 843 #define NVIC_SYS_PRI3_TICK_S 29 844 #define NVIC_SYS_PRI3_PENDSV_S 21 845 #define NVIC_SYS_PRI3_DEBUG_S 5 846 847 //***************************************************************************** 848 // 849 // The following are defines for the bit fields in the NVIC_SYS_HND_CTRL 850 // register. 851 // 852 //***************************************************************************** 853 #define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable 854 #define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable 855 #define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable 856 #define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending 857 #define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending 858 #define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending 859 #define NVIC_SYS_HND_CTRL_USAGEP \ 860 0x00001000 // Usage Fault Pending 861 #define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active 862 #define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active 863 #define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active 864 #define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active 865 #define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active 866 #define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active 867 #define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active 868 869 //***************************************************************************** 870 // 871 // The following are defines for the bit fields in the NVIC_FAULT_STAT 872 // register. 873 // 874 //***************************************************************************** 875 #define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault 876 #define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault 877 #define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault 878 #define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault 879 #define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault 880 #define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage 881 // Fault 882 #define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid 883 #define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy 884 // State Preservation 885 #define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault 886 #define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault 887 #define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error 888 #define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error 889 #define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error 890 #define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address 891 // Register Valid 892 #define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on 893 // Floating-Point Lazy State 894 // Preservation 895 #define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation 896 #define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation 897 #define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation 898 #define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation 899 900 //***************************************************************************** 901 // 902 // The following are defines for the bit fields in the NVIC_HFAULT_STAT 903 // register. 904 // 905 //***************************************************************************** 906 #define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event 907 #define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault 908 #define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault 909 910 //***************************************************************************** 911 // 912 // The following are defines for the bit fields in the NVIC_DEBUG_STAT 913 // register. 914 // 915 //***************************************************************************** 916 #define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted 917 #define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch 918 #define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match 919 #define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction 920 #define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request 921 922 //***************************************************************************** 923 // 924 // The following are defines for the bit fields in the NVIC_MM_ADDR register. 925 // 926 //***************************************************************************** 927 #define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address 928 #define NVIC_MM_ADDR_S 0 929 930 //***************************************************************************** 931 // 932 // The following are defines for the bit fields in the NVIC_FAULT_ADDR 933 // register. 934 // 935 //***************************************************************************** 936 #define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address 937 #define NVIC_FAULT_ADDR_S 0 938 939 //***************************************************************************** 940 // 941 // The following are defines for the bit fields in the NVIC_DBG_CTRL register. 942 // 943 //***************************************************************************** 944 #define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask 945 #define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key 946 #define NVIC_DBG_CTRL_S_RESET_ST \ 947 0x02000000 // Core has reset since last read 948 #define NVIC_DBG_CTRL_S_RETIRE_ST \ 949 0x01000000 // Core has executed insruction 950 // since last read 951 #define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up 952 #define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping 953 #define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt 954 #define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available 955 #define NVIC_DBG_CTRL_C_SNAPSTALL \ 956 0x00000020 // Breaks a stalled load/store 957 #define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping 958 #define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core 959 #define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core 960 #define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug 961 962 //***************************************************************************** 963 // 964 // The following are defines for the bit fields in the NVIC_DBG_XFER register. 965 // 966 //***************************************************************************** 967 #define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read 968 #define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register 969 #define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0 970 #define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1 971 #define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2 972 #define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3 973 #define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4 974 #define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5 975 #define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6 976 #define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7 977 #define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8 978 #define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9 979 #define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10 980 #define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11 981 #define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12 982 #define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13 983 #define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14 984 #define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15 985 #define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register 986 #define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP 987 #define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP 988 #define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP 989 #define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask 990 991 //***************************************************************************** 992 // 993 // The following are defines for the bit fields in the NVIC_DBG_DATA register. 994 // 995 //***************************************************************************** 996 #define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache 997 #define NVIC_DBG_DATA_S 0 998 999 //***************************************************************************** 1000 // 1001 // The following are defines for the bit fields in the NVIC_DBG_INT register. 1002 // 1003 //***************************************************************************** 1004 #define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault 1005 #define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors 1006 #define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error 1007 #define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state 1008 #define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check 1009 #define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error 1010 #define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault 1011 #define NVIC_DBG_INT_RESET 0x00000008 // Core reset status 1012 #define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset 1013 #define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending 1014 #define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch 1015 1016 //***************************************************************************** 1017 // 1018 // The following are defines for the bit fields in the NVIC_SW_TRIG register. 1019 // 1020 //***************************************************************************** 1021 #define NVIC_SW_TRIG_INTID_M 0x0000003F // Interrupt ID 1022 #define NVIC_SW_TRIG_INTID_S 0 1023 1024 #endif // __HW_NVIC_H__ 1025
