1 /****************************************************************************** 2 * Filename: hw_i2s_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_I2S_H__ 38 #define __HW_I2S_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // I2S component 44 // 45 //***************************************************************************** 46 // WCLK Source Selection 47 #define I2S_O_AIFWCLKSRC 0x00000000 48 49 // DMA Buffer Size Configuration 50 #define I2S_O_AIFDMACFG 0x00000004 51 52 // Pin Direction 53 #define I2S_O_AIFDIRCFG 0x00000008 54 55 // Serial Interface Format Configuration 56 #define I2S_O_AIFFMTCFG 0x0000000C 57 58 // Word Selection Bit Mask for Pin 0 59 #define I2S_O_AIFWMASK0 0x00000010 60 61 // Word Selection Bit Mask for Pin 1 62 #define I2S_O_AIFWMASK1 0x00000014 63 64 // Audio Interface PWM Debug Value 65 #define I2S_O_AIFPWMVALUE 0x0000001C 66 67 // DMA Input Buffer Next Pointer 68 #define I2S_O_AIFINPTRNEXT 0x00000020 69 70 // DMA Input Buffer Current Pointer 71 #define I2S_O_AIFINPTR 0x00000024 72 73 // DMA Output Buffer Next Pointer 74 #define I2S_O_AIFOUTPTRNEXT 0x00000028 75 76 // DMA Output Buffer Current Pointer 77 #define I2S_O_AIFOUTPTR 0x0000002C 78 79 // Samplestamp Generator Control Register 80 #define I2S_O_STMPCTL 0x00000034 81 82 // Captured XOSC Counter Value, Capture Channel 0 83 #define I2S_O_STMPXCNTCAPT0 0x00000038 84 85 // XOSC Period Value 86 #define I2S_O_STMPXPER 0x0000003C 87 88 // Captured WCLK Counter Value, Capture Channel 0 89 #define I2S_O_STMPWCNTCAPT0 0x00000040 90 91 // WCLK Counter Period Value 92 #define I2S_O_STMPWPER 0x00000044 93 94 // WCLK Counter Trigger Value for Input Pins 95 #define I2S_O_STMPINTRIG 0x00000048 96 97 // WCLK Counter Trigger Value for Output Pins 98 #define I2S_O_STMPOUTTRIG 0x0000004C 99 100 // WCLK Counter Set Operation 101 #define I2S_O_STMPWSET 0x00000050 102 103 // WCLK Counter Add Operation 104 #define I2S_O_STMPWADD 0x00000054 105 106 // XOSC Minimum Period Value 107 #define I2S_O_STMPXPERMIN 0x00000058 108 109 // Current Value of WCNT 110 #define I2S_O_STMPWCNT 0x0000005C 111 112 // Current Value of XCNT 113 #define I2S_O_STMPXCNT 0x00000060 114 115 // Internal 116 #define I2S_O_STMPXCNTCAPT1 0x00000064 117 118 // Internal 119 #define I2S_O_STMPWCNTCAPT1 0x00000068 120 121 // Interrupt Mask Register 122 #define I2S_O_IRQMASK 0x00000070 123 124 // Raw Interrupt Status Register 125 #define I2S_O_IRQFLAGS 0x00000074 126 127 // Interrupt Set Register 128 #define I2S_O_IRQSET 0x00000078 129 130 // Interrupt Clear Register 131 #define I2S_O_IRQCLR 0x0000007C 132 133 //***************************************************************************** 134 // 135 // Register: I2S_O_AIFWCLKSRC 136 // 137 //***************************************************************************** 138 // Field: [2] WCLK_INV 139 // 140 // Inverts WCLK source (pad or internal) when set. 141 // 142 // 0: Not inverted 143 // 1: Inverted 144 #define I2S_AIFWCLKSRC_WCLK_INV 0x00000004 145 #define I2S_AIFWCLKSRC_WCLK_INV_BITN 2 146 #define I2S_AIFWCLKSRC_WCLK_INV_M 0x00000004 147 #define I2S_AIFWCLKSRC_WCLK_INV_S 2 148 149 // Field: [1:0] WCLK_SRC 150 // 151 // Selects WCLK source for AIF (should be the same as the BCLK source). The 152 // BCLK source is defined in the PRCM:I2SBCLKSEL.SRC 153 // ENUMs: 154 // RESERVED Not supported. Will give same WCLK as 'NONE' 155 // ('00') 156 // INT Internal WCLK generator, from module PRCM 157 // EXT External WCLK generator, from pad 158 // NONE None ('0') 159 #define I2S_AIFWCLKSRC_WCLK_SRC_W 2 160 #define I2S_AIFWCLKSRC_WCLK_SRC_M 0x00000003 161 #define I2S_AIFWCLKSRC_WCLK_SRC_S 0 162 #define I2S_AIFWCLKSRC_WCLK_SRC_RESERVED 0x00000003 163 #define I2S_AIFWCLKSRC_WCLK_SRC_INT 0x00000002 164 #define I2S_AIFWCLKSRC_WCLK_SRC_EXT 0x00000001 165 #define I2S_AIFWCLKSRC_WCLK_SRC_NONE 0x00000000 166 167 //***************************************************************************** 168 // 169 // Register: I2S_O_AIFDMACFG 170 // 171 //***************************************************************************** 172 // Field: [7:0] END_FRAME_IDX 173 // 174 // Defines the length of the DMA buffer. Writing a non-zero value to this 175 // register field enables and initializes AIF. Note that before doing so, all 176 // other configuration must have been done, and AIFINPTRNEXT/AIFOUTPTRNEXT must 177 // have been loaded. 178 #define I2S_AIFDMACFG_END_FRAME_IDX_W 8 179 #define I2S_AIFDMACFG_END_FRAME_IDX_M 0x000000FF 180 #define I2S_AIFDMACFG_END_FRAME_IDX_S 0 181 182 //***************************************************************************** 183 // 184 // Register: I2S_O_AIFDIRCFG 185 // 186 //***************************************************************************** 187 // Field: [5:4] AD1 188 // 189 // Configures the AD1 audio data pin usage: 190 // 191 // 0x3: Reserved 192 // ENUMs: 193 // OUT Output mode 194 // IN Input mode 195 // DIS Not in use (disabled) 196 #define I2S_AIFDIRCFG_AD1_W 2 197 #define I2S_AIFDIRCFG_AD1_M 0x00000030 198 #define I2S_AIFDIRCFG_AD1_S 4 199 #define I2S_AIFDIRCFG_AD1_OUT 0x00000020 200 #define I2S_AIFDIRCFG_AD1_IN 0x00000010 201 #define I2S_AIFDIRCFG_AD1_DIS 0x00000000 202 203 // Field: [1:0] AD0 204 // 205 // Configures the AD0 audio data pin usage: 206 // 207 // 0x3: Reserved 208 // ENUMs: 209 // OUT Output mode 210 // IN Input mode 211 // DIS Not in use (disabled) 212 #define I2S_AIFDIRCFG_AD0_W 2 213 #define I2S_AIFDIRCFG_AD0_M 0x00000003 214 #define I2S_AIFDIRCFG_AD0_S 0 215 #define I2S_AIFDIRCFG_AD0_OUT 0x00000002 216 #define I2S_AIFDIRCFG_AD0_IN 0x00000001 217 #define I2S_AIFDIRCFG_AD0_DIS 0x00000000 218 219 //***************************************************************************** 220 // 221 // Register: I2S_O_AIFFMTCFG 222 // 223 //***************************************************************************** 224 // Field: [15:8] DATA_DELAY 225 // 226 // The number of BCLK periods between a WCLK edge and MSB of the first word in 227 // a phase: 228 // 229 // 0x00: LJF and DSP format 230 // 0x01: I2S and DSP format 231 // 0x02: RJF format 232 // ... 233 // 0xFF: RJF format 234 // 235 // Note: When 0, MSB of the next word will be output in the idle period between 236 // LSB of the previous word and the start of the next word. Otherwise logical 0 237 // will be output until the data delay has expired. 238 #define I2S_AIFFMTCFG_DATA_DELAY_W 8 239 #define I2S_AIFFMTCFG_DATA_DELAY_M 0x0000FF00 240 #define I2S_AIFFMTCFG_DATA_DELAY_S 8 241 242 // Field: [7] MEM_LEN_24 243 // 244 // The size of each word stored to or loaded from memory: 245 // ENUMs: 246 // 24BIT 24-bit (one 8 bit and one 16 bit locked access per 247 // sample) 248 // 16BIT 16-bit (one 16 bit access per sample) 249 #define I2S_AIFFMTCFG_MEM_LEN_24 0x00000080 250 #define I2S_AIFFMTCFG_MEM_LEN_24_BITN 7 251 #define I2S_AIFFMTCFG_MEM_LEN_24_M 0x00000080 252 #define I2S_AIFFMTCFG_MEM_LEN_24_S 7 253 #define I2S_AIFFMTCFG_MEM_LEN_24_24BIT 0x00000080 254 #define I2S_AIFFMTCFG_MEM_LEN_24_16BIT 0x00000000 255 256 // Field: [6] SMPL_EDGE 257 // 258 // On the serial audio interface, data (and wclk) is sampled and clocked out on 259 // opposite edges of BCLK. 260 // ENUMs: 261 // POS Data is sampled on the positive edge and clocked 262 // out on the negative edge. 263 // NEG Data is sampled on the negative edge and clocked 264 // out on the positive edge. 265 #define I2S_AIFFMTCFG_SMPL_EDGE 0x00000040 266 #define I2S_AIFFMTCFG_SMPL_EDGE_BITN 6 267 #define I2S_AIFFMTCFG_SMPL_EDGE_M 0x00000040 268 #define I2S_AIFFMTCFG_SMPL_EDGE_S 6 269 #define I2S_AIFFMTCFG_SMPL_EDGE_POS 0x00000040 270 #define I2S_AIFFMTCFG_SMPL_EDGE_NEG 0x00000000 271 272 // Field: [5] DUAL_PHASE 273 // 274 // Selects dual- or single-phase format. 275 // 276 // 0: Single-phase: DSP format 277 // 1: Dual-phase: I2S, LJF and RJF formats 278 #define I2S_AIFFMTCFG_DUAL_PHASE 0x00000020 279 #define I2S_AIFFMTCFG_DUAL_PHASE_BITN 5 280 #define I2S_AIFFMTCFG_DUAL_PHASE_M 0x00000020 281 #define I2S_AIFFMTCFG_DUAL_PHASE_S 5 282 283 // Field: [4:0] WORD_LEN 284 // 285 // Number of bits per word (8-24): 286 // In single-phase format, this is the exact number of bits per word. 287 // In dual-phase format, this is the maximum number of bits per word. 288 // 289 // Values below 8 and above 24 give undefined behavior. Data written to memory 290 // is always aligned to 16 or 24 bits as defined by MEM_LEN_24. Bit widths that 291 // differ from this alignment will either be truncated or zero padded. 292 #define I2S_AIFFMTCFG_WORD_LEN_W 5 293 #define I2S_AIFFMTCFG_WORD_LEN_M 0x0000001F 294 #define I2S_AIFFMTCFG_WORD_LEN_S 0 295 296 //***************************************************************************** 297 // 298 // Register: I2S_O_AIFWMASK0 299 // 300 //***************************************************************************** 301 // Field: [7:0] MASK 302 // 303 // Bit-mask indicating valid channels in a frame on AD0. 304 // 305 // In single-phase mode, each bit represents one channel, starting with LSB for 306 // the first word in the frame. A frame can contain up to 8 channels. Channels 307 // that are not included in the mask will not be sampled and stored in memory, 308 // and clocked out as '0'. 309 // 310 // In dual-phase mode, only the two LSBs are considered. For a stereo 311 // configuration, set both bits. For a mono configuration, set bit 0 only. In 312 // mono mode, only channel 0 will be sampled and stored to memory, and channel 313 // 0 will be repeated when clocked out. 314 // 315 // In mono mode, only channel 0 will be sampled and stored to memory, and 316 // channel 0 will be repeated in the second phase when clocked out. 317 // 318 // If all bits are zero, no input words will be stored to memory, and the 319 // output data lines will be constant '0'. This can be utilized when PWM debug 320 // output is desired without any actively used output pins. 321 #define I2S_AIFWMASK0_MASK_W 8 322 #define I2S_AIFWMASK0_MASK_M 0x000000FF 323 #define I2S_AIFWMASK0_MASK_S 0 324 325 //***************************************************************************** 326 // 327 // Register: I2S_O_AIFWMASK1 328 // 329 //***************************************************************************** 330 // Field: [7:0] MASK 331 // 332 // Bit-mask indicating valid channels in a frame on AD1. 333 // 334 // In single-phase mode, each bit represents one channel, starting with LSB for 335 // the first word in the frame. A frame can contain up to 8 channels. Channels 336 // that are not included in the mask will not be sampled and stored in memory, 337 // and clocked out as '0'. 338 // 339 // In dual-phase mode, only the two LSBs are considered. For a stereo 340 // configuration, set both bits. For a mono configuration, set bit 0 only. In 341 // mono mode, only channel 0 will be sampled and stored to memory, and channel 342 // 0 will be repeated when clocked out. 343 // 344 // In mono mode, only channel 0 will be sampled and stored to memory, and 345 // channel 0 will be repeated in the second phase when clocked out. 346 // 347 // If all bits are zero, no input words will be stored to memory, and the 348 // output data lines will be constant '0'. This can be utilized when PWM debug 349 // output is desired without any actively used output pins. 350 #define I2S_AIFWMASK1_MASK_W 8 351 #define I2S_AIFWMASK1_MASK_M 0x000000FF 352 #define I2S_AIFWMASK1_MASK_S 0 353 354 //***************************************************************************** 355 // 356 // Register: I2S_O_AIFPWMVALUE 357 // 358 //***************************************************************************** 359 // Field: [15:0] PULSE_WIDTH 360 // 361 // The value written to this register determines the width of the active high 362 // PWM pulse (pwm_debug), which starts together with MSB of the first output 363 // word in a DMA buffer: 364 // 365 // 0x0000: Constant low 366 // 0x0001: Width of the pulse (number of BCLK cycles, here 1). 367 // ... 368 // 0xFFFE: Width of the pulse (number of BCLK cycles, here 65534). 369 // 0xFFFF: Constant high 370 #define I2S_AIFPWMVALUE_PULSE_WIDTH_W 16 371 #define I2S_AIFPWMVALUE_PULSE_WIDTH_M 0x0000FFFF 372 #define I2S_AIFPWMVALUE_PULSE_WIDTH_S 0 373 374 //***************************************************************************** 375 // 376 // Register: I2S_O_AIFINPTRNEXT 377 // 378 //***************************************************************************** 379 // Field: [31:0] PTR 380 // 381 // Pointer to the first byte in the next DMA input buffer. 382 // 383 // The read value equals the last written value until the currently used DMA 384 // input buffer is completed, and then becomes null when the last written value 385 // is transferred to the DMA controller to start on the next buffer. This event 386 // is signalized by IRQFLAGS.AIF_DMA_IN. 387 // 388 // At startup, the value must be written once before and once after configuring 389 // the DMA buffer size in AIFDMACFG. 390 // 391 // The next pointer must be written to this register while the DMA function 392 // uses the previously written pointer. If not written in time, 393 // IRQFLAGS.PTR_ERR will be raised and all input pins will be disabled. 394 #define I2S_AIFINPTRNEXT_PTR_W 32 395 #define I2S_AIFINPTRNEXT_PTR_M 0xFFFFFFFF 396 #define I2S_AIFINPTRNEXT_PTR_S 0 397 398 //***************************************************************************** 399 // 400 // Register: I2S_O_AIFINPTR 401 // 402 //***************************************************************************** 403 // Field: [31:0] PTR 404 // 405 // Value of the DMA input buffer pointer currently used by the DMA controller. 406 // Incremented by 1 (byte) or 2 (word) for each AHB access. 407 #define I2S_AIFINPTR_PTR_W 32 408 #define I2S_AIFINPTR_PTR_M 0xFFFFFFFF 409 #define I2S_AIFINPTR_PTR_S 0 410 411 //***************************************************************************** 412 // 413 // Register: I2S_O_AIFOUTPTRNEXT 414 // 415 //***************************************************************************** 416 // Field: [31:0] PTR 417 // 418 // Pointer to the first byte in the next DMA output buffer. 419 // 420 // The read value equals the last written value until the currently used DMA 421 // output buffer is completed, and then becomes null when the last written 422 // value is transferred to the DMA controller to start on the next buffer. This 423 // event is signalized by IRQFLAGS.AIF_DMA_OUT. 424 // 425 // At startup, the value must be written once before and once after configuring 426 // the DMA buffer size in AIFDMACFG. At this time, the first two samples will 427 // be fetched from memory. 428 // 429 // The next pointer must be written to this register while the DMA function 430 // uses the previously written pointer. If not written in time, 431 // IRQFLAGS.PTR_ERR will be raised and all output pins will be disabled. 432 #define I2S_AIFOUTPTRNEXT_PTR_W 32 433 #define I2S_AIFOUTPTRNEXT_PTR_M 0xFFFFFFFF 434 #define I2S_AIFOUTPTRNEXT_PTR_S 0 435 436 //***************************************************************************** 437 // 438 // Register: I2S_O_AIFOUTPTR 439 // 440 //***************************************************************************** 441 // Field: [31:0] PTR 442 // 443 // Value of the DMA output buffer pointer currently used by the DMA controller 444 // Incremented by 1 (byte) or 2 (word) for each AHB access. 445 #define I2S_AIFOUTPTR_PTR_W 32 446 #define I2S_AIFOUTPTR_PTR_M 0xFFFFFFFF 447 #define I2S_AIFOUTPTR_PTR_S 0 448 449 //***************************************************************************** 450 // 451 // Register: I2S_O_STMPCTL 452 // 453 //***************************************************************************** 454 // Field: [2] OUT_RDY 455 // 456 // Low until the output pins are ready to be started by the samplestamp 457 // generator. When started (that is STMPOUTTRIG equals the WCLK counter) the 458 // bit goes back low. 459 #define I2S_STMPCTL_OUT_RDY 0x00000004 460 #define I2S_STMPCTL_OUT_RDY_BITN 2 461 #define I2S_STMPCTL_OUT_RDY_M 0x00000004 462 #define I2S_STMPCTL_OUT_RDY_S 2 463 464 // Field: [1] IN_RDY 465 // 466 // Low until the input pins are ready to be started by the samplestamp 467 // generator. When started (that is STMPINTRIG equals the WCLK counter) the bit 468 // goes back low. 469 #define I2S_STMPCTL_IN_RDY 0x00000002 470 #define I2S_STMPCTL_IN_RDY_BITN 1 471 #define I2S_STMPCTL_IN_RDY_M 0x00000002 472 #define I2S_STMPCTL_IN_RDY_S 1 473 474 // Field: [0] STMP_EN 475 // 476 // Enables the samplestamp generator. The samplestamp generator must only be 477 // enabled after it has been properly configured. 478 // When cleared, all samplestamp generator counters and capture values are 479 // cleared. 480 #define I2S_STMPCTL_STMP_EN 0x00000001 481 #define I2S_STMPCTL_STMP_EN_BITN 0 482 #define I2S_STMPCTL_STMP_EN_M 0x00000001 483 #define I2S_STMPCTL_STMP_EN_S 0 484 485 //***************************************************************************** 486 // 487 // Register: I2S_O_STMPXCNTCAPT0 488 // 489 //***************************************************************************** 490 // Field: [15:0] CAPT_VALUE 491 // 492 // The value of the samplestamp XOSC counter (STMPXCNT.CURR_VALUE) last time an 493 // event was pulsed (event source selected in [EVENT.I2SSTMPSEL0.EV] for 494 // channel 0). This number corresponds to the number of 24 MHz clock cycles 495 // since the last positive edge of the selected WCLK. 496 // The value is cleared when STMPCTL.STMP_EN = 0. 497 // Note: Due to buffering and synchronization, WCLK is delayed by a small 498 // number of BCLK periods and clk periods. 499 // Note: When calculating the fractional part of the sample stamp, STMPXPER may 500 // be less than this bit field. 501 #define I2S_STMPXCNTCAPT0_CAPT_VALUE_W 16 502 #define I2S_STMPXCNTCAPT0_CAPT_VALUE_M 0x0000FFFF 503 #define I2S_STMPXCNTCAPT0_CAPT_VALUE_S 0 504 505 //***************************************************************************** 506 // 507 // Register: I2S_O_STMPXPER 508 // 509 //***************************************************************************** 510 // Field: [15:0] VALUE 511 // 512 // The number of 24 MHz clock cycles in the previous WCLK period (that is - 513 // the next value of the XOSC counter at the positive WCLK edge, had it not 514 // been reset to 0). 515 // The value is cleared when STMPCTL.STMP_EN = 0. 516 #define I2S_STMPXPER_VALUE_W 16 517 #define I2S_STMPXPER_VALUE_M 0x0000FFFF 518 #define I2S_STMPXPER_VALUE_S 0 519 520 //***************************************************************************** 521 // 522 // Register: I2S_O_STMPWCNTCAPT0 523 // 524 //***************************************************************************** 525 // Field: [15:0] CAPT_VALUE 526 // 527 // The value of the samplestamp WCLK counter (STMPWCNT.CURR_VALUE) last time an 528 // event was pulsed (event source selected in EVENT:I2SSTMPSEL0.EV for channel 529 // 0). This number corresponds to the number of positive WCLK edges since the 530 // samplestamp generator was enabled (not taking modification through 531 // STMPWADD/STMPWSET into account). 532 // The value is cleared when STMPCTL.STMP_EN = 0. 533 #define I2S_STMPWCNTCAPT0_CAPT_VALUE_W 16 534 #define I2S_STMPWCNTCAPT0_CAPT_VALUE_M 0x0000FFFF 535 #define I2S_STMPWCNTCAPT0_CAPT_VALUE_S 0 536 537 //***************************************************************************** 538 // 539 // Register: I2S_O_STMPWPER 540 // 541 //***************************************************************************** 542 // Field: [15:0] VALUE 543 // 544 // Used to define when STMPWCNT is to be reset so number of WCLK edges are 545 // found for the size of the sample buffer. This is thus a modulo value for the 546 // WCLK counter. This number must correspond to the size of the sample buffer 547 // used by the system (that is the index of the last sample plus 1). 548 #define I2S_STMPWPER_VALUE_W 16 549 #define I2S_STMPWPER_VALUE_M 0x0000FFFF 550 #define I2S_STMPWPER_VALUE_S 0 551 552 //***************************************************************************** 553 // 554 // Register: I2S_O_STMPINTRIG 555 // 556 //***************************************************************************** 557 // Field: [15:0] IN_START_WCNT 558 // 559 // Compare value used to start the incoming audio streams. 560 // This bit field shall equal the WCLK counter value during the WCLK period in 561 // which the first input word(s) are sampled and stored to memory (that is the 562 // sample at the start of the very first DMA input buffer). 563 // 564 // The value of this register takes effect when the following conditions are 565 // met: 566 // - One or more pins are configured as inputs in AIFDIRCFG. 567 // - AIFDMACFG has been configured for the correct buffer size, and at least 32 568 // BCLK cycle ticks have happened. 569 // 570 // Note: To avoid false triggers, this bit field should be set higher than 571 // STMPWPER.VALUE. 572 #define I2S_STMPINTRIG_IN_START_WCNT_W 16 573 #define I2S_STMPINTRIG_IN_START_WCNT_M 0x0000FFFF 574 #define I2S_STMPINTRIG_IN_START_WCNT_S 0 575 576 //***************************************************************************** 577 // 578 // Register: I2S_O_STMPOUTTRIG 579 // 580 //***************************************************************************** 581 // Field: [15:0] OUT_START_WCNT 582 // 583 // Compare value used to start the outgoing audio streams. 584 // 585 // This bit field must equal the WCLK counter value during the WCLK period in 586 // which the first output word(s) read from memory are clocked out (that is the 587 // sample at the start of the very first DMA output buffer). 588 // 589 // The value of this register takes effect when the following conditions are 590 // met: 591 // - One or more pins are configured as outputs in AIFDIRCFG. 592 // - AIFDMACFG has been configured for the correct buffer size, and 32 BCLK 593 // cycle ticks have happened. 594 // - 2 samples have been preloaded from memory (examine the AIFOUTPTR register 595 // if necessary). 596 // Note: The memory read access is only performed when required, that is 597 // channels 0/1 must be selected in AIFWMASK0/AIFWMASK1. 598 // 599 // Note: To avoid false triggers, this bit field should be set higher than 600 // STMPWPER.VALUE. 601 #define I2S_STMPOUTTRIG_OUT_START_WCNT_W 16 602 #define I2S_STMPOUTTRIG_OUT_START_WCNT_M 0x0000FFFF 603 #define I2S_STMPOUTTRIG_OUT_START_WCNT_S 0 604 605 //***************************************************************************** 606 // 607 // Register: I2S_O_STMPWSET 608 // 609 //***************************************************************************** 610 // Field: [15:0] VALUE 611 // 612 // WCLK counter modification: Sets the running WCLK counter equal to the 613 // written value. 614 #define I2S_STMPWSET_VALUE_W 16 615 #define I2S_STMPWSET_VALUE_M 0x0000FFFF 616 #define I2S_STMPWSET_VALUE_S 0 617 618 //***************************************************************************** 619 // 620 // Register: I2S_O_STMPWADD 621 // 622 //***************************************************************************** 623 // Field: [15:0] VALUE_INC 624 // 625 // WCLK counter modification: Adds the written value to the running WCLK 626 // counter. If a positive edge of WCLK occurs at the same time as the 627 // operation, this will be taken into account. 628 // To add a negative value, write "STMPWPER.VALUE - value". 629 // 630 #define I2S_STMPWADD_VALUE_INC_W 16 631 #define I2S_STMPWADD_VALUE_INC_M 0x0000FFFF 632 #define I2S_STMPWADD_VALUE_INC_S 0 633 634 //***************************************************************************** 635 // 636 // Register: I2S_O_STMPXPERMIN 637 // 638 //***************************************************************************** 639 // Field: [15:0] VALUE 640 // 641 // Each time STMPXPER is updated, the value is also loaded into this register, 642 // provided that the value is smaller than the current value in this register. 643 // When written, the register is reset to 0xFFFF (65535), regardless of the 644 // value written. 645 // The minimum value can be used to detect extra WCLK pulses (this registers 646 // value will be significantly smaller than STMPXPER.VALUE). 647 #define I2S_STMPXPERMIN_VALUE_W 16 648 #define I2S_STMPXPERMIN_VALUE_M 0x0000FFFF 649 #define I2S_STMPXPERMIN_VALUE_S 0 650 651 //***************************************************************************** 652 // 653 // Register: I2S_O_STMPWCNT 654 // 655 //***************************************************************************** 656 // Field: [15:0] CURR_VALUE 657 // 658 // Current value of the WCLK counter 659 #define I2S_STMPWCNT_CURR_VALUE_W 16 660 #define I2S_STMPWCNT_CURR_VALUE_M 0x0000FFFF 661 #define I2S_STMPWCNT_CURR_VALUE_S 0 662 663 //***************************************************************************** 664 // 665 // Register: I2S_O_STMPXCNT 666 // 667 //***************************************************************************** 668 // Field: [15:0] CURR_VALUE 669 // 670 // Current value of the XOSC counter, latched when reading STMPWCNT. 671 #define I2S_STMPXCNT_CURR_VALUE_W 16 672 #define I2S_STMPXCNT_CURR_VALUE_M 0x0000FFFF 673 #define I2S_STMPXCNT_CURR_VALUE_S 0 674 675 //***************************************************************************** 676 // 677 // Register: I2S_O_STMPXCNTCAPT1 678 // 679 //***************************************************************************** 680 // Field: [15:0] CAPT_VALUE 681 // 682 // Internal. Only to be used through TI provided API. 683 #define I2S_STMPXCNTCAPT1_CAPT_VALUE_W 16 684 #define I2S_STMPXCNTCAPT1_CAPT_VALUE_M 0x0000FFFF 685 #define I2S_STMPXCNTCAPT1_CAPT_VALUE_S 0 686 687 //***************************************************************************** 688 // 689 // Register: I2S_O_STMPWCNTCAPT1 690 // 691 //***************************************************************************** 692 // Field: [15:0] CAPT_VALUE 693 // 694 // Internal. Only to be used through TI provided API. 695 #define I2S_STMPWCNTCAPT1_CAPT_VALUE_W 16 696 #define I2S_STMPWCNTCAPT1_CAPT_VALUE_M 0x0000FFFF 697 #define I2S_STMPWCNTCAPT1_CAPT_VALUE_S 0 698 699 //***************************************************************************** 700 // 701 // Register: I2S_O_IRQMASK 702 // 703 //***************************************************************************** 704 // Field: [5] AIF_DMA_IN 705 // 706 // IRQFLAGS.AIF_DMA_IN interrupt mask 707 // 708 // 0: Disable 709 // 1: Enable 710 #define I2S_IRQMASK_AIF_DMA_IN 0x00000020 711 #define I2S_IRQMASK_AIF_DMA_IN_BITN 5 712 #define I2S_IRQMASK_AIF_DMA_IN_M 0x00000020 713 #define I2S_IRQMASK_AIF_DMA_IN_S 5 714 715 // Field: [4] AIF_DMA_OUT 716 // 717 // IRQFLAGS.AIF_DMA_OUT interrupt mask 718 // 719 // 0: Disable 720 // 1: Enable 721 #define I2S_IRQMASK_AIF_DMA_OUT 0x00000010 722 #define I2S_IRQMASK_AIF_DMA_OUT_BITN 4 723 #define I2S_IRQMASK_AIF_DMA_OUT_M 0x00000010 724 #define I2S_IRQMASK_AIF_DMA_OUT_S 4 725 726 // Field: [3] WCLK_TIMEOUT 727 // 728 // IRQFLAGS.WCLK_TIMEOUT interrupt mask 729 // 730 // 0: Disable 731 // 1: Enable 732 #define I2S_IRQMASK_WCLK_TIMEOUT 0x00000008 733 #define I2S_IRQMASK_WCLK_TIMEOUT_BITN 3 734 #define I2S_IRQMASK_WCLK_TIMEOUT_M 0x00000008 735 #define I2S_IRQMASK_WCLK_TIMEOUT_S 3 736 737 // Field: [2] BUS_ERR 738 // 739 // IRQFLAGS.BUS_ERR interrupt mask 740 // 741 // 0: Disable 742 // 1: Enable 743 #define I2S_IRQMASK_BUS_ERR 0x00000004 744 #define I2S_IRQMASK_BUS_ERR_BITN 2 745 #define I2S_IRQMASK_BUS_ERR_M 0x00000004 746 #define I2S_IRQMASK_BUS_ERR_S 2 747 748 // Field: [1] WCLK_ERR 749 // 750 // IRQFLAGS.WCLK_ERR interrupt mask 751 // 752 // 0: Disable 753 // 1: Enable 754 #define I2S_IRQMASK_WCLK_ERR 0x00000002 755 #define I2S_IRQMASK_WCLK_ERR_BITN 1 756 #define I2S_IRQMASK_WCLK_ERR_M 0x00000002 757 #define I2S_IRQMASK_WCLK_ERR_S 1 758 759 // Field: [0] PTR_ERR 760 // 761 // IRQFLAGS.PTR_ERR interrupt mask. 762 // 763 // 0: Disable 764 // 1: Enable 765 #define I2S_IRQMASK_PTR_ERR 0x00000001 766 #define I2S_IRQMASK_PTR_ERR_BITN 0 767 #define I2S_IRQMASK_PTR_ERR_M 0x00000001 768 #define I2S_IRQMASK_PTR_ERR_S 0 769 770 //***************************************************************************** 771 // 772 // Register: I2S_O_IRQFLAGS 773 // 774 //***************************************************************************** 775 // Field: [5] AIF_DMA_IN 776 // 777 // Set when condition for this bit field event occurs (auto cleared when input 778 // pointer is updated - AIFINPTRNEXT), see description of AIFINPTRNEXT register 779 // for details. 780 #define I2S_IRQFLAGS_AIF_DMA_IN 0x00000020 781 #define I2S_IRQFLAGS_AIF_DMA_IN_BITN 5 782 #define I2S_IRQFLAGS_AIF_DMA_IN_M 0x00000020 783 #define I2S_IRQFLAGS_AIF_DMA_IN_S 5 784 785 // Field: [4] AIF_DMA_OUT 786 // 787 // Set when condition for this bit field event occurs (auto cleared when output 788 // pointer is updated - AIFOUTPTRNEXT), see description of AIFOUTPTRNEXT 789 // register for details 790 #define I2S_IRQFLAGS_AIF_DMA_OUT 0x00000010 791 #define I2S_IRQFLAGS_AIF_DMA_OUT_BITN 4 792 #define I2S_IRQFLAGS_AIF_DMA_OUT_M 0x00000010 793 #define I2S_IRQFLAGS_AIF_DMA_OUT_S 4 794 795 // Field: [3] WCLK_TIMEOUT 796 // 797 // Set when the sample stamp generator does not detect a positive WCLK edge for 798 // 65535 clk periods. This signalizes that the internal or external BCLK and 799 // WCLK generator source has been disabled. 800 // 801 // The bit is sticky and may only be cleared by software (by writing '1' to 802 // IRQCLR.WCLK_TIMEOUT). 803 #define I2S_IRQFLAGS_WCLK_TIMEOUT 0x00000008 804 #define I2S_IRQFLAGS_WCLK_TIMEOUT_BITN 3 805 #define I2S_IRQFLAGS_WCLK_TIMEOUT_M 0x00000008 806 #define I2S_IRQFLAGS_WCLK_TIMEOUT_S 3 807 808 // Field: [2] BUS_ERR 809 // 810 // Set when a DMA operation is not completed in time (that is audio output 811 // buffer underflow, or audio input buffer overflow). 812 // This error requires a complete restart since word synchronization has been 813 // lost. The bit is sticky and may only be cleared by software (by writing '1' 814 // to IRQCLR.BUS_ERR). 815 // 816 // Note that DMA initiated transactions to illegal addresses will not trigger 817 // an interrupt. The response to such transactions is undefined. 818 #define I2S_IRQFLAGS_BUS_ERR 0x00000004 819 #define I2S_IRQFLAGS_BUS_ERR_BITN 2 820 #define I2S_IRQFLAGS_BUS_ERR_M 0x00000004 821 #define I2S_IRQFLAGS_BUS_ERR_S 2 822 823 // Field: [1] WCLK_ERR 824 // 825 // Set when: 826 // - An unexpected WCLK edge occurs during the data delay period of a phase. 827 // Note unexpected WCLK edges during the word and idle periods of the phase are 828 // not detected. 829 // - In dual-phase mode, when two WCLK edges are less than 4 BCLK cycles 830 // apart. 831 // - In single-phase mode, when a WCLK pulse occurs before the last channel. 832 // This error requires a complete restart since word synchronization has been 833 // lost. The bit is sticky and may only be cleared by software (by writing '1' 834 // to IRQCLR.WCLK_ERR). 835 #define I2S_IRQFLAGS_WCLK_ERR 0x00000002 836 #define I2S_IRQFLAGS_WCLK_ERR_BITN 1 837 #define I2S_IRQFLAGS_WCLK_ERR_M 0x00000002 838 #define I2S_IRQFLAGS_WCLK_ERR_S 1 839 840 // Field: [0] PTR_ERR 841 // 842 // Set when AIFINPTRNEXT or AIFOUTPTRNEXT has not been loaded with the next 843 // block address in time. 844 // This error requires a complete restart since word synchronization has been 845 // lost. The bit is sticky and may only be cleared by software (by writing '1' 846 // to IRQCLR.PTR_ERR). 847 #define I2S_IRQFLAGS_PTR_ERR 0x00000001 848 #define I2S_IRQFLAGS_PTR_ERR_BITN 0 849 #define I2S_IRQFLAGS_PTR_ERR_M 0x00000001 850 #define I2S_IRQFLAGS_PTR_ERR_S 0 851 852 //***************************************************************************** 853 // 854 // Register: I2S_O_IRQSET 855 // 856 //***************************************************************************** 857 // Field: [5] AIF_DMA_IN 858 // 859 // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_IN (unless a auto clear criteria 860 // was given at the same time, in which the set will be ignored) 861 #define I2S_IRQSET_AIF_DMA_IN 0x00000020 862 #define I2S_IRQSET_AIF_DMA_IN_BITN 5 863 #define I2S_IRQSET_AIF_DMA_IN_M 0x00000020 864 #define I2S_IRQSET_AIF_DMA_IN_S 5 865 866 // Field: [4] AIF_DMA_OUT 867 // 868 // 1: Sets the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a auto clear criteria 869 // was given at the same time, in which the set will be ignored) 870 #define I2S_IRQSET_AIF_DMA_OUT 0x00000010 871 #define I2S_IRQSET_AIF_DMA_OUT_BITN 4 872 #define I2S_IRQSET_AIF_DMA_OUT_M 0x00000010 873 #define I2S_IRQSET_AIF_DMA_OUT_S 4 874 875 // Field: [3] WCLK_TIMEOUT 876 // 877 // 1: Sets the interrupt of IRQFLAGS.WCLK_TIMEOUT 878 #define I2S_IRQSET_WCLK_TIMEOUT 0x00000008 879 #define I2S_IRQSET_WCLK_TIMEOUT_BITN 3 880 #define I2S_IRQSET_WCLK_TIMEOUT_M 0x00000008 881 #define I2S_IRQSET_WCLK_TIMEOUT_S 3 882 883 // Field: [2] BUS_ERR 884 // 885 // 1: Sets the interrupt of IRQFLAGS.BUS_ERR 886 #define I2S_IRQSET_BUS_ERR 0x00000004 887 #define I2S_IRQSET_BUS_ERR_BITN 2 888 #define I2S_IRQSET_BUS_ERR_M 0x00000004 889 #define I2S_IRQSET_BUS_ERR_S 2 890 891 // Field: [1] WCLK_ERR 892 // 893 // 1: Sets the interrupt of IRQFLAGS.WCLK_ERR 894 #define I2S_IRQSET_WCLK_ERR 0x00000002 895 #define I2S_IRQSET_WCLK_ERR_BITN 1 896 #define I2S_IRQSET_WCLK_ERR_M 0x00000002 897 #define I2S_IRQSET_WCLK_ERR_S 1 898 899 // Field: [0] PTR_ERR 900 // 901 // 1: Sets the interrupt of IRQFLAGS.PTR_ERR 902 #define I2S_IRQSET_PTR_ERR 0x00000001 903 #define I2S_IRQSET_PTR_ERR_BITN 0 904 #define I2S_IRQSET_PTR_ERR_M 0x00000001 905 #define I2S_IRQSET_PTR_ERR_S 0 906 907 //***************************************************************************** 908 // 909 // Register: I2S_O_IRQCLR 910 // 911 //***************************************************************************** 912 // Field: [5] AIF_DMA_IN 913 // 914 // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_IN (unless a set criteria was 915 // given at the same time in which the clear will be ignored) 916 #define I2S_IRQCLR_AIF_DMA_IN 0x00000020 917 #define I2S_IRQCLR_AIF_DMA_IN_BITN 5 918 #define I2S_IRQCLR_AIF_DMA_IN_M 0x00000020 919 #define I2S_IRQCLR_AIF_DMA_IN_S 5 920 921 // Field: [4] AIF_DMA_OUT 922 // 923 // 1: Clears the interrupt of IRQFLAGS.AIF_DMA_OUT (unless a set criteria was 924 // given at the same time in which the clear will be ignored) 925 #define I2S_IRQCLR_AIF_DMA_OUT 0x00000010 926 #define I2S_IRQCLR_AIF_DMA_OUT_BITN 4 927 #define I2S_IRQCLR_AIF_DMA_OUT_M 0x00000010 928 #define I2S_IRQCLR_AIF_DMA_OUT_S 4 929 930 // Field: [3] WCLK_TIMEOUT 931 // 932 // 1: Clears the interrupt of IRQFLAGS.WCLK_TIMEOUT (unless a set criteria was 933 // given at the same time in which the clear will be ignored) 934 #define I2S_IRQCLR_WCLK_TIMEOUT 0x00000008 935 #define I2S_IRQCLR_WCLK_TIMEOUT_BITN 3 936 #define I2S_IRQCLR_WCLK_TIMEOUT_M 0x00000008 937 #define I2S_IRQCLR_WCLK_TIMEOUT_S 3 938 939 // Field: [2] BUS_ERR 940 // 941 // 1: Clears the interrupt of IRQFLAGS.BUS_ERR (unless a set criteria was given 942 // at the same time in which the clear will be ignored) 943 #define I2S_IRQCLR_BUS_ERR 0x00000004 944 #define I2S_IRQCLR_BUS_ERR_BITN 2 945 #define I2S_IRQCLR_BUS_ERR_M 0x00000004 946 #define I2S_IRQCLR_BUS_ERR_S 2 947 948 // Field: [1] WCLK_ERR 949 // 950 // 1: Clears the interrupt of IRQFLAGS.WCLK_ERR (unless a set criteria was 951 // given at the same time in which the clear will be ignored) 952 #define I2S_IRQCLR_WCLK_ERR 0x00000002 953 #define I2S_IRQCLR_WCLK_ERR_BITN 1 954 #define I2S_IRQCLR_WCLK_ERR_M 0x00000002 955 #define I2S_IRQCLR_WCLK_ERR_S 1 956 957 // Field: [0] PTR_ERR 958 // 959 // 1: Clears the interrupt of IRQFLAGS.PTR_ERR (unless a set criteria was given 960 // at the same time in which the clear will be ignored) 961 #define I2S_IRQCLR_PTR_ERR 0x00000001 962 #define I2S_IRQCLR_PTR_ERR_BITN 0 963 #define I2S_IRQCLR_PTR_ERR_M 0x00000001 964 #define I2S_IRQCLR_PTR_ERR_S 0 965 966 967 #endif // __I2S__ 968
