1 /****************************************************************************** 2 * Filename: hw_ddi.h 3 * 4 * Copyright (c) 2015 - 2022, Texas Instruments Incorporated 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1) Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2) Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 18 * be used to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 ******************************************************************************/ 34 35 #ifndef __HW_DDI_H__ 36 #define __HW_DDI_H__ 37 38 //***************************************************************************** 39 // 40 // This file contains macros for controlling the DDI master and 41 // accessing DDI Slave registers via the DDI Master. 42 // There are 3 categories of macros in this file: 43 // - macros that provide an offset to a register 44 // located within the DDI Master itself. 45 // - macros that define bits or bitfields 46 // within the DDI Master Registers. 47 // - macros that provide an "instruction offset" 48 // that are used when accessing a DDI Slave. 49 // 50 // The macros that that provide DDI Master register offsets and 51 // define bits and bitfields for those registers are the typical 52 // macros that appear in most hw_<module>.h header files. In 53 // the following example DDI_O_CFG is a macro for a 54 // register offset and DDI_CFG_WAITFORACK is a macro for 55 // a bit in that register. This example code will set the WAITFORACK 56 // bit in register DDI_O_CFG of the DDI Master. (Note: this 57 // access the Master not the Slave). 58 // 59 // HWREG(AUX_OSCDDI_BASE + DDI_O_CFG) |= DDI_CFG_WAITFORACK; 60 // 61 // 62 // The "instruction offset" macros are used to pass an instruction to 63 // the DDI Master when accessing DDI slave registers. These macros are 64 // only used when accessing DDI Slave Registers. (Remember DDI 65 // Master Registers are accessed normally). 66 // 67 // The instructions supported when accessing a DDI Slave Regsiter follow: 68 // - Direct Access to a DDI Slave register. I.e. read or 69 // write the register. 70 // - Set the specified bits in a DDI Slave register. 71 // - Clear the specified bits in a DDI Slave register. 72 // - Mask write of 4 bits to the a DDI Slave register. 73 // - Mask write of 8 bits to the a DDI Slave register. 74 // - Mask write of 16 bits to the a DDI Slave register. 75 // 76 // Note: only the "Direct Access" offset should be used when reading 77 // a DDI Slave register. Only 8- and 16-bit reads are supported. 78 // 79 // The generic format of using this marcos for a read follows: 80 // // read low 16-bits in DDI_SLAVE_OFF 81 // myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR); 82 // 83 // // read high 16-bits in DDI_SLAVE_OFF 84 // // add 2 for data[31:16] 85 // myushortvar = HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_DIR); 86 87 // // read data[31:24] byte in DDI_SLAVE_OFF 88 // // add 3 for data[31:24] 89 // myuchar = HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 3 + DDI_O_DIR); 90 // 91 // Notes: In the above example: 92 // - DDI_MASTER_BASE is the base address of the DDI Master defined 93 // in the hw_memmap.h header file. 94 // - DDI_SLAVE_OFF is the DDI Slave offset defined in the 95 // hw_<ddi_slave>.h header file (e.g. hw_osc_top.h for the oscsc 96 // oscillator modules. 97 // - DDI_O_DIR is the "instruction offset" macro defined in this 98 // file that specifies the Direct Access instruction. 99 // 100 // Writes can use any of the "instruction macros". 101 // The following examples do a "direct write" to DDI Slave register 102 // DDI_SLAVE_OFF using different size operands: 103 // 104 // // ---------- DIRECT WRITES ---------- 105 // // Write 32-bits aligned 106 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x12345678; 107 108 // // Write 16-bits aligned to high 16-bits then low 16-bits 109 // // Add 2 to get to high 16-bits. 110 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0xabcd; 111 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0xef01; 112 // 113 // // Write each byte at DDI_SLAVE_OFF, one at a time. 114 // // Add 1,2,or 3 to get to bytes 1,2, or 3. 115 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR) = 0x33; 116 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 1) = 0x44; 117 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 2) = 0x55; 118 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_DIR + 3) = 0x66; 119 // 120 // // ---------- SET/CLR ---------- 121 // The set and clear functions behave similarly to eachother. Each 122 // can be performed on an 8-, 16-, or 32-bit operand. 123 // Examples follow: 124 // // Set all odd bits in a 32-bit words 125 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_SET) = 0xaaaaaaaa; 126 // 127 // // Clear all bits in byte 2 (data[23:16]) using 32-bit operand 128 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_CLR) = 0x00ff0000; 129 // 130 // // Set even bits in byte 2 (data[23:16]) using 8-bit operand 131 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + 2 + DDI_O_CLR) = 0x55; 132 // 133 // // ---------- MASKED WRITES ---------- 134 // The mask writes are a bit different. They operate on nibbles, 135 // bytes, and 16-bit elements. Two operands are required; a 'mask' 136 // and 'data'; The operands are concatenated and written to the master. 137 // e.g. the mask and data are combined as follows for a 16 bit masked 138 // write: 139 // (mask << 16) | data; 140 // Examples follow: 141 // 142 // // Write 5555 to low 16-bits of DDI_SLAVE_OFF register 143 // // a long write is needed (32-bits). 144 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xffff5555; 145 146 // // Write 1AA to data bits 24:16 in high 16-bits of DDI_SLAVE_OFF register 147 // // Note add 4 for high 16-bits at DDI_SLAVE_OFF; mask is 1ff! 148 // HWREG(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 4) = 0x01ff01aa; 149 // 150 // // Do an 8 bit masked write of 00 to low byte of register (data[7:0]). 151 // // a short write is needed (16-bits). 152 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xff00; 153 // 154 // // Do an 8 bit masked write of 11 to byte 1 of register (data[15:8]). 155 // // add 2 to get to byte 1. 156 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 2) = 0xff11; 157 // 158 // // Do an 8 bit masked write of 33 to high byte of register (data[31:24]). 159 // // add 6 to get to byte 3. 160 // HWREGH(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 6) = 0xff33; 161 // 162 // // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). 163 // // Byte write is needed. 164 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B) = 0xf7; 165 // 166 // // Do an 4 bit masked write of 4 to data[7:4]). 167 // // Add 1 for next nibble 168 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + DDI_O_MASK16B + 1) = 0xf4; 169 // 170 //***************************************************************************** 171 172 //***************************************************************************** 173 // 174 // The following are defines for the DDI master instruction offsets. 175 // 176 //***************************************************************************** 177 #define DDI_O_DIR 0x00000000 // Offset for the direct access instruction 178 #define DDI_O_SET 0x00000080 // Offset for 'Set' instruction. 179 #define DDI_O_CLR 0x00000100 // Offset for 'Clear' instruction. 180 #define DDI_O_MASK4B 0x00000200 // Offset for 4-bit masked access. 181 // Data bit[n] is written if mask bit[n] is set ('1'). 182 // Bits 7:4 are mask. Bits 3:0 are data. 183 // Requires 'byte' write. 184 #define DDI_O_MASK8B 0x00000300 // Offset for 8-bit masked access. 185 // Data bit[n] is written if mask bit[n] is set ('1'). 186 // Bits 15:8 are mask. Bits 7:0 are data. 187 // Requires 'short' write. 188 #define DDI_O_MASK16B 0x00000400 // Offset for 16-bit masked access. 189 // Data bit[n] is written if mask bit[n] is set ('1'). 190 // Bits 31:16 are mask. Bits 15:0 are data. 191 // Requires 'long' write. 192 193 194 195 #endif // __HW_DDI_H__ 196
