1 /****************************************************************************** 2 * Filename: hw_aux_spim_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_SPIM_H__ 38 #define __HW_AUX_SPIM_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_SPIM component 44 // 45 //***************************************************************************** 46 // SPI Master Configuration 47 #define AUX_SPIM_O_SPIMCFG 0x00000000 48 49 // MISO Configuration 50 #define AUX_SPIM_O_MISOCFG 0x00000004 51 52 // MOSI Control 53 #define AUX_SPIM_O_MOSICTL 0x00000008 54 55 // Transmit 8 Bit 56 #define AUX_SPIM_O_TX8 0x0000000C 57 58 // Transmit 16 Bit 59 #define AUX_SPIM_O_TX16 0x00000010 60 61 // Receive 8 Bit 62 #define AUX_SPIM_O_RX8 0x00000014 63 64 // Receive 16 Bit 65 #define AUX_SPIM_O_RX16 0x00000018 66 67 // SCLK Idle 68 #define AUX_SPIM_O_SCLKIDLE 0x0000001C 69 70 // Data Idle 71 #define AUX_SPIM_O_DATAIDLE 0x00000020 72 73 //***************************************************************************** 74 // 75 // Register: AUX_SPIM_O_SPIMCFG 76 // 77 //***************************************************************************** 78 // Field: [7:2] DIV 79 // 80 // SCLK divider. 81 // 82 // Peripheral clock frequency division gives the SCLK clock frequency. The 83 // division factor equals (2 * (DIV+1)): 84 // 85 // 0x00: Divide by 2. 86 // 0x01: Divide by 4. 87 // 0x02: Divide by 6. 88 // ... 89 // 0x3F: Divide by 128. 90 #define AUX_SPIM_SPIMCFG_DIV_W 6 91 #define AUX_SPIM_SPIMCFG_DIV_M 0x000000FC 92 #define AUX_SPIM_SPIMCFG_DIV_S 2 93 94 // Field: [1] PHA 95 // 96 // Phase of the MOSI and MISO data signals. 97 // 98 // 0: Sample MISO at leading (odd) edges and shift MOSI at trailing (even) 99 // edges of SCLK. 100 // 1: Sample MISO at trailing (even) edges and shift MOSI at leading (odd) 101 // edges of SCLK. 102 #define AUX_SPIM_SPIMCFG_PHA 0x00000002 103 #define AUX_SPIM_SPIMCFG_PHA_BITN 1 104 #define AUX_SPIM_SPIMCFG_PHA_M 0x00000002 105 #define AUX_SPIM_SPIMCFG_PHA_S 1 106 107 // Field: [0] POL 108 // 109 // Polarity of the SCLK signal. 110 // 111 // 0: SCLK is low when idle, first clock edge rises. 112 // 1: SCLK is high when idle, first clock edge falls. 113 #define AUX_SPIM_SPIMCFG_POL 0x00000001 114 #define AUX_SPIM_SPIMCFG_POL_BITN 0 115 #define AUX_SPIM_SPIMCFG_POL_M 0x00000001 116 #define AUX_SPIM_SPIMCFG_POL_S 0 117 118 //***************************************************************************** 119 // 120 // Register: AUX_SPIM_O_MISOCFG 121 // 122 //***************************************************************************** 123 // Field: [4:0] AUXIO 124 // 125 // AUXIO to MISO mux. 126 // 127 // Select the AUXIO pin that connects to MISO. 128 #define AUX_SPIM_MISOCFG_AUXIO_W 5 129 #define AUX_SPIM_MISOCFG_AUXIO_M 0x0000001F 130 #define AUX_SPIM_MISOCFG_AUXIO_S 0 131 132 //***************************************************************************** 133 // 134 // Register: AUX_SPIM_O_MOSICTL 135 // 136 //***************************************************************************** 137 // Field: [0] VALUE 138 // 139 // MOSI level control. 140 // 141 // 0: Set MOSI low. 142 // 1: Set MOSI high. 143 #define AUX_SPIM_MOSICTL_VALUE 0x00000001 144 #define AUX_SPIM_MOSICTL_VALUE_BITN 0 145 #define AUX_SPIM_MOSICTL_VALUE_M 0x00000001 146 #define AUX_SPIM_MOSICTL_VALUE_S 0 147 148 //***************************************************************************** 149 // 150 // Register: AUX_SPIM_O_TX8 151 // 152 //***************************************************************************** 153 // Field: [7:0] DATA 154 // 155 // 8 bit data transfer. 156 // 157 // Write DATA to start transfer, MSB first. When transfer completes, MOSI stays 158 // at the value of LSB. 159 #define AUX_SPIM_TX8_DATA_W 8 160 #define AUX_SPIM_TX8_DATA_M 0x000000FF 161 #define AUX_SPIM_TX8_DATA_S 0 162 163 //***************************************************************************** 164 // 165 // Register: AUX_SPIM_O_TX16 166 // 167 //***************************************************************************** 168 // Field: [15:0] DATA 169 // 170 // 16 bit data transfer. 171 // 172 // Write DATA to start transfer, MSB first. When transfer completes, MOSI stays 173 // at the value of LSB. 174 #define AUX_SPIM_TX16_DATA_W 16 175 #define AUX_SPIM_TX16_DATA_M 0x0000FFFF 176 #define AUX_SPIM_TX16_DATA_S 0 177 178 //***************************************************************************** 179 // 180 // Register: AUX_SPIM_O_RX8 181 // 182 //***************************************************************************** 183 // Field: [7:0] DATA 184 // 185 // Latest 8 bits received on MISO. 186 #define AUX_SPIM_RX8_DATA_W 8 187 #define AUX_SPIM_RX8_DATA_M 0x000000FF 188 #define AUX_SPIM_RX8_DATA_S 0 189 190 //***************************************************************************** 191 // 192 // Register: AUX_SPIM_O_RX16 193 // 194 //***************************************************************************** 195 // Field: [15:0] DATA 196 // 197 // Latest 16 bits received on MISO. 198 #define AUX_SPIM_RX16_DATA_W 16 199 #define AUX_SPIM_RX16_DATA_M 0x0000FFFF 200 #define AUX_SPIM_RX16_DATA_S 0 201 202 //***************************************************************************** 203 // 204 // Register: AUX_SPIM_O_SCLKIDLE 205 // 206 //***************************************************************************** 207 // Field: [0] STAT 208 // 209 // Wait for SCLK idle. 210 // 211 // Read operation stalls until SCLK is idle with no remaining clock edges. Read 212 // then returns 1. 213 // 214 // AUX_SCE can use this to control CS deassertion. 215 #define AUX_SPIM_SCLKIDLE_STAT 0x00000001 216 #define AUX_SPIM_SCLKIDLE_STAT_BITN 0 217 #define AUX_SPIM_SCLKIDLE_STAT_M 0x00000001 218 #define AUX_SPIM_SCLKIDLE_STAT_S 0 219 220 //***************************************************************************** 221 // 222 // Register: AUX_SPIM_O_DATAIDLE 223 // 224 //***************************************************************************** 225 // Field: [0] STAT 226 // 227 // Wait for data idle. 228 // 229 // Read operation stalls until the SCLK period associated with LSB transmission 230 // completes. Read then returns 1. 231 // 232 // AUX_SCE can use this to control CS deassertion. 233 #define AUX_SPIM_DATAIDLE_STAT 0x00000001 234 #define AUX_SPIM_DATAIDLE_STAT_BITN 0 235 #define AUX_SPIM_DATAIDLE_STAT_M 0x00000001 236 #define AUX_SPIM_DATAIDLE_STAT_S 0 237 238 239 #endif // __AUX_SPIM__ 240
