1 /****************************************************************************** 2 * Filename: hw_aux_mac_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_MAC_H__ 38 #define __HW_AUX_MAC_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_MAC component 44 // 45 //***************************************************************************** 46 // Signed Operand 0 47 #define AUX_MAC_O_OP0S 0x00000000 48 49 // Unsigned Operand 0 50 #define AUX_MAC_O_OP0U 0x00000004 51 52 // Signed Operand 1 and Multiply 53 #define AUX_MAC_O_OP1SMUL 0x00000008 54 55 // Unsigned Operand 1 and Multiply 56 #define AUX_MAC_O_OP1UMUL 0x0000000C 57 58 // Signed Operand 1 and Multiply-Accumulate 59 #define AUX_MAC_O_OP1SMAC 0x00000010 60 61 // Unsigned Operand 1 and Multiply-Accumulate 62 #define AUX_MAC_O_OP1UMAC 0x00000014 63 64 // Signed Operand 1 and 16-bit Addition 65 #define AUX_MAC_O_OP1SADD16 0x00000018 66 67 // Unsigned Operand 1 and 16-bit Addition 68 #define AUX_MAC_O_OP1UADD16 0x0000001C 69 70 // Signed Operand 1 and 32-bit Addition 71 #define AUX_MAC_O_OP1SADD32 0x00000020 72 73 // Unsigned Operand 1 and 32-bit Addition 74 #define AUX_MAC_O_OP1UADD32 0x00000024 75 76 // Count Leading Zero 77 #define AUX_MAC_O_CLZ 0x00000028 78 79 // Count Leading Sign 80 #define AUX_MAC_O_CLS 0x0000002C 81 82 // Accumulator Shift 83 #define AUX_MAC_O_ACCSHIFT 0x00000030 84 85 // Accumulator Reset 86 #define AUX_MAC_O_ACCRESET 0x00000034 87 88 // Accumulator Bits 15:0 89 #define AUX_MAC_O_ACC15_0 0x00000038 90 91 // Accumulator Bits 16:1 92 #define AUX_MAC_O_ACC16_1 0x0000003C 93 94 // Accumulator Bits 17:2 95 #define AUX_MAC_O_ACC17_2 0x00000040 96 97 // Accumulator Bits 18:3 98 #define AUX_MAC_O_ACC18_3 0x00000044 99 100 // Accumulator Bits 19:4 101 #define AUX_MAC_O_ACC19_4 0x00000048 102 103 // Accumulator Bits 20:5 104 #define AUX_MAC_O_ACC20_5 0x0000004C 105 106 // Accumulator Bits 21:6 107 #define AUX_MAC_O_ACC21_6 0x00000050 108 109 // Accumulator Bits 22:7 110 #define AUX_MAC_O_ACC22_7 0x00000054 111 112 // Accumulator Bits 23:8 113 #define AUX_MAC_O_ACC23_8 0x00000058 114 115 // Accumulator Bits 24:9 116 #define AUX_MAC_O_ACC24_9 0x0000005C 117 118 // Accumulator Bits 25:10 119 #define AUX_MAC_O_ACC25_10 0x00000060 120 121 // Accumulator Bits 26:11 122 #define AUX_MAC_O_ACC26_11 0x00000064 123 124 // Accumulator Bits 27:12 125 #define AUX_MAC_O_ACC27_12 0x00000068 126 127 // Accumulator Bits 28:13 128 #define AUX_MAC_O_ACC28_13 0x0000006C 129 130 // Accumulator Bits 29:14 131 #define AUX_MAC_O_ACC29_14 0x00000070 132 133 // Accumulator Bits 30:15 134 #define AUX_MAC_O_ACC30_15 0x00000074 135 136 // Accumulator Bits 31:16 137 #define AUX_MAC_O_ACC31_16 0x00000078 138 139 // Accumulator Bits 32:17 140 #define AUX_MAC_O_ACC32_17 0x0000007C 141 142 // Accumulator Bits 33:18 143 #define AUX_MAC_O_ACC33_18 0x00000080 144 145 // Accumulator Bits 34:19 146 #define AUX_MAC_O_ACC34_19 0x00000084 147 148 // Accumulator Bits 35:20 149 #define AUX_MAC_O_ACC35_20 0x00000088 150 151 // Accumulator Bits 36:21 152 #define AUX_MAC_O_ACC36_21 0x0000008C 153 154 // Accumulator Bits 37:22 155 #define AUX_MAC_O_ACC37_22 0x00000090 156 157 // Accumulator Bits 38:23 158 #define AUX_MAC_O_ACC38_23 0x00000094 159 160 // Accumulator Bits 39:24 161 #define AUX_MAC_O_ACC39_24 0x00000098 162 163 // Accumulator Bits 39:32 164 #define AUX_MAC_O_ACC39_32 0x0000009C 165 166 //***************************************************************************** 167 // 168 // Register: AUX_MAC_O_OP0S 169 // 170 //***************************************************************************** 171 // Field: [15:0] OP0_VALUE 172 // 173 // Signed operand 0. 174 // 175 // Operand for multiply, multiply-and-accumulate, or 32-bit add operations. 176 #define AUX_MAC_OP0S_OP0_VALUE_W 16 177 #define AUX_MAC_OP0S_OP0_VALUE_M 0x0000FFFF 178 #define AUX_MAC_OP0S_OP0_VALUE_S 0 179 180 //***************************************************************************** 181 // 182 // Register: AUX_MAC_O_OP0U 183 // 184 //***************************************************************************** 185 // Field: [15:0] OP0_VALUE 186 // 187 // Unsigned operand 0. 188 // 189 // Operand for multiply, multiply-and-accumulate, or 32-bit add operations. 190 #define AUX_MAC_OP0U_OP0_VALUE_W 16 191 #define AUX_MAC_OP0U_OP0_VALUE_M 0x0000FFFF 192 #define AUX_MAC_OP0U_OP0_VALUE_S 0 193 194 //***************************************************************************** 195 // 196 // Register: AUX_MAC_O_OP1SMUL 197 // 198 //***************************************************************************** 199 // Field: [15:0] OP1_VALUE 200 // 201 // Signed operand 1 and multiplication trigger. 202 // 203 // Write OP1_VALUE to set signed operand 1 and trigger the following operation: 204 // 205 // When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * 206 // OP0S.OP0_VALUE. 207 // When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * 208 // OP0U.OP0_VALUE. 209 #define AUX_MAC_OP1SMUL_OP1_VALUE_W 16 210 #define AUX_MAC_OP1SMUL_OP1_VALUE_M 0x0000FFFF 211 #define AUX_MAC_OP1SMUL_OP1_VALUE_S 0 212 213 //***************************************************************************** 214 // 215 // Register: AUX_MAC_O_OP1UMUL 216 // 217 //***************************************************************************** 218 // Field: [15:0] OP1_VALUE 219 // 220 // Unsigned operand 1 and multiplication trigger. 221 // 222 // Write OP1_VALUE to set unsigned operand 1 and trigger the following 223 // operation: 224 // 225 // When operand 0 was written to OP0S.OP0_VALUE: ACC = OP1_VALUE * 226 // OP0S.OP0_VALUE. 227 // When operand 0 was written to OP0U.OP0_VALUE: ACC = OP1_VALUE * 228 // OP0U.OP0_VALUE. 229 #define AUX_MAC_OP1UMUL_OP1_VALUE_W 16 230 #define AUX_MAC_OP1UMUL_OP1_VALUE_M 0x0000FFFF 231 #define AUX_MAC_OP1UMUL_OP1_VALUE_S 0 232 233 //***************************************************************************** 234 // 235 // Register: AUX_MAC_O_OP1SMAC 236 // 237 //***************************************************************************** 238 // Field: [15:0] OP1_VALUE 239 // 240 // Signed operand 1 and multiply-accumulation trigger. 241 // 242 // Write OP1_VALUE to set signed operand 1 and trigger the following operation: 243 // 244 // When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * 245 // OP0S.OP0_VALUE ). 246 // When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * 247 // OP0U.OP0_VALUE ). 248 #define AUX_MAC_OP1SMAC_OP1_VALUE_W 16 249 #define AUX_MAC_OP1SMAC_OP1_VALUE_M 0x0000FFFF 250 #define AUX_MAC_OP1SMAC_OP1_VALUE_S 0 251 252 //***************************************************************************** 253 // 254 // Register: AUX_MAC_O_OP1UMAC 255 // 256 //***************************************************************************** 257 // Field: [15:0] OP1_VALUE 258 // 259 // Unsigned operand 1 and multiply-accumulation trigger. 260 // 261 // Write OP1_VALUE to set unsigned operand 1 and trigger the following 262 // operation: 263 // 264 // When operand 0 was written to OP0S.OP0_VALUE: ACC = ACC + ( OP1_VALUE * 265 // OP0S.OP0_VALUE ). 266 // When operand 0 was written to OP0U.OP0_VALUE: ACC = ACC + ( OP1_VALUE * 267 // OP0U.OP0_VALUE ). 268 #define AUX_MAC_OP1UMAC_OP1_VALUE_W 16 269 #define AUX_MAC_OP1UMAC_OP1_VALUE_M 0x0000FFFF 270 #define AUX_MAC_OP1UMAC_OP1_VALUE_S 0 271 272 //***************************************************************************** 273 // 274 // Register: AUX_MAC_O_OP1SADD16 275 // 276 //***************************************************************************** 277 // Field: [15:0] OP1_VALUE 278 // 279 // Signed operand 1 and 16-bit addition trigger. 280 // 281 // Write OP1_VALUE to set signed operand 1 and trigger the following operation: 282 // 283 // ACC = ACC + OP1_VALUE. 284 #define AUX_MAC_OP1SADD16_OP1_VALUE_W 16 285 #define AUX_MAC_OP1SADD16_OP1_VALUE_M 0x0000FFFF 286 #define AUX_MAC_OP1SADD16_OP1_VALUE_S 0 287 288 //***************************************************************************** 289 // 290 // Register: AUX_MAC_O_OP1UADD16 291 // 292 //***************************************************************************** 293 // Field: [15:0] OP1_VALUE 294 // 295 // Unsigned operand 1 and 16-bit addition trigger. 296 // 297 // Write OP1_VALUE to set unsigned operand 1 and trigger the following 298 // operation: 299 // 300 // ACC = ACC + OP1_VALUE. 301 #define AUX_MAC_OP1UADD16_OP1_VALUE_W 16 302 #define AUX_MAC_OP1UADD16_OP1_VALUE_M 0x0000FFFF 303 #define AUX_MAC_OP1UADD16_OP1_VALUE_S 0 304 305 //***************************************************************************** 306 // 307 // Register: AUX_MAC_O_OP1SADD32 308 // 309 //***************************************************************************** 310 // Field: [15:0] OP1_VALUE 311 // 312 // Upper half of signed 32-bit operand and addition trigger. 313 // 314 // Write OP1_VALUE to set upper half of signed 32-bit operand and trigger the 315 // following operation: 316 // 317 // When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + 318 // (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). 319 // When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + 320 // (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). 321 #define AUX_MAC_OP1SADD32_OP1_VALUE_W 16 322 #define AUX_MAC_OP1SADD32_OP1_VALUE_M 0x0000FFFF 323 #define AUX_MAC_OP1SADD32_OP1_VALUE_S 0 324 325 //***************************************************************************** 326 // 327 // Register: AUX_MAC_O_OP1UADD32 328 // 329 //***************************************************************************** 330 // Field: [15:0] OP1_VALUE 331 // 332 // Upper half of unsigned 32-bit operand and addition trigger. 333 // 334 // Write OP1_VALUE to set upper half of unsigned 32-bit operand and trigger the 335 // following operation: 336 // 337 // When lower half of 32-bit operand was written to OP0S.OP0_VALUE: ACC = ACC + 338 // (( OP1_VALUE << 16) | OP0S.OP0_VALUE ). 339 // When lower half of 32-bit operand was written to OP0U.OP0_VALUE: ACC = ACC + 340 // (( OP1_VALUE << 16) | OP0U.OP0_VALUE ). 341 #define AUX_MAC_OP1UADD32_OP1_VALUE_W 16 342 #define AUX_MAC_OP1UADD32_OP1_VALUE_M 0x0000FFFF 343 #define AUX_MAC_OP1UADD32_OP1_VALUE_S 0 344 345 //***************************************************************************** 346 // 347 // Register: AUX_MAC_O_CLZ 348 // 349 //***************************************************************************** 350 // Field: [5:0] VALUE 351 // 352 // Number of leading zero bits in the accumulator: 353 // 354 // 0x00: 0 leading zeros. 355 // 0x01: 1 leading zero. 356 // ... 357 // 0x28: 40 leading zeros (accumulator value is 0). 358 #define AUX_MAC_CLZ_VALUE_W 6 359 #define AUX_MAC_CLZ_VALUE_M 0x0000003F 360 #define AUX_MAC_CLZ_VALUE_S 0 361 362 //***************************************************************************** 363 // 364 // Register: AUX_MAC_O_CLS 365 // 366 //***************************************************************************** 367 // Field: [5:0] VALUE 368 // 369 // Number of leading sign bits in the accumulator. 370 // 371 // When MSB of accumulator is 0, VALUE is number of leading zeros, MSB 372 // included. 373 // When MSB of accumulator is 1, VALUE is number of leading ones, MSB included. 374 // 375 // VALUE range is 1 thru 40. 376 #define AUX_MAC_CLS_VALUE_W 6 377 #define AUX_MAC_CLS_VALUE_M 0x0000003F 378 #define AUX_MAC_CLS_VALUE_S 0 379 380 //***************************************************************************** 381 // 382 // Register: AUX_MAC_O_ACCSHIFT 383 // 384 //***************************************************************************** 385 // Field: [2] LSL1 386 // 387 // Logic shift left by 1 bit. 388 // 389 // Write 1 to shift the accumulator one bit to the left, 0 inserted at bit 0. 390 #define AUX_MAC_ACCSHIFT_LSL1 0x00000004 391 #define AUX_MAC_ACCSHIFT_LSL1_BITN 2 392 #define AUX_MAC_ACCSHIFT_LSL1_M 0x00000004 393 #define AUX_MAC_ACCSHIFT_LSL1_S 2 394 395 // Field: [1] LSR1 396 // 397 // Logic shift right by 1 bit. 398 // 399 // Write 1 to shift the accumulator one bit to the right, 0 inserted at bit 39. 400 #define AUX_MAC_ACCSHIFT_LSR1 0x00000002 401 #define AUX_MAC_ACCSHIFT_LSR1_BITN 1 402 #define AUX_MAC_ACCSHIFT_LSR1_M 0x00000002 403 #define AUX_MAC_ACCSHIFT_LSR1_S 1 404 405 // Field: [0] ASR1 406 // 407 // Arithmetic shift right by 1 bit. 408 // 409 // Write 1 to shift the accumulator one bit to the right, previous sign bit 410 // inserted at bit 39. 411 #define AUX_MAC_ACCSHIFT_ASR1 0x00000001 412 #define AUX_MAC_ACCSHIFT_ASR1_BITN 0 413 #define AUX_MAC_ACCSHIFT_ASR1_M 0x00000001 414 #define AUX_MAC_ACCSHIFT_ASR1_S 0 415 416 //***************************************************************************** 417 // 418 // Register: AUX_MAC_O_ACCRESET 419 // 420 //***************************************************************************** 421 // Field: [15:0] TRG 422 // 423 // Write any value to this register to trigger a reset of all bits in the 424 // accumulator. 425 #define AUX_MAC_ACCRESET_TRG_W 16 426 #define AUX_MAC_ACCRESET_TRG_M 0x0000FFFF 427 #define AUX_MAC_ACCRESET_TRG_S 0 428 429 //***************************************************************************** 430 // 431 // Register: AUX_MAC_O_ACC15_0 432 // 433 //***************************************************************************** 434 // Field: [15:0] VALUE 435 // 436 // Value of the accumulator, bits 15:0. 437 // 438 // Write VALUE to initialize bits 15:0 of accumulator. 439 #define AUX_MAC_ACC15_0_VALUE_W 16 440 #define AUX_MAC_ACC15_0_VALUE_M 0x0000FFFF 441 #define AUX_MAC_ACC15_0_VALUE_S 0 442 443 //***************************************************************************** 444 // 445 // Register: AUX_MAC_O_ACC16_1 446 // 447 //***************************************************************************** 448 // Field: [15:0] VALUE 449 // 450 // Value of the accumulator, bits 16:1. 451 #define AUX_MAC_ACC16_1_VALUE_W 16 452 #define AUX_MAC_ACC16_1_VALUE_M 0x0000FFFF 453 #define AUX_MAC_ACC16_1_VALUE_S 0 454 455 //***************************************************************************** 456 // 457 // Register: AUX_MAC_O_ACC17_2 458 // 459 //***************************************************************************** 460 // Field: [15:0] VALUE 461 // 462 // Value of the accumulator, bits 17:2. 463 #define AUX_MAC_ACC17_2_VALUE_W 16 464 #define AUX_MAC_ACC17_2_VALUE_M 0x0000FFFF 465 #define AUX_MAC_ACC17_2_VALUE_S 0 466 467 //***************************************************************************** 468 // 469 // Register: AUX_MAC_O_ACC18_3 470 // 471 //***************************************************************************** 472 // Field: [15:0] VALUE 473 // 474 // Value of the accumulator, bits 18:3. 475 #define AUX_MAC_ACC18_3_VALUE_W 16 476 #define AUX_MAC_ACC18_3_VALUE_M 0x0000FFFF 477 #define AUX_MAC_ACC18_3_VALUE_S 0 478 479 //***************************************************************************** 480 // 481 // Register: AUX_MAC_O_ACC19_4 482 // 483 //***************************************************************************** 484 // Field: [15:0] VALUE 485 // 486 // Value of the accumulator, bits 19:4. 487 #define AUX_MAC_ACC19_4_VALUE_W 16 488 #define AUX_MAC_ACC19_4_VALUE_M 0x0000FFFF 489 #define AUX_MAC_ACC19_4_VALUE_S 0 490 491 //***************************************************************************** 492 // 493 // Register: AUX_MAC_O_ACC20_5 494 // 495 //***************************************************************************** 496 // Field: [15:0] VALUE 497 // 498 // Value of the accumulator, bits 20:5. 499 #define AUX_MAC_ACC20_5_VALUE_W 16 500 #define AUX_MAC_ACC20_5_VALUE_M 0x0000FFFF 501 #define AUX_MAC_ACC20_5_VALUE_S 0 502 503 //***************************************************************************** 504 // 505 // Register: AUX_MAC_O_ACC21_6 506 // 507 //***************************************************************************** 508 // Field: [15:0] VALUE 509 // 510 // Value of the accumulator, bits 21:6. 511 #define AUX_MAC_ACC21_6_VALUE_W 16 512 #define AUX_MAC_ACC21_6_VALUE_M 0x0000FFFF 513 #define AUX_MAC_ACC21_6_VALUE_S 0 514 515 //***************************************************************************** 516 // 517 // Register: AUX_MAC_O_ACC22_7 518 // 519 //***************************************************************************** 520 // Field: [15:0] VALUE 521 // 522 // Value of the accumulator, bits 22:7. 523 #define AUX_MAC_ACC22_7_VALUE_W 16 524 #define AUX_MAC_ACC22_7_VALUE_M 0x0000FFFF 525 #define AUX_MAC_ACC22_7_VALUE_S 0 526 527 //***************************************************************************** 528 // 529 // Register: AUX_MAC_O_ACC23_8 530 // 531 //***************************************************************************** 532 // Field: [15:0] VALUE 533 // 534 // Value of the accumulator, bits 23:8. 535 #define AUX_MAC_ACC23_8_VALUE_W 16 536 #define AUX_MAC_ACC23_8_VALUE_M 0x0000FFFF 537 #define AUX_MAC_ACC23_8_VALUE_S 0 538 539 //***************************************************************************** 540 // 541 // Register: AUX_MAC_O_ACC24_9 542 // 543 //***************************************************************************** 544 // Field: [15:0] VALUE 545 // 546 // Value of the accumulator, bits 24:9. 547 #define AUX_MAC_ACC24_9_VALUE_W 16 548 #define AUX_MAC_ACC24_9_VALUE_M 0x0000FFFF 549 #define AUX_MAC_ACC24_9_VALUE_S 0 550 551 //***************************************************************************** 552 // 553 // Register: AUX_MAC_O_ACC25_10 554 // 555 //***************************************************************************** 556 // Field: [15:0] VALUE 557 // 558 // Value of the accumulator, bits 25:10. 559 #define AUX_MAC_ACC25_10_VALUE_W 16 560 #define AUX_MAC_ACC25_10_VALUE_M 0x0000FFFF 561 #define AUX_MAC_ACC25_10_VALUE_S 0 562 563 //***************************************************************************** 564 // 565 // Register: AUX_MAC_O_ACC26_11 566 // 567 //***************************************************************************** 568 // Field: [15:0] VALUE 569 // 570 // Value of the accumulator, bits 26:11. 571 #define AUX_MAC_ACC26_11_VALUE_W 16 572 #define AUX_MAC_ACC26_11_VALUE_M 0x0000FFFF 573 #define AUX_MAC_ACC26_11_VALUE_S 0 574 575 //***************************************************************************** 576 // 577 // Register: AUX_MAC_O_ACC27_12 578 // 579 //***************************************************************************** 580 // Field: [15:0] VALUE 581 // 582 // Value of the accumulator, bits 27:12. 583 #define AUX_MAC_ACC27_12_VALUE_W 16 584 #define AUX_MAC_ACC27_12_VALUE_M 0x0000FFFF 585 #define AUX_MAC_ACC27_12_VALUE_S 0 586 587 //***************************************************************************** 588 // 589 // Register: AUX_MAC_O_ACC28_13 590 // 591 //***************************************************************************** 592 // Field: [15:0] VALUE 593 // 594 // Value of the accumulator, bits 28:13. 595 #define AUX_MAC_ACC28_13_VALUE_W 16 596 #define AUX_MAC_ACC28_13_VALUE_M 0x0000FFFF 597 #define AUX_MAC_ACC28_13_VALUE_S 0 598 599 //***************************************************************************** 600 // 601 // Register: AUX_MAC_O_ACC29_14 602 // 603 //***************************************************************************** 604 // Field: [15:0] VALUE 605 // 606 // Value of the accumulator, bits 29:14. 607 #define AUX_MAC_ACC29_14_VALUE_W 16 608 #define AUX_MAC_ACC29_14_VALUE_M 0x0000FFFF 609 #define AUX_MAC_ACC29_14_VALUE_S 0 610 611 //***************************************************************************** 612 // 613 // Register: AUX_MAC_O_ACC30_15 614 // 615 //***************************************************************************** 616 // Field: [15:0] VALUE 617 // 618 // Value of the accumulator, bits 30:15. 619 #define AUX_MAC_ACC30_15_VALUE_W 16 620 #define AUX_MAC_ACC30_15_VALUE_M 0x0000FFFF 621 #define AUX_MAC_ACC30_15_VALUE_S 0 622 623 //***************************************************************************** 624 // 625 // Register: AUX_MAC_O_ACC31_16 626 // 627 //***************************************************************************** 628 // Field: [15:0] VALUE 629 // 630 // Value of the accumulator, bits 31:16. 631 // 632 // Write VALUE to initialize bits 31:16 of accumulator. 633 #define AUX_MAC_ACC31_16_VALUE_W 16 634 #define AUX_MAC_ACC31_16_VALUE_M 0x0000FFFF 635 #define AUX_MAC_ACC31_16_VALUE_S 0 636 637 //***************************************************************************** 638 // 639 // Register: AUX_MAC_O_ACC32_17 640 // 641 //***************************************************************************** 642 // Field: [15:0] VALUE 643 // 644 // Value of the accumulator, bits 32:17. 645 #define AUX_MAC_ACC32_17_VALUE_W 16 646 #define AUX_MAC_ACC32_17_VALUE_M 0x0000FFFF 647 #define AUX_MAC_ACC32_17_VALUE_S 0 648 649 //***************************************************************************** 650 // 651 // Register: AUX_MAC_O_ACC33_18 652 // 653 //***************************************************************************** 654 // Field: [15:0] VALUE 655 // 656 // Value of the accumulator, bits 33:18. 657 #define AUX_MAC_ACC33_18_VALUE_W 16 658 #define AUX_MAC_ACC33_18_VALUE_M 0x0000FFFF 659 #define AUX_MAC_ACC33_18_VALUE_S 0 660 661 //***************************************************************************** 662 // 663 // Register: AUX_MAC_O_ACC34_19 664 // 665 //***************************************************************************** 666 // Field: [15:0] VALUE 667 // 668 // Value of the accumulator, bits 34:19. 669 #define AUX_MAC_ACC34_19_VALUE_W 16 670 #define AUX_MAC_ACC34_19_VALUE_M 0x0000FFFF 671 #define AUX_MAC_ACC34_19_VALUE_S 0 672 673 //***************************************************************************** 674 // 675 // Register: AUX_MAC_O_ACC35_20 676 // 677 //***************************************************************************** 678 // Field: [15:0] VALUE 679 // 680 // Value of the accumulator, bits 35:20. 681 #define AUX_MAC_ACC35_20_VALUE_W 16 682 #define AUX_MAC_ACC35_20_VALUE_M 0x0000FFFF 683 #define AUX_MAC_ACC35_20_VALUE_S 0 684 685 //***************************************************************************** 686 // 687 // Register: AUX_MAC_O_ACC36_21 688 // 689 //***************************************************************************** 690 // Field: [15:0] VALUE 691 // 692 // Value of the accumulator, bits 36:21. 693 #define AUX_MAC_ACC36_21_VALUE_W 16 694 #define AUX_MAC_ACC36_21_VALUE_M 0x0000FFFF 695 #define AUX_MAC_ACC36_21_VALUE_S 0 696 697 //***************************************************************************** 698 // 699 // Register: AUX_MAC_O_ACC37_22 700 // 701 //***************************************************************************** 702 // Field: [15:0] VALUE 703 // 704 // Value of the accumulator, bits 37:22. 705 #define AUX_MAC_ACC37_22_VALUE_W 16 706 #define AUX_MAC_ACC37_22_VALUE_M 0x0000FFFF 707 #define AUX_MAC_ACC37_22_VALUE_S 0 708 709 //***************************************************************************** 710 // 711 // Register: AUX_MAC_O_ACC38_23 712 // 713 //***************************************************************************** 714 // Field: [15:0] VALUE 715 // 716 // Value of the accumulator, bits 38:23. 717 #define AUX_MAC_ACC38_23_VALUE_W 16 718 #define AUX_MAC_ACC38_23_VALUE_M 0x0000FFFF 719 #define AUX_MAC_ACC38_23_VALUE_S 0 720 721 //***************************************************************************** 722 // 723 // Register: AUX_MAC_O_ACC39_24 724 // 725 //***************************************************************************** 726 // Field: [15:0] VALUE 727 // 728 // Value of the accumulator, bits 39:24. 729 #define AUX_MAC_ACC39_24_VALUE_W 16 730 #define AUX_MAC_ACC39_24_VALUE_M 0x0000FFFF 731 #define AUX_MAC_ACC39_24_VALUE_S 0 732 733 //***************************************************************************** 734 // 735 // Register: AUX_MAC_O_ACC39_32 736 // 737 //***************************************************************************** 738 // Field: [7:0] VALUE 739 // 740 // Value of the accumulator, bits 39:32. 741 // 742 // Write VALUE to initialize bits 39:32 of accumulator. 743 #define AUX_MAC_ACC39_32_VALUE_W 8 744 #define AUX_MAC_ACC39_32_VALUE_M 0x000000FF 745 #define AUX_MAC_ACC39_32_VALUE_S 0 746 747 748 #endif // __AUX_MAC__ 749
