1 /****************************************************************************** 2 * Filename: hw_aux_anaif_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_ANAIF_H__ 38 #define __HW_AUX_ANAIF_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_ANAIF component 44 // 45 //***************************************************************************** 46 // ADC Control 47 #define AUX_ANAIF_O_ADCCTL 0x00000010 48 49 // ADC FIFO Status 50 #define AUX_ANAIF_O_ADCFIFOSTAT 0x00000014 51 52 // ADC FIFO 53 #define AUX_ANAIF_O_ADCFIFO 0x00000018 54 55 // ADC Trigger 56 #define AUX_ANAIF_O_ADCTRIG 0x0000001C 57 58 // Current Source Control 59 #define AUX_ANAIF_O_ISRCCTL 0x00000020 60 61 // DAC Control 62 #define AUX_ANAIF_O_DACCTL 0x00000030 63 64 // Low Power Mode Bias Control 65 #define AUX_ANAIF_O_LPMBIASCTL 0x00000034 66 67 // DAC Sample Control 68 #define AUX_ANAIF_O_DACSMPLCTL 0x00000038 69 70 // DAC Sample Configuration 0 71 #define AUX_ANAIF_O_DACSMPLCFG0 0x0000003C 72 73 // DAC Sample Configuration 1 74 #define AUX_ANAIF_O_DACSMPLCFG1 0x00000040 75 76 // DAC Value 77 #define AUX_ANAIF_O_DACVALUE 0x00000044 78 79 // DAC Status 80 #define AUX_ANAIF_O_DACSTAT 0x00000048 81 82 //***************************************************************************** 83 // 84 // Register: AUX_ANAIF_O_ADCCTL 85 // 86 //***************************************************************************** 87 // Field: [14] START_POL 88 // 89 // Select active polarity for START_SRC event. 90 // ENUMs: 91 // FALL Set ADC trigger on falling edge of event source. 92 // RISE Set ADC trigger on rising edge of event source. 93 #define AUX_ANAIF_ADCCTL_START_POL 0x00004000 94 #define AUX_ANAIF_ADCCTL_START_POL_BITN 14 95 #define AUX_ANAIF_ADCCTL_START_POL_M 0x00004000 96 #define AUX_ANAIF_ADCCTL_START_POL_S 14 97 #define AUX_ANAIF_ADCCTL_START_POL_FALL 0x00004000 98 #define AUX_ANAIF_ADCCTL_START_POL_RISE 0x00000000 99 100 // Field: [13:8] START_SRC 101 // 102 // Select ADC trigger event source from the asynchronous AUX event bus. 103 // 104 // Set START_SRC to NO_EVENT if you want to trigger the ADC manually through 105 // ADCTRIG.START. 106 // 107 // If you write a non-enumerated value the behavior is identical to NO_EVENT. 108 // The written value is returned when read. 109 // ENUMs: 110 // NO_EVENT No event. 111 // AUX_SMPH_AUTOTAKE_DONE AUX_EVCTL:EVSTAT3.AUX_SMPH_AUTOTAKE_DONE 112 // AUX_ISRC_RESET_N AUX_EVCTL:EVSTAT3.AUX_ISRC_RESET_N 113 // AUX_TDC_DONE AUX_EVCTL:EVSTAT3.AUX_TDC_DONE 114 // AUX_TIMER0_EV AUX_EVCTL:EVSTAT3.AUX_TIMER0_EV 115 // AUX_TIMER1_EV AUX_EVCTL:EVSTAT3.AUX_TIMER1_EV 116 // AUX_TIMER2_PULSE AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE 117 // AUX_TIMER2_EV3 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3 118 // AUX_TIMER2_EV2 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2 119 // AUX_TIMER2_EV1 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1 120 // AUX_TIMER2_EV0 AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0 121 // AUX_COMPB AUX_EVCTL:EVSTAT2.AUX_COMPB 122 // AUX_COMPA AUX_EVCTL:EVSTAT2.AUX_COMPA 123 // MCU_EV AUX_EVCTL:EVSTAT2.MCU_EV 124 // ACLK_REF AUX_EVCTL:EVSTAT2.ACLK_REF 125 // VDDR_RECHARGE AUX_EVCTL:EVSTAT2.VDDR_RECHARGE 126 // MCU_ACTIVE AUX_EVCTL:EVSTAT2.MCU_ACTIVE 127 // PWR_DWN AUX_EVCTL:EVSTAT2.PWR_DWN 128 // SCLK_LF AUX_EVCTL:EVSTAT2.SCLK_LF 129 // AON_BATMON_TEMP_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_TEMP_UPD 130 // AON_BATMON_BAT_UPD AUX_EVCTL:EVSTAT2.AON_BATMON_BAT_UPD 131 // AON_RTC_4KHZ AUX_EVCTL:EVSTAT2.AON_RTC_4KHZ 132 // AON_RTC_CH2_DLY AUX_EVCTL:EVSTAT2.AON_RTC_CH2_DLY 133 // AON_RTC_CH2 AUX_EVCTL:EVSTAT2.AON_RTC_CH2 134 // MANUAL_EV AUX_EVCTL:EVSTAT2.MANUAL_EV 135 // AUXIO31 AUX_EVCTL:EVSTAT1.AUXIO31 136 // AUXIO30 AUX_EVCTL:EVSTAT1.AUXIO30 137 // AUXIO29 AUX_EVCTL:EVSTAT1.AUXIO29 138 // AUXIO28 AUX_EVCTL:EVSTAT1.AUXIO28 139 // AUXIO27 AUX_EVCTL:EVSTAT1.AUXIO27 140 // AUXIO26 AUX_EVCTL:EVSTAT1.AUXIO26 141 // AUXIO25 AUX_EVCTL:EVSTAT1.AUXIO25 142 // AUXIO24 AUX_EVCTL:EVSTAT1.AUXIO24 143 // AUXIO23 AUX_EVCTL:EVSTAT1.AUXIO23 144 // AUXIO22 AUX_EVCTL:EVSTAT1.AUXIO22 145 // AUXIO21 AUX_EVCTL:EVSTAT1.AUXIO21 146 // AUXIO20 AUX_EVCTL:EVSTAT1.AUXIO20 147 // AUXIO19 AUX_EVCTL:EVSTAT1.AUXIO19 148 // AUXIO18 AUX_EVCTL:EVSTAT1.AUXIO18 149 // AUXIO17 AUX_EVCTL:EVSTAT1.AUXIO17 150 // AUXIO16 AUX_EVCTL:EVSTAT1.AUXIO16 151 // AUXIO15 AUX_EVCTL:EVSTAT0.AUXIO15 152 // AUXIO14 AUX_EVCTL:EVSTAT0.AUXIO14 153 // AUXIO13 AUX_EVCTL:EVSTAT0.AUXIO13 154 // AUXIO12 AUX_EVCTL:EVSTAT0.AUXIO12 155 // AUXIO11 AUX_EVCTL:EVSTAT0.AUXIO11 156 // AUXIO10 AUX_EVCTL:EVSTAT0.AUXIO10 157 // AUXIO9 AUX_EVCTL:EVSTAT0.AUXIO9 158 // AUXIO8 AUX_EVCTL:EVSTAT0.AUXIO8 159 // AUXIO7 AUX_EVCTL:EVSTAT0.AUXIO7 160 // AUXIO6 AUX_EVCTL:EVSTAT0.AUXIO6 161 // AUXIO5 AUX_EVCTL:EVSTAT0.AUXIO5 162 // AUXIO4 AUX_EVCTL:EVSTAT0.AUXIO4 163 // AUXIO3 AUX_EVCTL:EVSTAT0.AUXIO3 164 // AUXIO2 AUX_EVCTL:EVSTAT0.AUXIO2 165 // AUXIO1 AUX_EVCTL:EVSTAT0.AUXIO1 166 // AUXIO0 AUX_EVCTL:EVSTAT0.AUXIO0 167 #define AUX_ANAIF_ADCCTL_START_SRC_W 6 168 #define AUX_ANAIF_ADCCTL_START_SRC_M 0x00003F00 169 #define AUX_ANAIF_ADCCTL_START_SRC_S 8 170 #define AUX_ANAIF_ADCCTL_START_SRC_NO_EVENT 0x00003F00 171 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_SMPH_AUTOTAKE_DONE 0x00003D00 172 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_ISRC_RESET_N 0x00003800 173 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_TDC_DONE 0x00003700 174 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER0_EV 0x00003600 175 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER1_EV 0x00003500 176 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_PULSE 0x00003400 177 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV3 0x00003300 178 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV2 0x00003200 179 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV1 0x00003100 180 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_TIMER2_EV0 0x00003000 181 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPB 0x00002F00 182 #define AUX_ANAIF_ADCCTL_START_SRC_AUX_COMPA 0x00002E00 183 #define AUX_ANAIF_ADCCTL_START_SRC_MCU_EV 0x00002B00 184 #define AUX_ANAIF_ADCCTL_START_SRC_ACLK_REF 0x00002A00 185 #define AUX_ANAIF_ADCCTL_START_SRC_VDDR_RECHARGE 0x00002900 186 #define AUX_ANAIF_ADCCTL_START_SRC_MCU_ACTIVE 0x00002800 187 #define AUX_ANAIF_ADCCTL_START_SRC_PWR_DWN 0x00002700 188 #define AUX_ANAIF_ADCCTL_START_SRC_SCLK_LF 0x00002600 189 #define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_TEMP_UPD 0x00002500 190 #define AUX_ANAIF_ADCCTL_START_SRC_AON_BATMON_BAT_UPD 0x00002400 191 #define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_4KHZ 0x00002300 192 #define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2_DLY 0x00002200 193 #define AUX_ANAIF_ADCCTL_START_SRC_AON_RTC_CH2 0x00002100 194 #define AUX_ANAIF_ADCCTL_START_SRC_MANUAL_EV 0x00002000 195 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO31 0x00001F00 196 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO30 0x00001E00 197 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO29 0x00001D00 198 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO28 0x00001C00 199 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO27 0x00001B00 200 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO26 0x00001A00 201 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO25 0x00001900 202 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO24 0x00001800 203 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO23 0x00001700 204 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO22 0x00001600 205 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO21 0x00001500 206 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO20 0x00001400 207 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO19 0x00001300 208 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO18 0x00001200 209 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO17 0x00001100 210 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO16 0x00001000 211 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO15 0x00000F00 212 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO14 0x00000E00 213 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO13 0x00000D00 214 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO12 0x00000C00 215 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO11 0x00000B00 216 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO10 0x00000A00 217 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO9 0x00000900 218 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO8 0x00000800 219 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO7 0x00000700 220 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO6 0x00000600 221 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO5 0x00000500 222 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO4 0x00000400 223 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO3 0x00000300 224 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO2 0x00000200 225 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO1 0x00000100 226 #define AUX_ANAIF_ADCCTL_START_SRC_AUXIO0 0x00000000 227 228 // Field: [1:0] CMD 229 // 230 // ADC interface command. 231 // 232 // Non-enumerated values are not supported. The written value is returned when 233 // read. 234 // ENUMs: 235 // FLUSH Flush ADC FIFO. 236 // 237 // You must set CMD to EN or 238 // DIS after flush. 239 // 240 // System CPU must wait two 241 // clock cycles before it sets CMD to EN or DIS. 242 // EN Enable ADC interface. 243 // DIS Disable ADC interface. 244 #define AUX_ANAIF_ADCCTL_CMD_W 2 245 #define AUX_ANAIF_ADCCTL_CMD_M 0x00000003 246 #define AUX_ANAIF_ADCCTL_CMD_S 0 247 #define AUX_ANAIF_ADCCTL_CMD_FLUSH 0x00000003 248 #define AUX_ANAIF_ADCCTL_CMD_EN 0x00000001 249 #define AUX_ANAIF_ADCCTL_CMD_DIS 0x00000000 250 251 //***************************************************************************** 252 // 253 // Register: AUX_ANAIF_O_ADCFIFOSTAT 254 // 255 //***************************************************************************** 256 // Field: [4] OVERFLOW 257 // 258 // FIFO overflow flag. 259 // 260 // 0: FIFO has not overflowed. 261 // 1: FIFO has overflowed, this flag is sticky until you flush the FIFO. 262 // 263 // When the flag is set, the ADC FIFO write pointer is static. It is not 264 // possible to add more samples to the ADC FIFO. Flush FIFO to clear the flag. 265 #define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW 0x00000010 266 #define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_BITN 4 267 #define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_M 0x00000010 268 #define AUX_ANAIF_ADCFIFOSTAT_OVERFLOW_S 4 269 270 // Field: [3] UNDERFLOW 271 // 272 // FIFO underflow flag. 273 // 274 // 0: FIFO has not underflowed. 275 // 1: FIFO has underflowed, this flag is sticky until you flush the FIFO. 276 // 277 // When the flag is set, the ADC FIFO read pointer is static. Read returns the 278 // previous sample that was read. Flush FIFO to clear the flag. 279 #define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW 0x00000008 280 #define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_BITN 3 281 #define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_M 0x00000008 282 #define AUX_ANAIF_ADCFIFOSTAT_UNDERFLOW_S 3 283 284 // Field: [2] FULL 285 // 286 // FIFO full flag. 287 // 288 // 0: FIFO is not full, there is less than 4 samples in the FIFO. 289 // 1: FIFO is full, there are 4 samples in the FIFO. 290 // 291 // When the flag is set, it is not possible to add more samples to the ADC 292 // FIFO. An attempt to add samples sets the OVERFLOW flag. 293 #define AUX_ANAIF_ADCFIFOSTAT_FULL 0x00000004 294 #define AUX_ANAIF_ADCFIFOSTAT_FULL_BITN 2 295 #define AUX_ANAIF_ADCFIFOSTAT_FULL_M 0x00000004 296 #define AUX_ANAIF_ADCFIFOSTAT_FULL_S 2 297 298 // Field: [1] ALMOST_FULL 299 // 300 // FIFO almost full flag. 301 // 302 // 0: There are less than 3 samples in the FIFO, or the FIFO is full. The FULL 303 // flag is also asserted in the latter case. 304 // 1: There are 3 samples in the FIFO, there is room for one more sample. 305 #define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL 0x00000002 306 #define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_BITN 1 307 #define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_M 0x00000002 308 #define AUX_ANAIF_ADCFIFOSTAT_ALMOST_FULL_S 1 309 310 // Field: [0] EMPTY 311 // 312 // FIFO empty flag. 313 // 314 // 0: FIFO contains one or more samples. 315 // 1: FIFO is empty. 316 // 317 // When the flag is set, read returns the previous sample that was read and 318 // sets the UNDERFLOW flag. 319 #define AUX_ANAIF_ADCFIFOSTAT_EMPTY 0x00000001 320 #define AUX_ANAIF_ADCFIFOSTAT_EMPTY_BITN 0 321 #define AUX_ANAIF_ADCFIFOSTAT_EMPTY_M 0x00000001 322 #define AUX_ANAIF_ADCFIFOSTAT_EMPTY_S 0 323 324 //***************************************************************************** 325 // 326 // Register: AUX_ANAIF_O_ADCFIFO 327 // 328 //***************************************************************************** 329 // Field: [11:0] DATA 330 // 331 // FIFO data. 332 // 333 // Read: 334 // Get oldest ADC sample from FIFO. 335 // 336 // Write: 337 // Write dummy sample to FIFO. This is useful for code development when you do 338 // not have real ADC samples. 339 #define AUX_ANAIF_ADCFIFO_DATA_W 12 340 #define AUX_ANAIF_ADCFIFO_DATA_M 0x00000FFF 341 #define AUX_ANAIF_ADCFIFO_DATA_S 0 342 343 //***************************************************************************** 344 // 345 // Register: AUX_ANAIF_O_ADCTRIG 346 // 347 //***************************************************************************** 348 // Field: [0] START 349 // 350 // Manual ADC trigger. 351 // 352 // Write any value to START to trigger ADC. 353 // 354 // To manually trigger the ADC, you must set ADCCTL.START_SRC to NO_EVENT to 355 // avoid conflict with event-driven ADC trigger. 356 #define AUX_ANAIF_ADCTRIG_START 0x00000001 357 #define AUX_ANAIF_ADCTRIG_START_BITN 0 358 #define AUX_ANAIF_ADCTRIG_START_M 0x00000001 359 #define AUX_ANAIF_ADCTRIG_START_S 0 360 361 //***************************************************************************** 362 // 363 // Register: AUX_ANAIF_O_ISRCCTL 364 // 365 //***************************************************************************** 366 // Field: [0] RESET_N 367 // 368 // ISRC reset control. 369 // 370 // 0: ISRC drives 0 uA. 371 // 1: ISRC drives current ADI_4_AUX:ISRC.TRIM to COMPA_IN. 372 #define AUX_ANAIF_ISRCCTL_RESET_N 0x00000001 373 #define AUX_ANAIF_ISRCCTL_RESET_N_BITN 0 374 #define AUX_ANAIF_ISRCCTL_RESET_N_M 0x00000001 375 #define AUX_ANAIF_ISRCCTL_RESET_N_S 0 376 377 //***************************************************************************** 378 // 379 // Register: AUX_ANAIF_O_DACCTL 380 // 381 //***************************************************************************** 382 // Field: [5] DAC_EN 383 // 384 // DAC module enable. 385 // 386 // 0: Disable DAC. 387 // 1: Enable DAC. 388 // 389 // The Sensor Controller must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ 390 // equals PDA. 391 // 392 // The System CPU must not use the DAC when AUX_SYSIF:OPMODEREQ.REQ equals PDA 393 // in Standby TI-RTOS power mode. The System CPU must set 394 // AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE to BUS_RATE to use the DAC in Active 395 // and Idle TI-RTOS power modes. 396 #define AUX_ANAIF_DACCTL_DAC_EN 0x00000020 397 #define AUX_ANAIF_DACCTL_DAC_EN_BITN 5 398 #define AUX_ANAIF_DACCTL_DAC_EN_M 0x00000020 399 #define AUX_ANAIF_DACCTL_DAC_EN_S 5 400 401 // Field: [4] DAC_BUFFER_EN 402 // 403 // DAC buffer enable. 404 // 405 // DAC buffer reduces the time required to produce the programmed voltage at 406 // the expense of increased current consumption. 407 // 408 // 0: Disable DAC buffer. 409 // 1: Enable DAC buffer. 410 // 411 // Enable buffer when DAC_VOUT_SEL equals COMPA_IN. 412 // 413 // Do not enable the buffer when AUX_SYSIF:OPMODEREQ.REQ equals PDA or PDLP. 414 #define AUX_ANAIF_DACCTL_DAC_BUFFER_EN 0x00000010 415 #define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_BITN 4 416 #define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_M 0x00000010 417 #define AUX_ANAIF_DACCTL_DAC_BUFFER_EN_S 4 418 419 // Field: [3] DAC_PRECHARGE_EN 420 // 421 // DAC precharge enable. 422 // 423 // Only enable precharge when ADI_4_AUX:MUX2.DAC_VREF_SEL equals DCOUPL and 424 // VDDS is higher than 2.65 V. 425 // 426 // DAC output voltage range: 427 // 428 // 0: 0 V to 1.28 V. 429 // 1: 1.28 V to 2.56 V. 430 // 431 // Otherwise, see ADI_4_AUX:MUX2.DAC_VREF_SEL for DAC output voltage range. 432 // 433 // Enable precharge 1 us before you enable the DAC and the buffer. 434 #define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN 0x00000008 435 #define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_BITN 3 436 #define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_M 0x00000008 437 #define AUX_ANAIF_DACCTL_DAC_PRECHARGE_EN_S 3 438 439 // Field: [2:0] DAC_VOUT_SEL 440 // 441 // DAC output connection. 442 // 443 // An analog node must only have one driver. Other drivers for the following 444 // analog nodes are configured in [ANATOP_MMAP::ADI_4_AUX:*]. 445 // ENUMs: 446 // COMPA_IN Connect to COMPA_IN analog node. 447 // 448 // Required setting to drive 449 // external load selected in 450 // ADI_4_AUX:MUX1.COMPA_IN. 451 // COMPA_REF Connect to COMPA_REF analog node. 452 // 453 // It is not possible to 454 // drive external loads connected to COMPA_REF I/O 455 // mux with this setting. 456 // COMPB_REF Connect to COMPB_REF analog node. 457 // 458 // Required setting to use 459 // Comparator B. 460 // NC Connect to nothing 461 // 462 // It is recommended to use 463 // NC as intermediate step when you change 464 // DAC_VOUT_SEL. 465 #define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_W 3 466 #define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_M 0x00000007 467 #define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_S 0 468 #define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_IN 0x00000004 469 #define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPA_REF 0x00000002 470 #define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_COMPB_REF 0x00000001 471 #define AUX_ANAIF_DACCTL_DAC_VOUT_SEL_NC 0x00000000 472 473 //***************************************************************************** 474 // 475 // Register: AUX_ANAIF_O_LPMBIASCTL 476 // 477 //***************************************************************************** 478 // Field: [0] EN 479 // 480 // Module enable. 481 // 482 // 0: Disable low power mode bias module. 483 // 1: Enable low power mode bias module. 484 // 485 // Set EN to 1 15 us before you enable the DAC or Comparator A. 486 #define AUX_ANAIF_LPMBIASCTL_EN 0x00000001 487 #define AUX_ANAIF_LPMBIASCTL_EN_BITN 0 488 #define AUX_ANAIF_LPMBIASCTL_EN_M 0x00000001 489 #define AUX_ANAIF_LPMBIASCTL_EN_S 0 490 491 //***************************************************************************** 492 // 493 // Register: AUX_ANAIF_O_DACSMPLCTL 494 // 495 //***************************************************************************** 496 // Field: [0] EN 497 // 498 // DAC sample clock enable. 499 // 500 // 0: Disable sample clock. The sample clock stops low and DACSTAT becomes 0 501 // when the current sample clock period completes. 502 // 1: Enable DAC sample clock. DACSTAT must be 0 before you enable sample 503 // clock. 504 #define AUX_ANAIF_DACSMPLCTL_EN 0x00000001 505 #define AUX_ANAIF_DACSMPLCTL_EN_BITN 0 506 #define AUX_ANAIF_DACSMPLCTL_EN_M 0x00000001 507 #define AUX_ANAIF_DACSMPLCTL_EN_S 0 508 509 //***************************************************************************** 510 // 511 // Register: AUX_ANAIF_O_DACSMPLCFG0 512 // 513 //***************************************************************************** 514 // Field: [5:0] CLKDIV 515 // 516 // Clock division. 517 // 518 // AUX_SYSIF:PEROPRATE.ANAIF_DAC_OP_RATE divided by (CLKDIV + 1) determines the 519 // sample clock base frequency. 520 // 521 // 0: Divide by 1. 522 // 1: Divide by 2. 523 // ... 524 // 63: Divide by 64. 525 #define AUX_ANAIF_DACSMPLCFG0_CLKDIV_W 6 526 #define AUX_ANAIF_DACSMPLCFG0_CLKDIV_M 0x0000003F 527 #define AUX_ANAIF_DACSMPLCFG0_CLKDIV_S 0 528 529 //***************************************************************************** 530 // 531 // Register: AUX_ANAIF_O_DACSMPLCFG1 532 // 533 //***************************************************************************** 534 // Field: [14] H_PER 535 // 536 // High time. 537 // 538 // The sample clock period is high for this many base periods. 539 // 540 // 0: 2 periods 541 // 1: 4 periods 542 #define AUX_ANAIF_DACSMPLCFG1_H_PER 0x00004000 543 #define AUX_ANAIF_DACSMPLCFG1_H_PER_BITN 14 544 #define AUX_ANAIF_DACSMPLCFG1_H_PER_M 0x00004000 545 #define AUX_ANAIF_DACSMPLCFG1_H_PER_S 14 546 547 // Field: [13:12] L_PER 548 // 549 // Low time. 550 // 551 // The sample clock period is low for this many base periods. 552 // 553 // 0: 1 period 554 // 1: 2 periods 555 // 2: 3 periods 556 // 3: 4 periods 557 #define AUX_ANAIF_DACSMPLCFG1_L_PER_W 2 558 #define AUX_ANAIF_DACSMPLCFG1_L_PER_M 0x00003000 559 #define AUX_ANAIF_DACSMPLCFG1_L_PER_S 12 560 561 // Field: [11:8] SETUP_CNT 562 // 563 // Setup count. 564 // 565 // Number of active sample clock periods during the setup phase. 566 // 567 // 0: 1 sample clock period 568 // 1: 2 sample clock periods 569 // ... 570 // 15 : 16 sample clock periods 571 #define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_W 4 572 #define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_M 0x00000F00 573 #define AUX_ANAIF_DACSMPLCFG1_SETUP_CNT_S 8 574 575 // Field: [7:0] HOLD_INTERVAL 576 // 577 // Hold interval. 578 // 579 // Number of inactive sample clock periods between each active sample clock 580 // period during hold phase. The sample clock is low when inactive. 581 // 582 // The range is 0 to 255. 583 #define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_W 8 584 #define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_M 0x000000FF 585 #define AUX_ANAIF_DACSMPLCFG1_HOLD_INTERVAL_S 0 586 587 //***************************************************************************** 588 // 589 // Register: AUX_ANAIF_O_DACVALUE 590 // 591 //***************************************************************************** 592 // Field: [7:0] VALUE 593 // 594 // DAC value. 595 // 596 // Digital data word for the DAC. 597 // 598 // Only change VALUE when DACCTL.DAC_EN is 0. Then wait 1 us before you enable 599 // the DAC. 600 #define AUX_ANAIF_DACVALUE_VALUE_W 8 601 #define AUX_ANAIF_DACVALUE_VALUE_M 0x000000FF 602 #define AUX_ANAIF_DACVALUE_VALUE_S 0 603 604 //***************************************************************************** 605 // 606 // Register: AUX_ANAIF_O_DACSTAT 607 // 608 //***************************************************************************** 609 // Field: [1] SETUP_ACTIVE 610 // 611 // DAC setup phase status. 612 // 613 // 0: Sample clock is disabled or setup phase is complete. 614 // 1: Setup phase in progress. 615 #define AUX_ANAIF_DACSTAT_SETUP_ACTIVE 0x00000002 616 #define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_BITN 1 617 #define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_M 0x00000002 618 #define AUX_ANAIF_DACSTAT_SETUP_ACTIVE_S 1 619 620 // Field: [0] HOLD_ACTIVE 621 // 622 // DAC hold phase status. 623 // 624 // 0: Sample clock is disabled or DAC is not in hold phase. 625 // 1: Hold phase in progress. 626 #define AUX_ANAIF_DACSTAT_HOLD_ACTIVE 0x00000001 627 #define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_BITN 0 628 #define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_M 0x00000001 629 #define AUX_ANAIF_DACSTAT_HOLD_ACTIVE_S 0 630 631 632 #endif // __AUX_ANAIF__ 633
