1 /****************************************************************************** 2 * Filename: hw_aux_aiodio_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AUX_AIODIO_H__ 38 #define __HW_AUX_AIODIO_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AUX_AIODIO component 44 // 45 //***************************************************************************** 46 // Input Output Mode 47 #define AUX_AIODIO_O_IOMODE 0x00000000 48 49 // General Purpose Input Output Digital Input Enable 50 #define AUX_AIODIO_O_GPIODIE 0x00000004 51 52 // Input Output Peripheral Output Enable 53 #define AUX_AIODIO_O_IOPOE 0x00000008 54 55 // General Purpose Input Output Data Out 56 #define AUX_AIODIO_O_GPIODOUT 0x0000000C 57 58 // General Purpose Input Output Data In 59 #define AUX_AIODIO_O_GPIODIN 0x00000010 60 61 // General Purpose Input Output Data Out Set 62 #define AUX_AIODIO_O_GPIODOUTSET 0x00000014 63 64 // General Purpose Input Output Data Out Clear 65 #define AUX_AIODIO_O_GPIODOUTCLR 0x00000018 66 67 // General Purpose Input Output Data Out Toggle 68 #define AUX_AIODIO_O_GPIODOUTTGL 0x0000001C 69 70 // Input Output 0 Peripheral Select 71 #define AUX_AIODIO_O_IO0PSEL 0x00000020 72 73 // Input Output 1 Peripheral Select 74 #define AUX_AIODIO_O_IO1PSEL 0x00000024 75 76 // Input Output 2 Peripheral Select 77 #define AUX_AIODIO_O_IO2PSEL 0x00000028 78 79 // Input Output 3 Peripheral Select 80 #define AUX_AIODIO_O_IO3PSEL 0x0000002C 81 82 // Input Output 4 Peripheral Select 83 #define AUX_AIODIO_O_IO4PSEL 0x00000030 84 85 // Input Output 5 Peripheral Select 86 #define AUX_AIODIO_O_IO5PSEL 0x00000034 87 88 // Input Output 6 Peripheral Select 89 #define AUX_AIODIO_O_IO6PSEL 0x00000038 90 91 // Input Output 7 Peripheral Select 92 #define AUX_AIODIO_O_IO7PSEL 0x0000003C 93 94 // Input Output Mode Low 95 #define AUX_AIODIO_O_IOMODEL 0x00000040 96 97 // Input Output Mode High 98 #define AUX_AIODIO_O_IOMODEH 0x00000044 99 100 //***************************************************************************** 101 // 102 // Register: AUX_AIODIO_O_IOMODE 103 // 104 //***************************************************************************** 105 // Field: [15:14] IO7 106 // 107 // Selects mode for AUXIO[8i+7]. 108 // ENUMs: 109 // OPEN_SOURCE Open-Source Mode: 110 // 111 // When IOPOE bit 7 is 0: 112 // - If GPIODOUT bit 7 is 0: 113 // AUXIO[8i+7] is tri-stated or pulled. This 114 // depends on IOC:IOCFGn.PULL_CTL. 115 // - If GPIODOUT bit 7 is 1: 116 // AUXIO[8i+7] is driven high. 117 // 118 // When IOPOE bit 7 is 1: 119 // - If signal selected by 120 // IO7PSEL.SRC is 0: AUXIO[8i+7] is tri-stated or 121 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 122 // - If signal selected by 123 // IO7PSEL.SRC is 1: AUXIO[8i+7] is driven high. 124 // OPEN_DRAIN Open-Drain Mode: 125 // 126 // When IOPOE bit 7 is 0: 127 // - If GPIODOUT bit 7 is 0: 128 // AUXIO[8i+7] is driven low. 129 // - If GPIODOUT bit 7 is 1: 130 // AUXIO[8i+7] is tri-stated or pulled. This 131 // depends on IOC:IOCFGn.PULL_CTL. 132 // 133 // When IOPOE bit 7 is 1: 134 // - If signal selected by 135 // IO7PSEL.SRC is 0: AUXIO[8i+7] is driven low. 136 // - If signal selected by 137 // IO7PSEL.SRC is 1: AUXIO[8i+7] is tri-stated or 138 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 139 // IN Input Mode: 140 // 141 // When GPIODIE bit 7 is 0: 142 // AUXIO[8i+7] is enabled for analog signal 143 // transfer. 144 // 145 // When GPIODIE bit 7 is 1: 146 // AUXIO[8i+7] is enabled for digital input. 147 // OUT Output Mode: 148 // 149 // When IOPOE bit 7 is 0: 150 // GPIODOUT bit 7 drives AUXIO[8i+7]. 151 // 152 // When IOPOE bit 7 is 1: 153 // The signal selected by IO7PSEL.SRC drives 154 // AUXIO[8i+7]. 155 #define AUX_AIODIO_IOMODE_IO7_W 2 156 #define AUX_AIODIO_IOMODE_IO7_M 0x0000C000 157 #define AUX_AIODIO_IOMODE_IO7_S 14 158 #define AUX_AIODIO_IOMODE_IO7_OPEN_SOURCE 0x0000C000 159 #define AUX_AIODIO_IOMODE_IO7_OPEN_DRAIN 0x00008000 160 #define AUX_AIODIO_IOMODE_IO7_IN 0x00004000 161 #define AUX_AIODIO_IOMODE_IO7_OUT 0x00000000 162 163 // Field: [13:12] IO6 164 // 165 // Selects mode for AUXIO[8i+6]. 166 // ENUMs: 167 // OPEN_SOURCE Open-Source Mode: 168 // 169 // When IOPOE bit 6 is 0: 170 // - If GPIODOUT bit 6 is 0: 171 // AUXIO[8i+6] is tri-stated or pulled. This 172 // depends on IOC:IOCFGn.PULL_CTL. 173 // - If GPIODOUT bit 6 is 1: 174 // AUXIO[8i+6] is driven high. 175 // 176 // When IOPOE bit 6 is 1: 177 // - If signal selected by 178 // IO6PSEL.SRC is 0: AUXIO[8i+6] is tri-stated or 179 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 180 // - If signal selected by 181 // IO6PSEL.SRC is 1: AUXIO[8i+6] is driven high. 182 // OPEN_DRAIN Open-Drain Mode: 183 // 184 // When IOPOE bit 6 is 0: 185 // - If GPIODOUT bit 6 is 0: 186 // AUXIO[8i+6] is driven low. 187 // - If GPIODOUT bit 6 is 1: 188 // AUXIO[8i+6] is tri-stated or pulled. This 189 // depends on IOC:IOCFGn.PULL_CTL. 190 // 191 // When IOPOE bit 6 is 1: 192 // - If signal selected by 193 // IO6PSEL.SRC is 0: AUXIO[8i+6] is driven low. 194 // - If signal selected by 195 // IO6PSEL.SRC is 1: AUXIO[8i+6] is tri-stated or 196 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 197 // IN Input Mode: 198 // 199 // When GPIODIE bit 6 is 0: 200 // AUXIO[8i+6] is enabled for analog signal 201 // transfer. 202 // 203 // When GPIODIE bit 6 is 1: 204 // AUXIO[8i+6] is enabled for digital input. 205 // OUT Output Mode: 206 // 207 // When IOPOE bit 6 is 0: 208 // GPIODOUT bit 6 drives AUXIO[8i+6]. 209 // 210 // When IOPOE bit 6 is 1: 211 // The signal selected by IO6PSEL.SRC drives 212 // AUXIO[8i+6]. 213 #define AUX_AIODIO_IOMODE_IO6_W 2 214 #define AUX_AIODIO_IOMODE_IO6_M 0x00003000 215 #define AUX_AIODIO_IOMODE_IO6_S 12 216 #define AUX_AIODIO_IOMODE_IO6_OPEN_SOURCE 0x00003000 217 #define AUX_AIODIO_IOMODE_IO6_OPEN_DRAIN 0x00002000 218 #define AUX_AIODIO_IOMODE_IO6_IN 0x00001000 219 #define AUX_AIODIO_IOMODE_IO6_OUT 0x00000000 220 221 // Field: [11:10] IO5 222 // 223 // Selects mode for AUXIO[8i+5]. 224 // ENUMs: 225 // OPEN_SOURCE Open-Source Mode: 226 // 227 // When IOPOE bit 5 is 0: 228 // - If GPIODOUT bit 5 is 0: 229 // AUXIO[8i+5] is tri-stated or pulled. This 230 // depends on IOC:IOCFGn.PULL_CTL. 231 // - If GPIODOUT bit 5 is 1: 232 // AUXIO[8i+5] is driven high. 233 // 234 // When IOPOE bit 5 is 1: 235 // - If signal selected by 236 // IO5PSEL.SRC is 0: AUXIO[8i+5] is tri-stated or 237 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 238 // - If signal selected by 239 // IO5PSEL.SRC is 1: AUXIO[8i+5] is driven high. 240 // OPEN_DRAIN Open-Drain Mode: 241 // 242 // When IOPOE bit 5 is 0: 243 // - If GPIODOUT bit 5 is 0: 244 // AUXIO[8i+5] is driven low. 245 // - If GPIODOUT bit 5 is 1: 246 // AUXIO[8i+5] is tri-stated or pulled. This 247 // depends on IOC:IOCFGn.PULL_CTL. 248 // 249 // When IOPOE bit 5 is 1: 250 // - If signal selected by 251 // IO5PSEL.SRC is 0: AUXIO[8i+5] is driven low. 252 // - If signal selected by 253 // IO5PSEL.SRC is 1: AUXIO[8i+5] is tri-stated or 254 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 255 // IN Input Mode: 256 // 257 // When GPIODIE bit 5 is 0: 258 // AUXIO[8i+5] is enabled for analog signal 259 // transfer. 260 // 261 // When GPIODIE bit 5 is 1: 262 // AUXIO[8i+5] is enabled for digital input. 263 // OUT Output Mode: 264 // 265 // When IOPOE bit 5 is 0: 266 // GPIODOUT bit 5 drives AUXIO[8i+5]. 267 // 268 // When IOPOE bit 5 is 1: 269 // The signal selected by IO5PSEL.SRC drives 270 // AUXIO[8i+5]. 271 #define AUX_AIODIO_IOMODE_IO5_W 2 272 #define AUX_AIODIO_IOMODE_IO5_M 0x00000C00 273 #define AUX_AIODIO_IOMODE_IO5_S 10 274 #define AUX_AIODIO_IOMODE_IO5_OPEN_SOURCE 0x00000C00 275 #define AUX_AIODIO_IOMODE_IO5_OPEN_DRAIN 0x00000800 276 #define AUX_AIODIO_IOMODE_IO5_IN 0x00000400 277 #define AUX_AIODIO_IOMODE_IO5_OUT 0x00000000 278 279 // Field: [9:8] IO4 280 // 281 // Selects mode for AUXIO[8i+4]. 282 // ENUMs: 283 // OPEN_SOURCE Open-Source Mode: 284 // 285 // When IOPOE bit 4 is 0: 286 // - If GPIODOUT bit 4 is 0: 287 // AUXIO[8i+4] is tri-stated or pulled. This 288 // depends on IOC:IOCFGn.PULL_CTL. 289 // - If GPIODOUT bit 4 is 1: 290 // AUXIO[8i+4] is driven high. 291 // 292 // When IOPOE bit 4 is 1: 293 // - If signal selected by 294 // IO4PSEL.SRC is 0: AUXIO[8i+4] is tri-stated or 295 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 296 // - If signal selected by 297 // IO4PSEL.SRC is 1: AUXIO[8i+4] is driven high. 298 // OPEN_DRAIN Open-Drain Mode: 299 // 300 // When IOPOE bit 4 is 0: 301 // - If GPIODOUT bit 4 is 0: 302 // AUXIO[8i+4] is driven low. 303 // - If GPIODOUT bit 4 is 1: 304 // AUXIO[8i+4] is tri-stated or pulled. This 305 // depends on IOC:IOCFGn.PULL_CTL. 306 // 307 // When IOPOE bit 4 is 1: 308 // - If signal selected by 309 // IO4PSEL.SRC is 0: AUXIO[8i+4] is driven low. 310 // - If signal selected by 311 // IO4PSEL.SRC is 1: AUXIO[8i+4] is tri-stated or 312 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 313 // IN Input Mode: 314 // 315 // When GPIODIE bit 4 is 0: 316 // AUXIO[8i+4] is enabled for analog signal 317 // transfer. 318 // 319 // When GPIODIE bit 4 is 1: 320 // AUXIO[8i+4] is enabled for digital input. 321 // OUT Output Mode: 322 // 323 // When IOPOE bit 4 is 0: 324 // GPIODOUT bit 4 drives AUXIO[8i+4]. 325 // 326 // When IOPOE bit 4 is 1: 327 // The signal selected by IO4PSEL.SRC drives 328 // AUXIO[8i+4]. 329 #define AUX_AIODIO_IOMODE_IO4_W 2 330 #define AUX_AIODIO_IOMODE_IO4_M 0x00000300 331 #define AUX_AIODIO_IOMODE_IO4_S 8 332 #define AUX_AIODIO_IOMODE_IO4_OPEN_SOURCE 0x00000300 333 #define AUX_AIODIO_IOMODE_IO4_OPEN_DRAIN 0x00000200 334 #define AUX_AIODIO_IOMODE_IO4_IN 0x00000100 335 #define AUX_AIODIO_IOMODE_IO4_OUT 0x00000000 336 337 // Field: [7:6] IO3 338 // 339 // Selects mode for AUXIO[8i+3]. 340 // ENUMs: 341 // OPEN_SOURCE Open-Source Mode: 342 // 343 // When IOPOE bit 3 is 0: 344 // - If GPIODOUT bit 3 is 0: 345 // AUXIO[8i+3] is tri-stated or pulled. This 346 // depends on IOC:IOCFGn.PULL_CTL. 347 // - If GPIODOUT bit 3 is 1: 348 // AUXIO[8i+3] is driven high. 349 // 350 // When IOPOE bit 3 is 1: 351 // - If signal selected by 352 // IO3PSEL.SRC is 0: AUXIO[8i+3] is tri-stated or 353 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 354 // - If signal selected by 355 // IO3PSEL.SRC is 1: AUXIO[8i+3] is driven high. 356 // OPEN_DRAIN Open-Drain Mode: 357 // 358 // When IOPOE bit 3 is 0: 359 // - If GPIODOUT bit 3 is 0: 360 // AUXIO[8i+3] is driven low. 361 // - If GPIODOUT bit 3 is 1: 362 // AUXIO[8i+3] is tri-stated or pulled. This 363 // depends on IOC:IOCFGn.PULL_CTL. 364 // 365 // When IOPOE bit 3 is 1: 366 // - If signal selected by 367 // IO3PSEL.SRC is 0: AUXIO[8i+3] is driven low. 368 // - If signal selected by 369 // IO3PSEL.SRC is 1: AUXIO[8i+3] is tri-stated or 370 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 371 // IN Input Mode: 372 // 373 // When GPIODIE bit 3 is 0: 374 // AUXIO[8i+3] is enabled for analog signal 375 // transfer. 376 // 377 // When GPIODIE bit 3 is 1: 378 // AUXIO[8i+3] is enabled for digital input. 379 // OUT Output Mode: 380 // 381 // When IOPOE bit 3 is 0: 382 // GPIODOUT bit 3 drives AUXIO[8i+3]. 383 // 384 // When IOPOE bit 3 is 1: 385 // The signal selected by IO3PSEL.SRC drives 386 // AUXIO[8i+3]. 387 #define AUX_AIODIO_IOMODE_IO3_W 2 388 #define AUX_AIODIO_IOMODE_IO3_M 0x000000C0 389 #define AUX_AIODIO_IOMODE_IO3_S 6 390 #define AUX_AIODIO_IOMODE_IO3_OPEN_SOURCE 0x000000C0 391 #define AUX_AIODIO_IOMODE_IO3_OPEN_DRAIN 0x00000080 392 #define AUX_AIODIO_IOMODE_IO3_IN 0x00000040 393 #define AUX_AIODIO_IOMODE_IO3_OUT 0x00000000 394 395 // Field: [5:4] IO2 396 // 397 // Select mode for AUXIO[8i+2]. 398 // ENUMs: 399 // OPEN_SOURCE Open-Source Mode: 400 // 401 // When IOPOE bit 2 is 0: 402 // - If GPIODOUT bit 2 is 0: 403 // AUXIO[8i+2] is tri-stated or pulled. This 404 // depends on IOC:IOCFGn.PULL_CTL. 405 // - If GPIODOUT bit 2 is 1: 406 // AUXIO[8i+2] is driven high. 407 // 408 // When IOPOE bit 2 is 1: 409 // - If signal selected by 410 // IO2PSEL.SRC is 0: AUXIO[8i+2] is tri-stated or 411 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 412 // - If signal selected by 413 // IO2PSEL.SRC is 1: AUXIO[8i+2] is driven high. 414 // OPEN_DRAIN Open-Drain Mode: 415 // 416 // When IOPOE bit 2 is 0: 417 // - If GPIODOUT bit 2 is 0: 418 // AUXIO[8i+2] is driven low. 419 // - If GPIODOUT bit 2 is 1: 420 // AUXIO[8i+2] is tri-stated or pulled. This 421 // depends on IOC:IOCFGn.PULL_CTL. 422 // 423 // When IOPOE bit 2 is 1: 424 // - If signal selected by 425 // IO2PSEL.SRC is 0: AUXIO[8i+2] is driven low. 426 // - If signal selected by 427 // IO2PSEL.SRC is 1: AUXIO[8i+2] is tri-stated or 428 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 429 // IN Input Mode: 430 // 431 // When GPIODIE bit 2 is 0: 432 // AUXIO[8i+2] is enabled for analog signal 433 // transfer. 434 // 435 // When GPIODIE bit 2 is 1: 436 // AUXIO[8i+2] is enabled for digital input. 437 // OUT Output Mode: 438 // 439 // When IOPOE bit 2 is 0: 440 // GPIODOUT bit 2 drives AUXIO[8i+2]. 441 // 442 // When IOPOE bit 2 is 1: 443 // The signal selected by IO2PSEL.SRC drives 444 // AUXIO[8i+2]. 445 #define AUX_AIODIO_IOMODE_IO2_W 2 446 #define AUX_AIODIO_IOMODE_IO2_M 0x00000030 447 #define AUX_AIODIO_IOMODE_IO2_S 4 448 #define AUX_AIODIO_IOMODE_IO2_OPEN_SOURCE 0x00000030 449 #define AUX_AIODIO_IOMODE_IO2_OPEN_DRAIN 0x00000020 450 #define AUX_AIODIO_IOMODE_IO2_IN 0x00000010 451 #define AUX_AIODIO_IOMODE_IO2_OUT 0x00000000 452 453 // Field: [3:2] IO1 454 // 455 // Select mode for AUXIO[8i+1]. 456 // ENUMs: 457 // OPEN_SOURCE Open-Source Mode: 458 // 459 // When IOPOE bit 1 is 0: 460 // - If GPIODOUT bit 1 is 0: 461 // AUXIO[8i+1] is tri-stated or pulled. This 462 // depends on IOC:IOCFGn.PULL_CTL. 463 // - If GPIODOUT bit 1 is 1: 464 // AUXIO[8i+1] is driven high. 465 // 466 // When IOPOE bit 1 is 1: 467 // - If signal selected by 468 // IO1PSEL.SRC is 0: AUXIO[8i+1] is tri-stated or 469 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 470 // - If signal selected by 471 // IO1PSEL.SRC is 1: AUXIO[8i+1] is driven high. 472 // OPEN_DRAIN Open-Drain Mode: 473 // 474 // When IOPOE bit 1 is 0: 475 // - If GPIODOUT bit 1 is 0: 476 // AUXIO[8i+1] is driven low. 477 // - If GPIODOUT bit 1 is 1: 478 // AUXIO[8i+1] is tri-stated or pulled. This 479 // depends on IOC:IOCFGn.PULL_CTL. 480 // 481 // When IOPOE bit 1 is 1: 482 // - If signal selected by 483 // IO1PSEL.SRC is 0: AUXIO[8i+1] is driven low. 484 // - If signal selected by 485 // IO1PSEL.SRC is 1: AUXIO[8i+1] is tri-stated or 486 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 487 // IN Input Mode: 488 // 489 // When GPIODIE bit 1 is 0: 490 // AUXIO[8i+1] is enabled for analog signal 491 // transfer. 492 // 493 // When GPIODIE bit 1 is 1: 494 // AUXIO[8i+1] is enabled for digital input. 495 // OUT Output Mode: 496 // 497 // When IOPOE bit 1 is 0: 498 // GPIODOUT bit 1 drives AUXIO[8i+1]. 499 // 500 // When IOPOE bit 1 is 1: 501 // The signal selected by IO1PSEL.SRC drives 502 // AUXIO[8i+1]. 503 #define AUX_AIODIO_IOMODE_IO1_W 2 504 #define AUX_AIODIO_IOMODE_IO1_M 0x0000000C 505 #define AUX_AIODIO_IOMODE_IO1_S 2 506 #define AUX_AIODIO_IOMODE_IO1_OPEN_SOURCE 0x0000000C 507 #define AUX_AIODIO_IOMODE_IO1_OPEN_DRAIN 0x00000008 508 #define AUX_AIODIO_IOMODE_IO1_IN 0x00000004 509 #define AUX_AIODIO_IOMODE_IO1_OUT 0x00000000 510 511 // Field: [1:0] IO0 512 // 513 // Select mode for AUXIO[8i+0]. 514 // ENUMs: 515 // OPEN_SOURCE Open-Source Mode: 516 // 517 // When IOPOE bit 0 is 0: 518 // - If GPIODOUT bit 0 is 0: 519 // AUXIO[8i+0] is tri-stated or pulled. This 520 // depends on IOC:IOCFGn.PULL_CTL. 521 // - If GPIODOUT bit 0 is 1: 522 // AUXIO[8i+0] is driven high. 523 // 524 // When IOPOE bit 0 is 1: 525 // - If signal selected by 526 // IO0PSEL.SRC is 0: AUXIO[8i+0] is tri-stated or 527 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 528 // - If signal selected by 529 // IO0PSEL.SRC is 1: AUXIO[8i+0] is driven high. 530 // OPEN_DRAIN Open-Drain Mode: 531 // 532 // When IOPOE bit 0 is 0: 533 // - If GPIODOUT bit 0 is 0: 534 // AUXIO[8i+0] is driven low. 535 // - If GPIODOUT bit 0 is 1: 536 // AUXIO[8i+0] is tri-stated or pulled. This 537 // depends on IOC:IOCFGn.PULL_CTL. 538 // 539 // When IOPOE bit 0 is 1: 540 // - If signal selected by 541 // IO0PSEL.SRC is 0: AUXIO[8i+0] is driven low. 542 // - If signal selected by 543 // IO0PSEL.SRC is 1: AUXIO[8i+0] is tri-stated or 544 // pulled. This depends on IOC:IOCFGn.PULL_CTL. 545 // IN Input Mode: 546 // 547 // When GPIODIE bit 0 is 0: 548 // AUXIO[8i+0] is enabled for analog signal 549 // transfer. 550 // 551 // When GPIODIE bit 0 is 1: 552 // AUXIO[8i+0] is enabled for digital input. 553 // OUT Output Mode: 554 // 555 // When IOPOE bit 0 is 0: 556 // GPIODOUT bit 0 drives AUXIO[8i+0]. 557 // 558 // When IOPOE bit 0 is 1: 559 // The signal selected by IO0PSEL.SRC drives 560 // AUXIO[8i+0]. 561 #define AUX_AIODIO_IOMODE_IO0_W 2 562 #define AUX_AIODIO_IOMODE_IO0_M 0x00000003 563 #define AUX_AIODIO_IOMODE_IO0_S 0 564 #define AUX_AIODIO_IOMODE_IO0_OPEN_SOURCE 0x00000003 565 #define AUX_AIODIO_IOMODE_IO0_OPEN_DRAIN 0x00000002 566 #define AUX_AIODIO_IOMODE_IO0_IN 0x00000001 567 #define AUX_AIODIO_IOMODE_IO0_OUT 0x00000000 568 569 //***************************************************************************** 570 // 571 // Register: AUX_AIODIO_O_GPIODIE 572 // 573 //***************************************************************************** 574 // Field: [7:0] IO7_0 575 // 576 // Write 1 to bit index n in this bit vector to enable digital input buffer for 577 // AUXIO[8i+n]. 578 // Write 0 to bit index n in this bit vector to disable digital input buffer 579 // for AUXIO[8i+n]. 580 // 581 // You must enable the digital input buffer for AUXIO[8i+n] to read the pin 582 // value in GPIODIN. 583 // You must disable the digital input buffer for analog input or pins that 584 // float to avoid current leakage. 585 #define AUX_AIODIO_GPIODIE_IO7_0_W 8 586 #define AUX_AIODIO_GPIODIE_IO7_0_M 0x000000FF 587 #define AUX_AIODIO_GPIODIE_IO7_0_S 0 588 589 //***************************************************************************** 590 // 591 // Register: AUX_AIODIO_O_IOPOE 592 // 593 //***************************************************************************** 594 // Field: [7:0] IO7_0 595 // 596 // Write 1 to bit index n in this bit vector to configure AUXIO[8i+n] to be 597 // driven from source given in [IOnPSEL.*]. 598 // Write 0 to bit index n in this bit vector to configure AUXIO[8i+n] to be 599 // driven from bit n in GPIODOUT. 600 #define AUX_AIODIO_IOPOE_IO7_0_W 8 601 #define AUX_AIODIO_IOPOE_IO7_0_M 0x000000FF 602 #define AUX_AIODIO_IOPOE_IO7_0_S 0 603 604 //***************************************************************************** 605 // 606 // Register: AUX_AIODIO_O_GPIODOUT 607 // 608 //***************************************************************************** 609 // Field: [7:0] IO7_0 610 // 611 // Write 1 to bit index n in this bit vector to set AUXIO[8i+n]. 612 // Write 0 to bit index n in this bit vector to clear AUXIO[8i+n]. 613 // 614 // You must clear bit n in IOPOE to connect bit n in this bit vector to 615 // AUXIO[8i+n]. 616 #define AUX_AIODIO_GPIODOUT_IO7_0_W 8 617 #define AUX_AIODIO_GPIODOUT_IO7_0_M 0x000000FF 618 #define AUX_AIODIO_GPIODOUT_IO7_0_S 0 619 620 //***************************************************************************** 621 // 622 // Register: AUX_AIODIO_O_GPIODIN 623 // 624 //***************************************************************************** 625 // Field: [7:0] IO7_0 626 // 627 // Bit n in this bit vector contains the value for AUXIO[8i+n] when GPIODIE bit 628 // n is set. Otherwise, bit n is read as 0. 629 #define AUX_AIODIO_GPIODIN_IO7_0_W 8 630 #define AUX_AIODIO_GPIODIN_IO7_0_M 0x000000FF 631 #define AUX_AIODIO_GPIODIN_IO7_0_S 0 632 633 //***************************************************************************** 634 // 635 // Register: AUX_AIODIO_O_GPIODOUTSET 636 // 637 //***************************************************************************** 638 // Field: [7:0] IO7_0 639 // 640 // Write 1 to bit index n in this bit vector to set GPIODOUT bit n. 641 // 642 // Read value is 0. 643 #define AUX_AIODIO_GPIODOUTSET_IO7_0_W 8 644 #define AUX_AIODIO_GPIODOUTSET_IO7_0_M 0x000000FF 645 #define AUX_AIODIO_GPIODOUTSET_IO7_0_S 0 646 647 //***************************************************************************** 648 // 649 // Register: AUX_AIODIO_O_GPIODOUTCLR 650 // 651 //***************************************************************************** 652 // Field: [7:0] IO7_0 653 // 654 // Write 1 to bit index n in this bit vector to clear GPIODOUT bit n. 655 // 656 // Read value is 0. 657 #define AUX_AIODIO_GPIODOUTCLR_IO7_0_W 8 658 #define AUX_AIODIO_GPIODOUTCLR_IO7_0_M 0x000000FF 659 #define AUX_AIODIO_GPIODOUTCLR_IO7_0_S 0 660 661 //***************************************************************************** 662 // 663 // Register: AUX_AIODIO_O_GPIODOUTTGL 664 // 665 //***************************************************************************** 666 // Field: [7:0] IO7_0 667 // 668 // Write 1 to bit index n in this bit vector to toggle GPIODOUT bit n. 669 // 670 // Read value is 0. 671 #define AUX_AIODIO_GPIODOUTTGL_IO7_0_W 8 672 #define AUX_AIODIO_GPIODOUTTGL_IO7_0_M 0x000000FF 673 #define AUX_AIODIO_GPIODOUTTGL_IO7_0_S 0 674 675 //***************************************************************************** 676 // 677 // Register: AUX_AIODIO_O_IO0PSEL 678 // 679 //***************************************************************************** 680 // Field: [2:0] SRC 681 // 682 // Select a peripheral signal that connects to AUXIO[8i+0] when IOPOE bit 0 is 683 // set. 684 // ENUMs: 685 // AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version 686 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. 687 // AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version 688 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 689 // AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version 690 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 691 // AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version 692 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 693 // AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version 694 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 695 // AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. 696 // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. 697 // AUX_EV_OBS Peripheral output mux selects event selected by 698 // AUX_EVCTL:EVOBSCFG 699 #define AUX_AIODIO_IO0PSEL_SRC_W 3 700 #define AUX_AIODIO_IO0PSEL_SRC_M 0x00000007 701 #define AUX_AIODIO_IO0PSEL_SRC_S 0 702 #define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 703 #define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV3 0x00000006 704 #define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV2 0x00000005 705 #define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV1 0x00000004 706 #define AUX_AIODIO_IO0PSEL_SRC_AUX_TIMER2_EV0 0x00000003 707 #define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_MOSI 0x00000002 708 #define AUX_AIODIO_IO0PSEL_SRC_AUX_SPIM_SCLK 0x00000001 709 #define AUX_AIODIO_IO0PSEL_SRC_AUX_EV_OBS 0x00000000 710 711 //***************************************************************************** 712 // 713 // Register: AUX_AIODIO_O_IO1PSEL 714 // 715 //***************************************************************************** 716 // Field: [2:0] SRC 717 // 718 // Select a peripheral signal that connects to AUXIO[8i+1] when IOPOE bit 1 is 719 // set. 720 // ENUMs: 721 // AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version 722 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. 723 // AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version 724 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 725 // AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version 726 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 727 // AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version 728 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 729 // AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version 730 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 731 // AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. 732 // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. 733 // AUX_EV_OBS Peripheral output mux selects event selected by 734 // AUX_EVCTL:EVOBSCFG 735 #define AUX_AIODIO_IO1PSEL_SRC_W 3 736 #define AUX_AIODIO_IO1PSEL_SRC_M 0x00000007 737 #define AUX_AIODIO_IO1PSEL_SRC_S 0 738 #define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 739 #define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV3 0x00000006 740 #define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV2 0x00000005 741 #define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV1 0x00000004 742 #define AUX_AIODIO_IO1PSEL_SRC_AUX_TIMER2_EV0 0x00000003 743 #define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_MOSI 0x00000002 744 #define AUX_AIODIO_IO1PSEL_SRC_AUX_SPIM_SCLK 0x00000001 745 #define AUX_AIODIO_IO1PSEL_SRC_AUX_EV_OBS 0x00000000 746 747 //***************************************************************************** 748 // 749 // Register: AUX_AIODIO_O_IO2PSEL 750 // 751 //***************************************************************************** 752 // Field: [2:0] SRC 753 // 754 // Select a peripheral signal that connects to AUXIO[8i+2] when IOPOE bit 2 is 755 // set. 756 // ENUMs: 757 // AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version 758 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. 759 // AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version 760 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 761 // AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version 762 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 763 // AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version 764 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 765 // AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version 766 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 767 // AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. 768 // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. 769 // AUX_EV_OBS Peripheral output mux selects event selected by 770 // AUX_EVCTL:EVOBSCFG 771 #define AUX_AIODIO_IO2PSEL_SRC_W 3 772 #define AUX_AIODIO_IO2PSEL_SRC_M 0x00000007 773 #define AUX_AIODIO_IO2PSEL_SRC_S 0 774 #define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 775 #define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV3 0x00000006 776 #define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV2 0x00000005 777 #define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV1 0x00000004 778 #define AUX_AIODIO_IO2PSEL_SRC_AUX_TIMER2_EV0 0x00000003 779 #define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_MOSI 0x00000002 780 #define AUX_AIODIO_IO2PSEL_SRC_AUX_SPIM_SCLK 0x00000001 781 #define AUX_AIODIO_IO2PSEL_SRC_AUX_EV_OBS 0x00000000 782 783 //***************************************************************************** 784 // 785 // Register: AUX_AIODIO_O_IO3PSEL 786 // 787 //***************************************************************************** 788 // Field: [2:0] SRC 789 // 790 // Select a peripheral signal that connects to AUXIO[8i+3] when IOPOE bit 3 is 791 // set. 792 // ENUMs: 793 // AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version 794 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. 795 // AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version 796 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 797 // AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version 798 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 799 // AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version 800 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 801 // AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version 802 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 803 // AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. 804 // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. 805 // AUX_EV_OBS Peripheral output mux selects event selected by 806 // AUX_EVCTL:EVOBSCFG 807 #define AUX_AIODIO_IO3PSEL_SRC_W 3 808 #define AUX_AIODIO_IO3PSEL_SRC_M 0x00000007 809 #define AUX_AIODIO_IO3PSEL_SRC_S 0 810 #define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 811 #define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV3 0x00000006 812 #define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV2 0x00000005 813 #define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV1 0x00000004 814 #define AUX_AIODIO_IO3PSEL_SRC_AUX_TIMER2_EV0 0x00000003 815 #define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_MOSI 0x00000002 816 #define AUX_AIODIO_IO3PSEL_SRC_AUX_SPIM_SCLK 0x00000001 817 #define AUX_AIODIO_IO3PSEL_SRC_AUX_EV_OBS 0x00000000 818 819 //***************************************************************************** 820 // 821 // Register: AUX_AIODIO_O_IO4PSEL 822 // 823 //***************************************************************************** 824 // Field: [2:0] SRC 825 // 826 // Select a peripheral signal that connects to AUXIO[8i+4] when IOPOE bit 4 is 827 // set. 828 // ENUMs: 829 // AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version 830 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. 831 // AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version 832 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 833 // AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version 834 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 835 // AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version 836 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 837 // AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version 838 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 839 // AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. 840 // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. 841 // AUX_EV_OBS Peripheral output mux selects event selected by 842 // AUX_EVCTL:EVOBSCFG 843 #define AUX_AIODIO_IO4PSEL_SRC_W 3 844 #define AUX_AIODIO_IO4PSEL_SRC_M 0x00000007 845 #define AUX_AIODIO_IO4PSEL_SRC_S 0 846 #define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 847 #define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV3 0x00000006 848 #define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV2 0x00000005 849 #define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV1 0x00000004 850 #define AUX_AIODIO_IO4PSEL_SRC_AUX_TIMER2_EV0 0x00000003 851 #define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_MOSI 0x00000002 852 #define AUX_AIODIO_IO4PSEL_SRC_AUX_SPIM_SCLK 0x00000001 853 #define AUX_AIODIO_IO4PSEL_SRC_AUX_EV_OBS 0x00000000 854 855 //***************************************************************************** 856 // 857 // Register: AUX_AIODIO_O_IO5PSEL 858 // 859 //***************************************************************************** 860 // Field: [2:0] SRC 861 // 862 // Select a peripheral signal that connects to AUXIO[8i+5] when IOPOE bit 5 is 863 // set. 864 // ENUMs: 865 // AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version 866 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. 867 // AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version 868 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 869 // AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version 870 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 871 // AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version 872 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 873 // AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version 874 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 875 // AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. 876 // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. 877 // AUX_EV_OBS Peripheral output mux selects event selected by 878 // AUX_EVCTL:EVOBSCFG 879 #define AUX_AIODIO_IO5PSEL_SRC_W 3 880 #define AUX_AIODIO_IO5PSEL_SRC_M 0x00000007 881 #define AUX_AIODIO_IO5PSEL_SRC_S 0 882 #define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 883 #define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV3 0x00000006 884 #define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV2 0x00000005 885 #define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV1 0x00000004 886 #define AUX_AIODIO_IO5PSEL_SRC_AUX_TIMER2_EV0 0x00000003 887 #define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_MOSI 0x00000002 888 #define AUX_AIODIO_IO5PSEL_SRC_AUX_SPIM_SCLK 0x00000001 889 #define AUX_AIODIO_IO5PSEL_SRC_AUX_EV_OBS 0x00000000 890 891 //***************************************************************************** 892 // 893 // Register: AUX_AIODIO_O_IO6PSEL 894 // 895 //***************************************************************************** 896 // Field: [2:0] SRC 897 // 898 // Select a peripheral signal that connects to AUXIO[8i+6] when IOPOE bit 6 is 899 // set. 900 // ENUMs: 901 // AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version 902 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. 903 // AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version 904 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 905 // AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version 906 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 907 // AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version 908 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 909 // AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version 910 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 911 // AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. 912 // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. 913 // AUX_EV_OBS Peripheral output mux selects event selected by 914 // AUX_EVCTL:EVOBSCFG 915 #define AUX_AIODIO_IO6PSEL_SRC_W 3 916 #define AUX_AIODIO_IO6PSEL_SRC_M 0x00000007 917 #define AUX_AIODIO_IO6PSEL_SRC_S 0 918 #define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 919 #define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV3 0x00000006 920 #define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV2 0x00000005 921 #define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV1 0x00000004 922 #define AUX_AIODIO_IO6PSEL_SRC_AUX_TIMER2_EV0 0x00000003 923 #define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_MOSI 0x00000002 924 #define AUX_AIODIO_IO6PSEL_SRC_AUX_SPIM_SCLK 0x00000001 925 #define AUX_AIODIO_IO6PSEL_SRC_AUX_EV_OBS 0x00000000 926 927 //***************************************************************************** 928 // 929 // Register: AUX_AIODIO_O_IO7PSEL 930 // 931 //***************************************************************************** 932 // Field: [2:0] SRC 933 // 934 // Select a peripheral signal that connects to AUXIO[8i+7] when IOPOE bit 7 is 935 // set. 936 // ENUMs: 937 // AUX_TIMER2_PULSE Peripheral output mux selects asynchronous version 938 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_PULSE. 939 // AUX_TIMER2_EV3 Peripheral output mux selects asynchronous version 940 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV3. 941 // AUX_TIMER2_EV2 Peripheral output mux selects asynchronous version 942 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV2. 943 // AUX_TIMER2_EV1 Peripheral output mux selects asynchronous version 944 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV1. 945 // AUX_TIMER2_EV0 Peripheral output mux selects asynchronous version 946 // of AUX_EVCTL:EVSTAT3.AUX_TIMER2_EV0. 947 // AUX_SPIM_MOSI Peripheral output mux selects AUX_SPIM MOSI. 948 // AUX_SPIM_SCLK Peripheral output mux selects AUX_SPIM SCLK. 949 // AUX_EV_OBS Peripheral output mux selects event selected by 950 // AUX_EVCTL:EVOBSCFG 951 #define AUX_AIODIO_IO7PSEL_SRC_W 3 952 #define AUX_AIODIO_IO7PSEL_SRC_M 0x00000007 953 #define AUX_AIODIO_IO7PSEL_SRC_S 0 954 #define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_PULSE 0x00000007 955 #define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV3 0x00000006 956 #define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV2 0x00000005 957 #define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV1 0x00000004 958 #define AUX_AIODIO_IO7PSEL_SRC_AUX_TIMER2_EV0 0x00000003 959 #define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_MOSI 0x00000002 960 #define AUX_AIODIO_IO7PSEL_SRC_AUX_SPIM_SCLK 0x00000001 961 #define AUX_AIODIO_IO7PSEL_SRC_AUX_EV_OBS 0x00000000 962 963 //***************************************************************************** 964 // 965 // Register: AUX_AIODIO_O_IOMODEL 966 // 967 //***************************************************************************** 968 // Field: [7:6] IO3 969 // 970 // See IOMODE.IO3. 971 #define AUX_AIODIO_IOMODEL_IO3_W 2 972 #define AUX_AIODIO_IOMODEL_IO3_M 0x000000C0 973 #define AUX_AIODIO_IOMODEL_IO3_S 6 974 975 // Field: [5:4] IO2 976 // 977 // See IOMODE.IO2. 978 #define AUX_AIODIO_IOMODEL_IO2_W 2 979 #define AUX_AIODIO_IOMODEL_IO2_M 0x00000030 980 #define AUX_AIODIO_IOMODEL_IO2_S 4 981 982 // Field: [3:2] IO1 983 // 984 // See IOMODE.IO1. 985 #define AUX_AIODIO_IOMODEL_IO1_W 2 986 #define AUX_AIODIO_IOMODEL_IO1_M 0x0000000C 987 #define AUX_AIODIO_IOMODEL_IO1_S 2 988 989 // Field: [1:0] IO0 990 // 991 // See IOMODE.IO0. 992 #define AUX_AIODIO_IOMODEL_IO0_W 2 993 #define AUX_AIODIO_IOMODEL_IO0_M 0x00000003 994 #define AUX_AIODIO_IOMODEL_IO0_S 0 995 996 //***************************************************************************** 997 // 998 // Register: AUX_AIODIO_O_IOMODEH 999 // 1000 //***************************************************************************** 1001 // Field: [7:6] IO7 1002 // 1003 // See IOMODE.IO7. 1004 #define AUX_AIODIO_IOMODEH_IO7_W 2 1005 #define AUX_AIODIO_IOMODEH_IO7_M 0x000000C0 1006 #define AUX_AIODIO_IOMODEH_IO7_S 6 1007 1008 // Field: [5:4] IO6 1009 // 1010 // See IOMODE.IO6. 1011 #define AUX_AIODIO_IOMODEH_IO6_W 2 1012 #define AUX_AIODIO_IOMODEH_IO6_M 0x00000030 1013 #define AUX_AIODIO_IOMODEH_IO6_S 4 1014 1015 // Field: [3:2] IO5 1016 // 1017 // See IOMODE.IO5. 1018 #define AUX_AIODIO_IOMODEH_IO5_W 2 1019 #define AUX_AIODIO_IOMODEH_IO5_M 0x0000000C 1020 #define AUX_AIODIO_IOMODEH_IO5_S 2 1021 1022 // Field: [1:0] IO4 1023 // 1024 // See IOMODE.IO4. 1025 #define AUX_AIODIO_IOMODEH_IO4_W 2 1026 #define AUX_AIODIO_IOMODEH_IO4_M 0x00000003 1027 #define AUX_AIODIO_IOMODEH_IO4_S 0 1028 1029 1030 #endif // __AUX_AIODIO__ 1031
