1 /****************************************************************************** 2 * Filename: hw_aon_pmctl_h 3 * Revised: $Date$ 4 * Revision: $Revision$ 5 * 6 * Copyright (c) 2015 - 2017, Texas Instruments Incorporated 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions are met: 11 * 12 * 1) Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2) Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 20 * be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 ******************************************************************************/ 36 37 #ifndef __HW_AON_PMCTL_H__ 38 #define __HW_AON_PMCTL_H__ 39 40 //***************************************************************************** 41 // 42 // This section defines the register offsets of 43 // AON_PMCTL component 44 // 45 //***************************************************************************** 46 // AUX SCE Clock Management 47 #define AON_PMCTL_O_AUXSCECLK 0x00000004 48 49 // RAM Configuration 50 #define AON_PMCTL_O_RAMCFG 0x00000008 51 52 // Power Management Control 53 #define AON_PMCTL_O_PWRCTL 0x00000010 54 55 // AON Power and Reset Status 56 #define AON_PMCTL_O_PWRSTAT 0x00000014 57 58 // Shutdown Control 59 #define AON_PMCTL_O_SHUTDOWN 0x00000018 60 61 // Recharge Controller Configuration 62 #define AON_PMCTL_O_RECHARGECFG 0x0000001C 63 64 // Recharge Controller Status 65 #define AON_PMCTL_O_RECHARGESTAT 0x00000020 66 67 // Oscillator Configuration 68 #define AON_PMCTL_O_OSCCFG 0x00000024 69 70 // Reset Management 71 #define AON_PMCTL_O_RESETCTL 0x00000028 72 73 // Sleep Control 74 #define AON_PMCTL_O_SLEEPCTL 0x0000002C 75 76 // JTAG Configuration 77 #define AON_PMCTL_O_JTAGCFG 0x00000034 78 79 // JTAG USERCODE 80 #define AON_PMCTL_O_JTAGUSERCODE 0x0000003C 81 82 //***************************************************************************** 83 // 84 // Register: AON_PMCTL_O_AUXSCECLK 85 // 86 //***************************************************************************** 87 // Field: [8] PD_SRC 88 // 89 // Selects the clock source for the AUX domain when AUX is in powerdown mode. 90 // Note: Switching the clock source is guaranteed to be glitch-free 91 // ENUMs: 92 // SCLK_LF LF clock (SCLK_LF ) 93 // NO_CLOCK No clock 94 #define AON_PMCTL_AUXSCECLK_PD_SRC 0x00000100 95 #define AON_PMCTL_AUXSCECLK_PD_SRC_BITN 8 96 #define AON_PMCTL_AUXSCECLK_PD_SRC_M 0x00000100 97 #define AON_PMCTL_AUXSCECLK_PD_SRC_S 8 98 #define AON_PMCTL_AUXSCECLK_PD_SRC_SCLK_LF 0x00000100 99 #define AON_PMCTL_AUXSCECLK_PD_SRC_NO_CLOCK 0x00000000 100 101 // Field: [0] SRC 102 // 103 // Selects the clock source for the AUX domain when AUX is in active mode. 104 // Note: Switching the clock source is guaranteed to be glitch-free 105 // ENUMs: 106 // SCLK_MF MF Clock (SCLK_MF) 107 // SCLK_HFDIV2 HF Clock divided by 2 (SCLK_HFDIV2) 108 #define AON_PMCTL_AUXSCECLK_SRC 0x00000001 109 #define AON_PMCTL_AUXSCECLK_SRC_BITN 0 110 #define AON_PMCTL_AUXSCECLK_SRC_M 0x00000001 111 #define AON_PMCTL_AUXSCECLK_SRC_S 0 112 #define AON_PMCTL_AUXSCECLK_SRC_SCLK_MF 0x00000001 113 #define AON_PMCTL_AUXSCECLK_SRC_SCLK_HFDIV2 0x00000000 114 115 //***************************************************************************** 116 // 117 // Register: AON_PMCTL_O_RAMCFG 118 // 119 //***************************************************************************** 120 // Field: [17] AUX_SRAM_PWR_OFF 121 // 122 // Internal. Only to be used through TI provided API. 123 #define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF 0x00020000 124 #define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_BITN 17 125 #define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_M 0x00020000 126 #define AON_PMCTL_RAMCFG_AUX_SRAM_PWR_OFF_S 17 127 128 // Field: [16] AUX_SRAM_RET_EN 129 // 130 // Internal. Only to be used through TI provided API. 131 #define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN 0x00010000 132 #define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_BITN 16 133 #define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_M 0x00010000 134 #define AON_PMCTL_RAMCFG_AUX_SRAM_RET_EN_S 16 135 136 // Field: [3:0] BUS_SRAM_RET_EN 137 // 138 // MCU SRAM is partitioned into 5 banks . This register controls which of the 139 // banks that has retention during MCU Bus domain power off 140 // ENUMs: 141 // RET_FULL Retention on for all banks SRAM:BANK0, SRAM:BANK1 142 // ,SRAM:BANK2, SRAM:BANK3 and SRAM:BANK4 143 // RET_LEVEL3 Retention on for SRAM:BANK0, SRAM:BANK1 144 // ,SRAM:BANK2 and SRAM:BANK3 145 // RET_LEVEL2 Retention on for SRAM:BANK0, SRAM:BANK1 and 146 // SRAM:BANK2 147 // RET_NONE Retention is disabled 148 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_W 4 149 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_M 0x0000000F 150 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_S 0 151 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_FULL 0x0000000F 152 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL3 0x00000007 153 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_LEVEL2 0x00000003 154 #define AON_PMCTL_RAMCFG_BUS_SRAM_RET_EN_RET_NONE 0x00000000 155 156 //***************************************************************************** 157 // 158 // Register: AON_PMCTL_O_PWRCTL 159 // 160 //***************************************************************************** 161 // Field: [2] DCDC_ACTIVE 162 // 163 // Select to use DCDC regulator for VDDR in active mode 164 // 165 // 0: Use GLDO for regulation of VDDR in active mode. 166 // 1: Use DCDC for regulation of VDDR in active mode. 167 // 168 // DCDC_EN must also be set for DCDC to be used as regulator for VDDR in active 169 // mode 170 #define AON_PMCTL_PWRCTL_DCDC_ACTIVE 0x00000004 171 #define AON_PMCTL_PWRCTL_DCDC_ACTIVE_BITN 2 172 #define AON_PMCTL_PWRCTL_DCDC_ACTIVE_M 0x00000004 173 #define AON_PMCTL_PWRCTL_DCDC_ACTIVE_S 2 174 175 // Field: [1] EXT_REG_MODE 176 // 177 // Status of source for VDDRsupply: 178 // 179 // 0: DCDC or GLDO are generating VDDR 180 // 1: DCDC and GLDO are bypassed and an external regulator supplies VDDR 181 #define AON_PMCTL_PWRCTL_EXT_REG_MODE 0x00000002 182 #define AON_PMCTL_PWRCTL_EXT_REG_MODE_BITN 1 183 #define AON_PMCTL_PWRCTL_EXT_REG_MODE_M 0x00000002 184 #define AON_PMCTL_PWRCTL_EXT_REG_MODE_S 1 185 186 // Field: [0] DCDC_EN 187 // 188 // Select to use DCDC regulator during recharge of VDDR 189 // 190 // 0: Use GLDO for recharge of VDDR 191 // 1: Use DCDC for recharge of VDDR 192 // 193 // Note: This bitfield should be set to the same as DCDC_ACTIVE 194 #define AON_PMCTL_PWRCTL_DCDC_EN 0x00000001 195 #define AON_PMCTL_PWRCTL_DCDC_EN_BITN 0 196 #define AON_PMCTL_PWRCTL_DCDC_EN_M 0x00000001 197 #define AON_PMCTL_PWRCTL_DCDC_EN_S 0 198 199 //***************************************************************************** 200 // 201 // Register: AON_PMCTL_O_PWRSTAT 202 // 203 //***************************************************************************** 204 // Field: [2] JTAG_PD_ON 205 // 206 // Indicates JTAG power state: 207 // 208 // 0: JTAG is powered off 209 // 1: JTAG is powered on 210 #define AON_PMCTL_PWRSTAT_JTAG_PD_ON 0x00000004 211 #define AON_PMCTL_PWRSTAT_JTAG_PD_ON_BITN 2 212 #define AON_PMCTL_PWRSTAT_JTAG_PD_ON_M 0x00000004 213 #define AON_PMCTL_PWRSTAT_JTAG_PD_ON_S 2 214 215 // Field: [1] AUX_BUS_RESET_DONE 216 // 217 // Indicates Reset Done from AUX Bus: 218 // 219 // 0: AUX Bus is being reset 220 // 1: AUX Bus reset is released 221 #define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE 0x00000002 222 #define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_BITN 1 223 #define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_M 0x00000002 224 #define AON_PMCTL_PWRSTAT_AUX_BUS_RESET_DONE_S 1 225 226 // Field: [0] AUX_RESET_DONE 227 // 228 // Indicates Reset Done from AUX: 229 // 230 // 0: AUX is being reset 231 // 1: AUX reset is released 232 #define AON_PMCTL_PWRSTAT_AUX_RESET_DONE 0x00000001 233 #define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_BITN 0 234 #define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_M 0x00000001 235 #define AON_PMCTL_PWRSTAT_AUX_RESET_DONE_S 0 236 237 //***************************************************************************** 238 // 239 // Register: AON_PMCTL_O_SHUTDOWN 240 // 241 //***************************************************************************** 242 // Field: [0] EN 243 // 244 // Shutdown control. 245 // 246 // 0: Do not write 0 to this bit. 247 // 1: Immediately start the process to enter shutdown mode 248 #define AON_PMCTL_SHUTDOWN_EN 0x00000001 249 #define AON_PMCTL_SHUTDOWN_EN_BITN 0 250 #define AON_PMCTL_SHUTDOWN_EN_M 0x00000001 251 #define AON_PMCTL_SHUTDOWN_EN_S 0 252 253 //***************************************************************************** 254 // 255 // Register: AON_PMCTL_O_RECHARGECFG 256 // 257 //***************************************************************************** 258 // Field: [31:30] MODE 259 // 260 // Selects recharge algorithm for VDDR when the system is running on the uLDO 261 // ENUMs: 262 // COMPARATOR External recharge comparator. 263 // Note that the clock to 264 // the recharge comparator must be enabled, 265 // 266 // [ANATOP_MMAP:ADI_3_REFSYS:CTL_RECHARGE_CMP0:COMP_CLK_DISABLE], 267 // before selecting this recharge algorithm. 268 // ADAPTIVE Adaptive timer 269 // STATIC Static timer 270 // OFF Recharge disabled 271 #define AON_PMCTL_RECHARGECFG_MODE_W 2 272 #define AON_PMCTL_RECHARGECFG_MODE_M 0xC0000000 273 #define AON_PMCTL_RECHARGECFG_MODE_S 30 274 #define AON_PMCTL_RECHARGECFG_MODE_COMPARATOR 0xC0000000 275 #define AON_PMCTL_RECHARGECFG_MODE_ADAPTIVE 0x80000000 276 #define AON_PMCTL_RECHARGECFG_MODE_STATIC 0x40000000 277 #define AON_PMCTL_RECHARGECFG_MODE_OFF 0x00000000 278 279 // Field: [23:20] C2 280 // 281 // Internal. Only to be used through TI provided API. 282 #define AON_PMCTL_RECHARGECFG_C2_W 4 283 #define AON_PMCTL_RECHARGECFG_C2_M 0x00F00000 284 #define AON_PMCTL_RECHARGECFG_C2_S 20 285 286 // Field: [19:16] C1 287 // 288 // Internal. Only to be used through TI provided API. 289 #define AON_PMCTL_RECHARGECFG_C1_W 4 290 #define AON_PMCTL_RECHARGECFG_C1_M 0x000F0000 291 #define AON_PMCTL_RECHARGECFG_C1_S 16 292 293 // Field: [15:11] MAX_PER_M 294 // 295 // Internal. Only to be used through TI provided API. 296 #define AON_PMCTL_RECHARGECFG_MAX_PER_M_W 5 297 #define AON_PMCTL_RECHARGECFG_MAX_PER_M_M 0x0000F800 298 #define AON_PMCTL_RECHARGECFG_MAX_PER_M_S 11 299 300 // Field: [10:8] MAX_PER_E 301 // 302 // Internal. Only to be used through TI provided API. 303 #define AON_PMCTL_RECHARGECFG_MAX_PER_E_W 3 304 #define AON_PMCTL_RECHARGECFG_MAX_PER_E_M 0x00000700 305 #define AON_PMCTL_RECHARGECFG_MAX_PER_E_S 8 306 307 // Field: [7:3] PER_M 308 // 309 // Internal. Only to be used through TI provided API. 310 #define AON_PMCTL_RECHARGECFG_PER_M_W 5 311 #define AON_PMCTL_RECHARGECFG_PER_M_M 0x000000F8 312 #define AON_PMCTL_RECHARGECFG_PER_M_S 3 313 314 // Field: [2:0] PER_E 315 // 316 // Internal. Only to be used through TI provided API. 317 #define AON_PMCTL_RECHARGECFG_PER_E_W 3 318 #define AON_PMCTL_RECHARGECFG_PER_E_M 0x00000007 319 #define AON_PMCTL_RECHARGECFG_PER_E_S 0 320 321 //***************************************************************************** 322 // 323 // Register: AON_PMCTL_O_RECHARGESTAT 324 // 325 //***************************************************************************** 326 // Field: [19:16] VDDR_SMPLS 327 // 328 // The last 4 VDDR samples. 329 // 330 // For each bit: 331 // 0: VDDR was below VDDR_OK threshold when recharge started 332 // 1: VDDR was above VDDR_OK threshold when recharge started 333 // 334 // The register is updated prior to every recharge period with a shift left, 335 // and bit 0 is updated with the last VDDR sample. 336 #define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_W 4 337 #define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_M 0x000F0000 338 #define AON_PMCTL_RECHARGESTAT_VDDR_SMPLS_S 16 339 340 // Field: [15:0] MAX_USED_PER 341 // 342 // Shows the maximum number of 32kHz periods that have separated two recharge 343 // cycles and VDDR still was above VDDR_OK threshold when the latter recharge 344 // started. This register can be used as an indication of the leakage current 345 // during standby. 346 // 347 // This bitfield is cleared to 0 when writing this register. 348 #define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_W 16 349 #define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_M 0x0000FFFF 350 #define AON_PMCTL_RECHARGESTAT_MAX_USED_PER_S 0 351 352 //***************************************************************************** 353 // 354 // Register: AON_PMCTL_O_OSCCFG 355 // 356 //***************************************************************************** 357 // Field: [7:3] PER_M 358 // 359 // Internal. Only to be used through TI provided API. 360 #define AON_PMCTL_OSCCFG_PER_M_W 5 361 #define AON_PMCTL_OSCCFG_PER_M_M 0x000000F8 362 #define AON_PMCTL_OSCCFG_PER_M_S 3 363 364 // Field: [2:0] PER_E 365 // 366 // Internal. Only to be used through TI provided API. 367 #define AON_PMCTL_OSCCFG_PER_E_W 3 368 #define AON_PMCTL_OSCCFG_PER_E_M 0x00000007 369 #define AON_PMCTL_OSCCFG_PER_E_S 0 370 371 //***************************************************************************** 372 // 373 // Register: AON_PMCTL_O_RESETCTL 374 // 375 //***************************************************************************** 376 // Field: [31] SYSRESET 377 // 378 // Cold reset register. Writing 1 to this bitfield will reset the entire chip 379 // and cause boot code to run again. 380 // 381 // 0: No effect 382 // 1: Generate system reset. Appears as SYSRESET in RESET_SRC 383 #define AON_PMCTL_RESETCTL_SYSRESET 0x80000000 384 #define AON_PMCTL_RESETCTL_SYSRESET_BITN 31 385 #define AON_PMCTL_RESETCTL_SYSRESET_M 0x80000000 386 #define AON_PMCTL_RESETCTL_SYSRESET_S 31 387 388 // Field: [25] BOOT_DET_1_CLR 389 // 390 // Internal. Only to be used through TI provided API. 391 #define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR 0x02000000 392 #define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_BITN 25 393 #define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_M 0x02000000 394 #define AON_PMCTL_RESETCTL_BOOT_DET_1_CLR_S 25 395 396 // Field: [24] BOOT_DET_0_CLR 397 // 398 // Internal. Only to be used through TI provided API. 399 #define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR 0x01000000 400 #define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_BITN 24 401 #define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_M 0x01000000 402 #define AON_PMCTL_RESETCTL_BOOT_DET_0_CLR_S 24 403 404 // Field: [17] BOOT_DET_1_SET 405 // 406 // Internal. Only to be used through TI provided API. 407 #define AON_PMCTL_RESETCTL_BOOT_DET_1_SET 0x00020000 408 #define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_BITN 17 409 #define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_M 0x00020000 410 #define AON_PMCTL_RESETCTL_BOOT_DET_1_SET_S 17 411 412 // Field: [16] BOOT_DET_0_SET 413 // 414 // Internal. Only to be used through TI provided API. 415 #define AON_PMCTL_RESETCTL_BOOT_DET_0_SET 0x00010000 416 #define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_BITN 16 417 #define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_M 0x00010000 418 #define AON_PMCTL_RESETCTL_BOOT_DET_0_SET_S 16 419 420 // Field: [15] WU_FROM_SD 421 // 422 // A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from 423 // SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin 424 // being forced low) 425 // 426 // Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup 427 // sources. 428 // 429 // 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC 430 // 1: A wakeup has occurred from SHUTDOWN 431 // 432 // Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. 433 #define AON_PMCTL_RESETCTL_WU_FROM_SD 0x00008000 434 #define AON_PMCTL_RESETCTL_WU_FROM_SD_BITN 15 435 #define AON_PMCTL_RESETCTL_WU_FROM_SD_M 0x00008000 436 #define AON_PMCTL_RESETCTL_WU_FROM_SD_S 15 437 438 // Field: [14] GPIO_WU_FROM_SD 439 // 440 // A wakeup from SHUTDOWN on an IO event has occurred 441 // 442 // Please refer to IOC:IOCFGn.WU_CFG for configuring the IO's as wakeup 443 // sources. 444 // 445 // 0: The wakeup did not occur from SHUTDOWN on an IO event 446 // 1: A wakeup from SHUTDOWN occurred from an IO event 447 // 448 // The case where WU_FROM_SD is asserted but this bitfield is not asserted will 449 // only occur in a debug session. The boot code will not proceed with wakeup 450 // from SHUTDOWN procedure until this bitfield is asserted as well. 451 // 452 // Note: This flag will be cleared when SLEEPCTL.IO_PAD_SLEEP_DIS is asserted. 453 #define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD 0x00004000 454 #define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_BITN 14 455 #define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_M 0x00004000 456 #define AON_PMCTL_RESETCTL_GPIO_WU_FROM_SD_S 14 457 458 // Field: [13] BOOT_DET_1 459 // 460 // Internal. Only to be used through TI provided API. 461 #define AON_PMCTL_RESETCTL_BOOT_DET_1 0x00002000 462 #define AON_PMCTL_RESETCTL_BOOT_DET_1_BITN 13 463 #define AON_PMCTL_RESETCTL_BOOT_DET_1_M 0x00002000 464 #define AON_PMCTL_RESETCTL_BOOT_DET_1_S 13 465 466 // Field: [12] BOOT_DET_0 467 // 468 // Internal. Only to be used through TI provided API. 469 #define AON_PMCTL_RESETCTL_BOOT_DET_0 0x00001000 470 #define AON_PMCTL_RESETCTL_BOOT_DET_0_BITN 12 471 #define AON_PMCTL_RESETCTL_BOOT_DET_0_M 0x00001000 472 #define AON_PMCTL_RESETCTL_BOOT_DET_0_S 12 473 474 // Field: [8] VDDS_LOSS_EN 475 // 476 // Controls reset generation in case VDDS is lost 477 // 478 // 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 479 // 1: Brown out detect of VDDS generates system reset 480 #define AON_PMCTL_RESETCTL_VDDS_LOSS_EN 0x00000100 481 #define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_BITN 8 482 #define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_M 0x00000100 483 #define AON_PMCTL_RESETCTL_VDDS_LOSS_EN_S 8 484 485 // Field: [7] VDDR_LOSS_EN 486 // 487 // Controls reset generation in case VDDR is lost 488 // 489 // 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 490 // 1: Brown out detect of VDDR generates system reset 491 #define AON_PMCTL_RESETCTL_VDDR_LOSS_EN 0x00000080 492 #define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_BITN 7 493 #define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_M 0x00000080 494 #define AON_PMCTL_RESETCTL_VDDR_LOSS_EN_S 7 495 496 // Field: [6] VDD_LOSS_EN 497 // 498 // Controls reset generation in case VDD is lost 499 // 500 // 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 501 // 1: Brown out detect of VDD generates system reset 502 #define AON_PMCTL_RESETCTL_VDD_LOSS_EN 0x00000040 503 #define AON_PMCTL_RESETCTL_VDD_LOSS_EN_BITN 6 504 #define AON_PMCTL_RESETCTL_VDD_LOSS_EN_M 0x00000040 505 #define AON_PMCTL_RESETCTL_VDD_LOSS_EN_S 6 506 507 // Field: [5] CLK_LOSS_EN 508 // 509 // Controls reset generation in case SCLK_LF, SCLK_MF or SCLK_HF is lost when 510 // clock loss detection is enabled by [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] 511 // 512 // 0: Clock loss is ignored 513 // 1: Clock loss generates system reset 514 // 515 // Note: Clock loss reset generation must be disabled when changing clock 516 // source for SCLK_LF. Failure to do so may result in a spurious system 517 // reset. Clock loss reset generation is controlled by 518 // [ANATOP_MMAP:DDI_0_OSC:CTL0.CLK_LOSS_EN] 519 #define AON_PMCTL_RESETCTL_CLK_LOSS_EN 0x00000020 520 #define AON_PMCTL_RESETCTL_CLK_LOSS_EN_BITN 5 521 #define AON_PMCTL_RESETCTL_CLK_LOSS_EN_M 0x00000020 522 #define AON_PMCTL_RESETCTL_CLK_LOSS_EN_S 5 523 524 // Field: [4] MCU_WARM_RESET 525 // 526 // Internal. Only to be used through TI provided API. 527 #define AON_PMCTL_RESETCTL_MCU_WARM_RESET 0x00000010 528 #define AON_PMCTL_RESETCTL_MCU_WARM_RESET_BITN 4 529 #define AON_PMCTL_RESETCTL_MCU_WARM_RESET_M 0x00000010 530 #define AON_PMCTL_RESETCTL_MCU_WARM_RESET_S 4 531 532 // Field: [3:1] RESET_SRC 533 // 534 // Shows the root cause of the last system reset. More than the reported reset 535 // source can have been active during the last system reset but only the root 536 // cause is reported. 537 // 538 // The capture feature is not rearmed until all off the possible reset sources 539 // have been released and the result has been copied to AON_PMCTL. During the 540 // copy and rearm process it is one 2MHz period in which and eventual new 541 // system reset will be reported as Power on reset regardless of the root 542 // cause. 543 // ENUMs: 544 // WARMRESET Software reset via PRCM warm reset request 545 // SYSRESET Software reset via SYSRESET or hardware power 546 // management timeout detection. 547 // 548 // Note: The hardware power 549 // management timeout circuit is always enabled. 550 // CLK_LOSS SCLK_LF, SCLK_MF or SCLK_HF clock loss detect 551 // VDDR_LOSS Brown out detect on VDDR 552 // VDDS_LOSS Brown out detect on VDDS 553 // PIN_RESET Reset pin 554 // PWR_ON Power on reset 555 #define AON_PMCTL_RESETCTL_RESET_SRC_W 3 556 #define AON_PMCTL_RESETCTL_RESET_SRC_M 0x0000000E 557 #define AON_PMCTL_RESETCTL_RESET_SRC_S 1 558 #define AON_PMCTL_RESETCTL_RESET_SRC_WARMRESET 0x0000000E 559 #define AON_PMCTL_RESETCTL_RESET_SRC_SYSRESET 0x0000000C 560 #define AON_PMCTL_RESETCTL_RESET_SRC_CLK_LOSS 0x0000000A 561 #define AON_PMCTL_RESETCTL_RESET_SRC_VDDR_LOSS 0x00000008 562 #define AON_PMCTL_RESETCTL_RESET_SRC_VDDS_LOSS 0x00000004 563 #define AON_PMCTL_RESETCTL_RESET_SRC_PIN_RESET 0x00000002 564 #define AON_PMCTL_RESETCTL_RESET_SRC_PWR_ON 0x00000000 565 566 //***************************************************************************** 567 // 568 // Register: AON_PMCTL_O_SLEEPCTL 569 // 570 //***************************************************************************** 571 // Field: [0] IO_PAD_SLEEP_DIS 572 // 573 // Controls the I/O pad sleep mode. The boot code will set this bitfield 574 // automatically unless waking up from a SHUTDOWN ( RESETCTL.WU_FROM_SD is 575 // set). 576 // 577 // 0: I/O pad sleep mode is enabled, meaning all outputs and pad configurations 578 // are latched. Inputs are transparent if pad is configured as input before 579 // IO_PAD_SLEEP_DIS is set to 1 580 // 1: I/O pad sleep mode is disabled 581 // 582 // Application software must reconfigure the state for all IO's before setting 583 // this bitfield upon waking up from a SHUTDOWN to avoid glitches on pins. 584 #define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS 0x00000001 585 #define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_BITN 0 586 #define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_M 0x00000001 587 #define AON_PMCTL_SLEEPCTL_IO_PAD_SLEEP_DIS_S 0 588 589 //***************************************************************************** 590 // 591 // Register: AON_PMCTL_O_JTAGCFG 592 // 593 //***************************************************************************** 594 // Field: [8] JTAG_PD_FORCE_ON 595 // 596 // Controls JTAG Power domain power state: 597 // 598 // 0: Controlled exclusively by debug subsystem. (JTAG Power domain will be 599 // powered off unless a debugger is attached) 600 // 1: JTAG Power Domain is forced on, independent of debug subsystem. 601 // 602 // Note: The reset value causes JTAG Power domain to be powered on by default. 603 // Software must clear this bit to turn off the JTAG Power domain 604 #define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON 0x00000100 605 #define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_BITN 8 606 #define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_M 0x00000100 607 #define AON_PMCTL_JTAGCFG_JTAG_PD_FORCE_ON_S 8 608 609 //***************************************************************************** 610 // 611 // Register: AON_PMCTL_O_JTAGUSERCODE 612 // 613 //***************************************************************************** 614 // Field: [31:0] USER_CODE 615 // 616 // 32-bit JTAG USERCODE register feeding main JTAG TAP 617 // Note: This field can be locked by LOCKCFG.LOCK 618 #define AON_PMCTL_JTAGUSERCODE_USER_CODE_W 32 619 #define AON_PMCTL_JTAGUSERCODE_USER_CODE_M 0xFFFFFFFF 620 #define AON_PMCTL_JTAGUSERCODE_USER_CODE_S 0 621 622 623 #endif // __AON_PMCTL__ 624
