1 /****************************************************************************** 2 * Filename: hw_adi.h 3 * 4 * Copyright (c) 2015 - 2022, Texas Instruments Incorporated 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1) Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2) Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * 3) Neither the name of the ORGANIZATION nor the names of its contributors may 18 * be used to endorse or promote products derived from this software without 19 * specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 * 33 ******************************************************************************/ 34 35 #ifndef __HW_ADI_H__ 36 #define __HW_ADI_H__ 37 38 //***************************************************************************** 39 // 40 // This file contains macros for controlling the ADI master and 41 // accessing ADI slave registers via the ADI Master. 42 // There are 3 categories of macros in this file: 43 // - macros that provide an offset to a register 44 // located within the DDI Master itself. 45 // - macros that define bits or bitfields 46 // within the DDI Master Registers. 47 // - macros that provide an "instruction offset" 48 // that are used when accessing a ADI Slave. 49 // 50 // The macros that that provide ADI Master register offsets and 51 // define bits and bitfields for those registers are the typical 52 // macros that appear in most hw_<module>.h header files. In 53 // the following example ADI_O_SLAVECONF is a macro for a 54 // register offset and ADI_SLAVECONF_WAITFORACK is a macro for 55 // a bit in that register. This example code will set the WAITFORACK 56 // bit in register ADI_O_SLAVECONF of the ADI Master. (Note: this 57 // access the Master not the Slave). 58 // 59 // HWREG(ADI3_BASE + ADI_O_SLAVECONF) |= ADI_SLAVECONF_WAITFORACK; 60 // 61 // The "instruction offset" macros are used to pass an instruction to 62 // the ADI Master when accessing ADI slave registers. These macros are 63 // only used when accessing ADI Slave Registers. (Remember ADI 64 // Master Registers are accessed normally). 65 // 66 // The instructions supported when accessing an ADI Slave Register follow: 67 // - Direct Access to an ADI Slave register. I.e. read or 68 // write the register. 69 // - Set the specified bits in a ADI Slave register. 70 // - Clear the specified bits in a ADI Slave register. 71 // - Mask write of 4 bits to the a ADI Slave register. 72 // - Mask write of 8 bits to the a ADI Slave register. 73 // - Mask write of 16 bits to the a ADI Slave register. 74 // 75 // Note: only the "Direct Access" offset should be used when reading 76 // a ADI Slave register. Only 4-bit reads are supported and 8 bits write are 77 // supported natively. If accessing wider bitfields, the read/write operation 78 // will be spread out over a number of transactions. This is hidden for the 79 // user, but can potentially be very timeconsuming. Especially of running 80 // on a slow clock. 81 // 82 // The generic format of using these macros for a read follows: 83 // // Read low 8-bits in ADI_SLAVE_OFF 84 // myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); 85 // 86 // // Read high 8-bits in ADI_SLAVE_OFF (data[31:16]) 87 // myushortvar = HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR); 88 // 89 // Notes: In the above example: 90 // - ADI_MASTER_BASE is the base address of the ADI Master defined 91 // in the hw_memmap.h header file. 92 // - ADI_SLAVE_OFF is the ADI Slave offset defined in the 93 // hw_<adi_slave>.h header file (e.g. hw_adi_3_refsys_top.h for the refsys 94 // module). 95 // - ADI_O_DIR is the "instruction offset" macro defined in this 96 // file that specifies the Direct Access instruction. 97 // 98 // Writes can use any of the "instruction macros". 99 // The following examples do a "direct write" to an ADI Slave register 100 // ADI_SLAVE_OFF using different size operands: 101 // 102 // // ---------- DIRECT WRITES ---------- 103 // // Write 32-bits aligned 104 // HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x12345678; 105 // 106 // // Write 16-bits aligned to high 16-bits then low 16-bits 107 // // Add 2 to get to high 16-bits. 108 // HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0xabcd; 109 // HWREGH(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0xef01; 110 // 111 // // Write each byte at ADI_SLAVE_OFF, one at a time. 112 // // Add 1,2,or 3 to get to bytes 1,2, or 3. 113 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR) = 0x33; 114 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 1) = 0x44; 115 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 2) = 0x55; 116 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_DIR + 3) = 0x66; 117 // 118 // // ---------- SET/CLR ---------- 119 // The set and clear functions behave similarly to eachother. Each 120 // can be performed on an 8-, 16-, or 32-bit operand. 121 // Examples follow: 122 // // Set all odd bits in a 32-bit words 123 // HWREG(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_SET) = 0xaaaaaaaa; 124 // 125 // // Clear all bits in byte 2 (data[23:16]) using 32-bit operand 126 // HWREG(DDI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_CLR) = 0x00ff0000; 127 // 128 // // Set even bits in byte 2 (data[23:16]) using 8-bit operand 129 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + 2 + ADI_O_CLR) = 0x55; 130 // 131 // // ---------- MASKED WRITES ---------- 132 // The mask writes are a bit different. They operate on nibbles, 133 // bytes, and 16-bit elements. Two operands are required; a 'mask' 134 // and 'data'; The operands are concatenated and written to the master. 135 // e.g. the mask and data are combined as follows for a 16 bit masked 136 // write: 137 // (mask << 16) | data; 138 // Examples follow: 139 // 140 // // Do an 4 bit masked write (Nibble) of 7 to data[3:0]). 141 // // Byte write is needed. 142 // HWREGB(ADI_MASTER_BASE + ADI_SLAVE_OFF + ADI_O_MASK4B01) = 0xf7; 143 // 144 // // Do an 4 bit masked write of 4 to data[7:4]). 145 // // Add 1 for next nibble 146 // HWREGB(DDI_MASTER_BASE + DDI_SLAVE_OFF + ADI_O_MASK4B01 + 1) = 0xf4; 147 // 148 //***************************************************************************** 149 150 //***************************************************************************** 151 // 152 // The following are defines for the ADI master instruction offsets. 153 // 154 //***************************************************************************** 155 #define ADI_O_DIR 0x00000000 // Offset for the direct access 156 // instruction 157 #define ADI_O_SET 0x00000010 // Offset for 'Set' instruction. 158 #define ADI_O_CLR 0x00000020 // Offset for 'Clear' instruction. 159 #define ADI_O_MASK4B 0x00000040 // Offset for 4-bit masked access. 160 // Data bit[n] is written if mask 161 // bit[n] is set ('1'). 162 // Bits 7:4 are mask. Bits 3:0 are data. 163 // Requires 'byte' write. 164 #define ADI_O_MASK8B 0x00000060 // Offset for 8-bit masked access. 165 // Data bit[n] is written if mask 166 // bit[n] is set ('1'). Bits 15:8 are 167 // mask. Bits 7:0 are data. Requires 168 // 'short' write. 169 #define ADI_O_MASK16B 0x00000080 // Offset for 16-bit masked access. 170 // Data bit[n] is written if mask 171 // bit[n] is set ('1'). Bits 31:16 172 // are mask. Bits 15:0 are data. 173 // Requires 'long' write. 174 175 //***************************************************************************** 176 // 177 // The following are defines for the ADI register offsets. 178 // 179 //***************************************************************************** 180 #define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register 181 #define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration 182 183 //***************************************************************************** 184 // 185 // The following are defines for the bit fields in the 186 // ADI_O_SLAVESTAT register. 187 // 188 //***************************************************************************** 189 #define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ 190 // signal. Writing 0 to this bit 191 // forces a sync with slave, 192 // ensuring that req will be 0. It 193 // is recommended to write 0 to 194 // this register before power down 195 // of the master. 196 #define ADI_SLAVESTAT_DI_REQ_M 0x00000002 197 #define ADI_SLAVESTAT_DI_REQ_S 1 198 #define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK 199 // signal 200 #define ADI_SLAVESTAT_DI_ACK_M 0x00000001 201 #define ADI_SLAVESTAT_DI_ACK_S 0 202 //***************************************************************************** 203 // 204 // The following are defines for the bit fields in the 205 // ADI_O_SLAVECONF register. 206 // 207 //***************************************************************************** 208 #define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer 209 // accessible when this bit is set. 210 // (unless sticky_bit_overwrite is 211 // asserted on top module) 212 #define ADI_SLAVECONF_CONFLOCK_M \ 213 0x00000080 214 #define ADI_SLAVECONF_CONFLOCK_S 7 215 #define ADI_SLAVECONF_WAITFORACK \ 216 0x00000004 // A transaction on the ADI 217 // interface does not end until ack 218 // has been received from the slave 219 // when this bit is set. 220 221 #define ADI_SLAVECONF_WAITFORACK_M \ 222 0x00000004 223 #define ADI_SLAVECONF_WAITFORACK_S 2 224 #define ADI_SLAVECONF_ADICLKSPEED_M \ 225 0x00000003 // Sets the period of an ADI 226 // transactions. All transactions 227 // takes an even number of clock 228 // cycles,- ADI clock rising edge 229 // occurs in the middle of the 230 // period. Data and ctrl to slave 231 // is set up in beginning of cycle, 232 // and data from slave is read in 233 // after the transaction 00: An ADI 234 // transaction takes 2 master clock 235 // cyclkes 01: An ADI transaction 236 // takes 4 master clock cycles 10: 237 // And ADI Transaction takes 8 238 // master clock cycles 11: An ADI 239 // transaction takes 16 master 240 // clock cycles 241 242 #define ADI_SLAVECONF_ADICLKSPEED_S 0 243 244 //***************************************************************************** 245 // 246 // The following are defines pseudo-magic numbers that should go away. 247 // New code should not use these registers and old code should be ported 248 // to not use these. 249 // 250 //***************************************************************************** 251 #define ADI_O_DIR03 0x00000000 // Direct access for adi byte 252 // offsets 0 to 3 253 #define ADI_O_DIR47 0x00000004 // Direct access for adi byte 254 // offsets 4 to 7 255 #define ADI_O_DIR811 0x00000008 // Direct access for adi byte 256 // offsets 8 to 11 257 #define ADI_O_DIR1215 0x0000000C // Direct access for adi byte 258 // offsets 12 to 15 259 #define ADI_O_SET03 0x00000010 // Set register for ADI byte 260 // offsets 0 to 3 261 #define ADI_O_SET47 0x00000014 // Set register for ADI byte 262 // offsets 4 to 7 263 #define ADI_O_SET811 0x00000018 // Set register for ADI byte 264 // offsets 8 to 11 265 #define ADI_O_SET1215 0x0000001C // Set register for ADI byte 266 // offsets 12 to 15 267 #define ADI_O_CLR03 0x00000020 // Clear register for ADI byte 268 // offsets 0 to 3 269 #define ADI_O_CLR47 0x00000024 // Clear register for ADI byte 270 // offsets 4 to 7 271 #define ADI_O_CLR811 0x00000028 // Clear register for ADI byte 272 // offsets 8 to 11 273 #define ADI_O_CLR1215 0x0000002C // Clear register for ADI byte 274 // offsets 12 to 15 275 #define ADI_O_SLAVESTAT 0x00000030 // ADI Slave status register 276 #define ADI_O_SLAVECONF 0x00000038 // ADI Master configuration 277 // register 278 #define ADI_O_MASK4B01 0x00000040 // Masked access (4m/4d) for ADI 279 // Registers at byte offsets 0 and 280 // 1 281 #define ADI_O_MASK4B23 0x00000044 // Masked access (4m/4d) for ADI 282 // Registers at byte offsets 2 and 283 // 3 284 #define ADI_O_MASK4B45 0x00000048 // Masked access (4m/4d) for ADI 285 // Registers at byte offsets 4 and 286 // 5 287 #define ADI_O_MASK4B67 0x0000004C // Masked access (4m/4d) for ADI 288 // Registers at byte offsets 6 and 289 // 7 290 #define ADI_O_MASK4B89 0x00000050 // Masked access (4m/4d) for ADI 291 // Registers at byte offsets 8 and 292 // 9 293 #define ADI_O_MASK4B1011 0x00000054 // Masked access (4m/4d) for ADI 294 // Registers at byte offsets 10 and 295 // 11 296 #define ADI_O_MASK4B1213 0x00000058 // Masked access (4m/4d) for ADI 297 // Registers at byte offsets 12 and 298 // 13 299 #define ADI_O_MASK4B1415 0x0000005C // Masked access (4m/4d) for ADI 300 // Registers at byte offsets 14 and 301 // 15 302 #define ADI_O_MASK8B01 0x00000060 // Masked access (8m/8d) for ADI 303 // Registers at byte offsets 0 and 304 // 1 305 #define ADI_O_MASK8B23 0x00000064 // Masked access (8m/8d) for ADI 306 // Registers at byte offsets 2 and 307 // 3 308 #define ADI_O_MASK8B45 0x00000068 // Masked access (8m/8d) for ADI 309 // Registers at byte offsets 4 and 310 // 5 311 #define ADI_O_MASK8B67 0x0000006C // Masked access (8m/8d) for ADI 312 // Registers at byte offsets 6 and 313 // 7 314 #define ADI_O_MASK8B89 0x00000070 // Masked access (8m/8d) for ADI 315 // Registers at byte offsets 8 and 316 // 9 317 #define ADI_O_MASK8B1011 0x00000074 // Masked access (8m/8d) for ADI 318 // Registers at byte offsets 10 and 319 // 11 320 #define ADI_O_MASK8B1213 0x00000078 // Masked access (8m/8d) for ADI 321 // Registers at byte offsets 12 and 322 // 13 323 #define ADI_O_MASK8B1415 0x0000007C // Masked access (8m/8d) for ADI 324 // Registers at byte offsets 14 and 325 // 15 326 #define ADI_O_MASK16B01 0x00000080 // Masked access (16m/16d) for ADI 327 // Registers at byte offsets 0 and 328 // 1 329 #define ADI_O_MASK16B23 0x00000084 // Masked access (16m/16d) for ADI 330 // Registers at byte offsets 2 and 331 // 3 332 #define ADI_O_MASK16B45 0x00000088 // Masked access (16m/16d) for ADI 333 // Registers at byte offsets 4 and 334 // 5 335 #define ADI_O_MASK16B67 0x0000008C // Masked access (16m/16d) for ADI 336 // Registers at byte offsets 6 and 337 // 7 338 #define ADI_O_MASK16B89 0x00000090 // Masked access (16m/16d) for ADI 339 // Registers at byte offsets 8 and 340 // 9 341 #define ADI_O_MASK16B1011 0x00000094 // Masked access (16m/16d) for ADI 342 // Registers at byte offsets 10 and 343 // 11 344 #define ADI_O_MASK16B1213 0x00000098 // Masked access (16m/16d) for ADI 345 // Registers at byte offsets 12 and 346 // 13 347 #define ADI_O_MASK16B1415 0x0000009C // Masked access (16m/16d) for ADI 348 // Registers at byte offsets 14 and 349 // 15 350 351 //***************************************************************************** 352 // 353 // The following are defines for the bit fields in the ADI_O_DIR03 register. 354 // 355 //***************************************************************************** 356 #define ADI_DIR03_B3_M 0xFF000000 // Direct access to ADI register 3 357 #define ADI_DIR03_B3_S 24 358 #define ADI_DIR03_B2_M 0x00FF0000 // Direct access to ADI register 2 359 #define ADI_DIR03_B2_S 16 360 #define ADI_DIR03_B1_M 0x0000FF00 // Direct access to ADI register 1 361 #define ADI_DIR03_B1_S 8 362 #define ADI_DIR03_B0_M 0x000000FF // Direct access to ADI register 0 363 #define ADI_DIR03_B0_S 0 364 //***************************************************************************** 365 // 366 // The following are defines for the bit fields in the ADI_O_DIR47 register. 367 // 368 //***************************************************************************** 369 #define ADI_DIR47_B3_M 0xFF000000 // Direct access to ADI register 7 370 #define ADI_DIR47_B3_S 24 371 #define ADI_DIR47_B2_M 0x00FF0000 // Direct access to ADI register 6 372 #define ADI_DIR47_B2_S 16 373 #define ADI_DIR47_B1_M 0x0000FF00 // Direct access to ADI register 5 374 #define ADI_DIR47_B1_S 8 375 #define ADI_DIR47_B0_M 0x000000FF // Direct access to ADI register 4 376 #define ADI_DIR47_B0_S 0 377 //***************************************************************************** 378 // 379 // The following are defines for the bit fields in the ADI_O_DIR811 register. 380 // 381 //***************************************************************************** 382 #define ADI_DIR811_B3_M 0xFF000000 // Direct access to ADI register 383 // 11 384 #define ADI_DIR811_B3_S 24 385 #define ADI_DIR811_B2_M 0x00FF0000 // Direct access to ADI register 386 // 10 387 #define ADI_DIR811_B2_S 16 388 #define ADI_DIR811_B1_M 0x0000FF00 // Direct access to ADI register 9 389 #define ADI_DIR811_B1_S 8 390 #define ADI_DIR811_B0_M 0x000000FF // Direct access to ADI register 8 391 #define ADI_DIR811_B0_S 0 392 //***************************************************************************** 393 // 394 // The following are defines for the bit fields in the ADI_O_DIR1215 register. 395 // 396 //***************************************************************************** 397 #define ADI_DIR1215_B3_M 0xFF000000 // Direct access to ADI register 398 // 15 399 #define ADI_DIR1215_B3_S 24 400 #define ADI_DIR1215_B2_M 0x00FF0000 // Direct access to ADI register 401 // 14 402 #define ADI_DIR1215_B2_S 16 403 #define ADI_DIR1215_B1_M 0x0000FF00 // Direct access to ADI register 404 // 13 405 #define ADI_DIR1215_B1_S 8 406 #define ADI_DIR1215_B0_M 0x000000FF // Direct access to ADI register 407 // 12 408 #define ADI_DIR1215_B0_S 0 409 //***************************************************************************** 410 // 411 // The following are defines for the bit fields in the ADI_O_SET03 register. 412 // 413 //***************************************************************************** 414 #define ADI_SET03_S3_M 0xFF000000 // A high bit value will set the 415 // corresponding bit in ADI 416 // register 3. Read returns 0. 417 #define ADI_SET03_S3_S 24 418 #define ADI_SET03_S2_M 0x00FF0000 // A high bit value will set the 419 // corresponding bit in ADI 420 // register 2. Read returns 0. 421 #define ADI_SET03_S2_S 16 422 #define ADI_SET03_S1_M 0x0000FF00 // A high bit value will set the 423 // corresponding bit in ADI 424 // register 1. Read returns 0. 425 #define ADI_SET03_S1_S 8 426 #define ADI_SET03_S0_M 0x000000FF // A high bit value will set the 427 // corresponding bit in ADI 428 // register 0. Read returns 0. 429 #define ADI_SET03_S0_S 0 430 //***************************************************************************** 431 // 432 // The following are defines for the bit fields in the ADI_O_SET47 register. 433 // 434 //***************************************************************************** 435 #define ADI_SET47_S3_M 0xFF000000 // A high bit value will set the 436 // corresponding bit in ADI 437 // register 7. Read returns 0. 438 #define ADI_SET47_S3_S 24 439 #define ADI_SET47_S2_M 0x00FF0000 // A high bit value will set the 440 // corresponding bit in ADI 441 // register 6. Read returns 0. 442 #define ADI_SET47_S2_S 16 443 #define ADI_SET47_S1_M 0x0000FF00 // A high bit value will set the 444 // corresponding bit in ADI 445 // register 5. Read returns 0. 446 #define ADI_SET47_S1_S 8 447 #define ADI_SET47_S0_M 0x000000FF // A high bit value will set the 448 // corresponding bit in ADI 449 // register 4. Read returns 0. 450 #define ADI_SET47_S0_S 0 451 //***************************************************************************** 452 // 453 // The following are defines for the bit fields in the ADI_O_SET811 register. 454 // 455 //***************************************************************************** 456 #define ADI_SET811_S3_M 0xFF000000 // A high bit value will set the 457 // corresponding bit in ADI 458 // register 11. Read returns 0. 459 #define ADI_SET811_S3_S 24 460 #define ADI_SET811_S2_M 0x00FF0000 // A high bit value will set the 461 // corresponding bit in ADI 462 // register 10. Read returns 0. 463 #define ADI_SET811_S2_S 16 464 #define ADI_SET811_S1_M 0x0000FF00 // A high bit value will set the 465 // corresponding bit in ADI 466 // register 9. Read returns 0. 467 #define ADI_SET811_S1_S 8 468 #define ADI_SET811_S0_M 0x000000FF // A high bit value will set the 469 // corresponding bit in ADI 470 // register 8. Read returns 0. 471 #define ADI_SET811_S0_S 0 472 //***************************************************************************** 473 // 474 // The following are defines for the bit fields in the ADI_O_SET1215 register. 475 // 476 //***************************************************************************** 477 #define ADI_SET1215_S3_M 0xFF000000 // A high bit value will set the 478 // corresponding bit in ADI 479 // register 15. Read returns 0. 480 #define ADI_SET1215_S3_S 24 481 #define ADI_SET1215_S2_M 0x00FF0000 // A high bit value will set the 482 // corresponding bit in ADI 483 // register 14. Read returns 0. 484 #define ADI_SET1215_S2_S 16 485 #define ADI_SET1215_S1_M 0x0000FF00 // A high bit value will set the 486 // corresponding bit in ADI 487 // register 13. Read returns 0. 488 #define ADI_SET1215_S1_S 8 489 #define ADI_SET1215_S0_M 0x000000FF // A high bit value will set the 490 // corresponding bit in ADI 491 // register 12. Read returns 0. 492 #define ADI_SET1215_S0_S 0 493 //***************************************************************************** 494 // 495 // The following are defines for the bit fields in the ADI_O_CLR03 register. 496 // 497 //***************************************************************************** 498 #define ADI_CLR03_S3_M 0xFF000000 // A high bit value will clear the 499 // corresponding bit in ADI 500 // register 3 501 #define ADI_CLR03_S3_S 24 502 #define ADI_CLR03_S2_M 0x00FF0000 // A high bit value will clear the 503 // corresponding bit in ADI 504 // register 2 505 #define ADI_CLR03_S2_S 16 506 #define ADI_CLR03_S1_M 0x0000FF00 // A high bit value will clear the 507 // corresponding bit in ADI 508 // register 1 509 #define ADI_CLR03_S1_S 8 510 #define ADI_CLR03_S0_M 0x000000FF // A high bit value will clear the 511 // corresponding bit in ADI 512 // register 0 513 #define ADI_CLR03_S0_S 0 514 //***************************************************************************** 515 // 516 // The following are defines for the bit fields in the ADI_O_CLR47 register. 517 // 518 //***************************************************************************** 519 #define ADI_CLR47_S3_M 0xFF000000 // A high bit value will clear the 520 // corresponding bit in ADI 521 // register 7 522 #define ADI_CLR47_S3_S 24 523 #define ADI_CLR47_S2_M 0x00FF0000 // A high bit value will clear the 524 // corresponding bit in ADI 525 // register 6 526 #define ADI_CLR47_S2_S 16 527 #define ADI_CLR47_S1_M 0x0000FF00 // A high bit value will clear the 528 // corresponding bit in ADI 529 // register 5 530 #define ADI_CLR47_S1_S 8 531 #define ADI_CLR47_S0_M 0x000000FF // A high bit value will clear the 532 // corresponding bit in ADI 533 // register 4 534 #define ADI_CLR47_S0_S 0 535 //***************************************************************************** 536 // 537 // The following are defines for the bit fields in the ADI_O_CLR811 register. 538 // 539 //***************************************************************************** 540 #define ADI_CLR811_S3_M 0xFF000000 // A high bit value will clear the 541 // corresponding bit in ADI 542 // register 11 543 #define ADI_CLR811_S3_S 24 544 #define ADI_CLR811_S2_M 0x00FF0000 // A high bit value will clear the 545 // corresponding bit in ADI 546 // register 10 547 #define ADI_CLR811_S2_S 16 548 #define ADI_CLR811_S1_M 0x0000FF00 // A high bit value will clear the 549 // corresponding bit in ADI 550 // register 9 551 #define ADI_CLR811_S1_S 8 552 #define ADI_CLR811_S0_M 0x000000FF // A high bit value will clear the 553 // corresponding bit in ADI 554 // register 8 555 #define ADI_CLR811_S0_S 0 556 //***************************************************************************** 557 // 558 // The following are defines for the bit fields in the ADI_O_CLR1215 register. 559 // 560 //***************************************************************************** 561 #define ADI_CLR1215_S3_M 0xFF000000 // A high bit value will clear the 562 // corresponding bit in ADI 563 // register 15 564 #define ADI_CLR1215_S3_S 24 565 #define ADI_CLR1215_S2_M 0x00FF0000 // A high bit value will clear the 566 // corresponding bit in ADI 567 // register 14 568 #define ADI_CLR1215_S2_S 16 569 #define ADI_CLR1215_S1_M 0x0000FF00 // A high bit value will clear the 570 // corresponding bit in ADI 571 // register 13 572 #define ADI_CLR1215_S1_S 8 573 #define ADI_CLR1215_S0_M 0x000000FF // A high bit value will clear the 574 // corresponding bit in ADI 575 // register 12 576 #define ADI_CLR1215_S0_S 0 577 //***************************************************************************** 578 // 579 // The following are defines for the bit fields in the 580 // ADI_O_SLAVESTAT register. 581 // 582 //***************************************************************************** 583 #define ADI_SLAVESTAT_DI_REQ 0x00000002 // Read current value of DI_REQ 584 // signal. Writing 0 to this bit 585 // forces a sync with slave, 586 // ensuring that req will be 0. It 587 // is recommended to write 0 to 588 // this register before power down 589 // of the master. 590 #define ADI_SLAVESTAT_DI_REQ_M 0x00000002 591 #define ADI_SLAVESTAT_DI_REQ_S 1 592 #define ADI_SLAVESTAT_DI_ACK 0x00000001 // Read current value of DI_ACK 593 // signal 594 #define ADI_SLAVESTAT_DI_ACK_M 0x00000001 595 #define ADI_SLAVESTAT_DI_ACK_S 0 596 //***************************************************************************** 597 // 598 // The following are defines for the bit fields in the 599 // ADI_O_SLAVECONF register. 600 // 601 //***************************************************************************** 602 #define ADI_SLAVECONF_CONFLOCK 0x00000080 // This register is no longer 603 // accessible when this bit is set. 604 // (unless sticky_bit_overwrite is 605 // asserted on top module) 606 #define ADI_SLAVECONF_CONFLOCK_M \ 607 0x00000080 608 #define ADI_SLAVECONF_CONFLOCK_S 7 609 #define ADI_SLAVECONF_WAITFORACK \ 610 0x00000004 // A transaction on the ADI 611 // interface does not end until ack 612 // has been received from the slave 613 // when this bit is set. 614 615 #define ADI_SLAVECONF_WAITFORACK_M \ 616 0x00000004 617 #define ADI_SLAVECONF_WAITFORACK_S 2 618 #define ADI_SLAVECONF_ADICLKSPEED_M \ 619 0x00000003 // Sets the period of an ADI 620 // transactions. All transactions 621 // takes an even number of clock 622 // cycles,- ADI clock rising edge 623 // occurs in the middle of the 624 // period. Data and ctrl to slave 625 // is set up in beginning of cycle, 626 // and data from slave is read in 627 // after the transaction 00: An ADI 628 // transaction takes 2 master clock 629 // cyclkes 01: An ADI transaction 630 // takes 4 master clock cycles 10: 631 // And ADI Transaction takes 8 632 // master clock cycles 11: An ADI 633 // transaction takes 16 master 634 // clock cycles 635 636 #define ADI_SLAVECONF_ADICLKSPEED_S 0 637 //***************************************************************************** 638 // 639 // The following are defines for the bit fields in the ADI_O_MASK4B01 register. 640 // 641 //***************************************************************************** 642 #define ADI_MASK4B01_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 643 // register 1 644 #define ADI_MASK4B01_M1H_S 28 645 #define ADI_MASK4B01_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 646 // register 1, - only bits selected 647 // by mask M1H will be affected by 648 // access 649 #define ADI_MASK4B01_D1H_S 24 650 #define ADI_MASK4B01_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 651 // register 1 652 #define ADI_MASK4B01_M1L_S 20 653 #define ADI_MASK4B01_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 654 // register 1, - only bits selected 655 // by mask M1L will be affected by 656 // access 657 #define ADI_MASK4B01_D1L_S 16 658 #define ADI_MASK4B01_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 659 // register 0 660 #define ADI_MASK4B01_M0H_S 12 661 #define ADI_MASK4B01_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 662 // register 0, - only bits selected 663 // by mask M0H will be affected by 664 // access 665 #define ADI_MASK4B01_D0H_S 8 666 #define ADI_MASK4B01_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 667 // register 0 668 #define ADI_MASK4B01_M0L_S 4 669 #define ADI_MASK4B01_D0L_M 0x0000000F // Data for bits [3:0] in ADI 670 // register 0, - only bits selected 671 // by mask M0L will be affected by 672 // access 673 #define ADI_MASK4B01_D0L_S 0 674 //***************************************************************************** 675 // 676 // The following are defines for the bit fields in the ADI_O_MASK4B23 register. 677 // 678 //***************************************************************************** 679 #define ADI_MASK4B23_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 680 // register 3 681 #define ADI_MASK4B23_M1H_S 28 682 #define ADI_MASK4B23_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 683 // register 3, - only bits selected 684 // by mask M1H will be affected by 685 // access 686 #define ADI_MASK4B23_D1H_S 24 687 #define ADI_MASK4B23_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 688 // register 3 689 #define ADI_MASK4B23_M1L_S 20 690 #define ADI_MASK4B23_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 691 // register 3, - only bits selected 692 // by mask M1L will be affected by 693 // access 694 #define ADI_MASK4B23_D1L_S 16 695 #define ADI_MASK4B23_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 696 // register 2 697 #define ADI_MASK4B23_M0H_S 12 698 #define ADI_MASK4B23_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 699 // register 2, - only bits selected 700 // by mask M0H will be affected by 701 // access 702 #define ADI_MASK4B23_D0H_S 8 703 #define ADI_MASK4B23_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 704 // register 2 705 #define ADI_MASK4B23_M0L_S 4 706 #define ADI_MASK4B23_D0L_M 0x0000000F // Data for bits [3:0] in ADI 707 // register 2, - only bits selected 708 // by mask M0L will be affected by 709 // access 710 #define ADI_MASK4B23_D0L_S 0 711 //***************************************************************************** 712 // 713 // The following are defines for the bit fields in the ADI_O_MASK4B45 register. 714 // 715 //***************************************************************************** 716 #define ADI_MASK4B45_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 717 // register 5 718 #define ADI_MASK4B45_M1H_S 28 719 #define ADI_MASK4B45_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 720 // register 5, - only bits selected 721 // by mask M1H will be affected by 722 // access 723 #define ADI_MASK4B45_D1H_S 24 724 #define ADI_MASK4B45_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 725 // register 5 726 #define ADI_MASK4B45_M1L_S 20 727 #define ADI_MASK4B45_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 728 // register 5, - only bits selected 729 // by mask M1L will be affected by 730 // access 731 #define ADI_MASK4B45_D1L_S 16 732 #define ADI_MASK4B45_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 733 // register 4 734 #define ADI_MASK4B45_M0H_S 12 735 #define ADI_MASK4B45_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 736 // register 4, - only bits selected 737 // by mask M0H will be affected by 738 // access 739 #define ADI_MASK4B45_D0H_S 8 740 #define ADI_MASK4B45_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 741 // register 4 742 #define ADI_MASK4B45_M0L_S 4 743 #define ADI_MASK4B45_D0L_M 0x0000000F // Data for bits [3:0] in ADI 744 // register 4, - only bits selected 745 // by mask M0L will be affected by 746 // access 747 #define ADI_MASK4B45_D0L_S 0 748 //***************************************************************************** 749 // 750 // The following are defines for the bit fields in the ADI_O_MASK4B67 register. 751 // 752 //***************************************************************************** 753 #define ADI_MASK4B67_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 754 // register 7 755 #define ADI_MASK4B67_M1H_S 28 756 #define ADI_MASK4B67_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 757 // register 7, - only bits selected 758 // by mask M1H will be affected by 759 // access 760 #define ADI_MASK4B67_D1H_S 24 761 #define ADI_MASK4B67_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 762 // register 7 763 #define ADI_MASK4B67_M1L_S 20 764 #define ADI_MASK4B67_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 765 // register 7, - only bits selected 766 // by mask M1L will be affected by 767 // access 768 #define ADI_MASK4B67_D1L_S 16 769 #define ADI_MASK4B67_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 770 // register 6 771 #define ADI_MASK4B67_M0H_S 12 772 #define ADI_MASK4B67_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 773 // register 6, - only bits selected 774 // by mask M0H will be affected by 775 // access 776 #define ADI_MASK4B67_D0H_S 8 777 #define ADI_MASK4B67_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 778 // register 6 779 #define ADI_MASK4B67_M0L_S 4 780 #define ADI_MASK4B67_D0L_M 0x0000000F // Data for bits [3:0] in ADI 781 // register 6, - only bits selected 782 // by mask M0L will be affected by 783 // access 784 #define ADI_MASK4B67_D0L_S 0 785 //***************************************************************************** 786 // 787 // The following are defines for the bit fields in the ADI_O_MASK4B89 register. 788 // 789 //***************************************************************************** 790 #define ADI_MASK4B89_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 791 // register 9 792 #define ADI_MASK4B89_M1H_S 28 793 #define ADI_MASK4B89_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 794 // register 9, - only bits selected 795 // by mask M1H will be affected by 796 // access 797 #define ADI_MASK4B89_D1H_S 24 798 #define ADI_MASK4B89_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 799 // register 9 800 #define ADI_MASK4B89_M1L_S 20 801 #define ADI_MASK4B89_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 802 // register 9, - only bits selected 803 // by mask M1L will be affected by 804 // access 805 #define ADI_MASK4B89_D1L_S 16 806 #define ADI_MASK4B89_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 807 // register 8 808 #define ADI_MASK4B89_M0H_S 12 809 #define ADI_MASK4B89_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 810 // register 8, - only bits selected 811 // by mask M0H will be affected by 812 // access 813 #define ADI_MASK4B89_D0H_S 8 814 #define ADI_MASK4B89_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 815 // register 8 816 #define ADI_MASK4B89_M0L_S 4 817 #define ADI_MASK4B89_D0L_M 0x0000000F // Data for bits [3:0] in ADI 818 // register 8, - only bits selected 819 // by mask M0L will be affected by 820 // access 821 #define ADI_MASK4B89_D0L_S 0 822 //***************************************************************************** 823 // 824 // The following are defines for the bit fields in the 825 // ADI_O_MASK4B1011 register. 826 // 827 //***************************************************************************** 828 #define ADI_MASK4B1011_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 829 // register 11 830 #define ADI_MASK4B1011_M1H_S 28 831 #define ADI_MASK4B1011_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 832 // register 11, - only bits 833 // selected by mask M1H will be 834 // affected by access 835 #define ADI_MASK4B1011_D1H_S 24 836 #define ADI_MASK4B1011_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 837 // register 11 838 #define ADI_MASK4B1011_M1L_S 20 839 #define ADI_MASK4B1011_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 840 // register 11, - only bits 841 // selected by mask M1L will be 842 // affected by access 843 #define ADI_MASK4B1011_D1L_S 16 844 #define ADI_MASK4B1011_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 845 // register 10 846 #define ADI_MASK4B1011_M0H_S 12 847 #define ADI_MASK4B1011_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 848 // register 10, - only bits 849 // selected by mask M0H will be 850 // affected by access 851 #define ADI_MASK4B1011_D0H_S 8 852 #define ADI_MASK4B1011_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 853 // register 10 854 #define ADI_MASK4B1011_M0L_S 4 855 #define ADI_MASK4B1011_D0L_M 0x0000000F // Data for bits [3:0] in ADI 856 // register 10, - only bits 857 // selected by mask M0L will be 858 // affected by access 859 #define ADI_MASK4B1011_D0L_S 0 860 //***************************************************************************** 861 // 862 // The following are defines for the bit fields in the 863 // ADI_O_MASK4B1213 register. 864 // 865 //***************************************************************************** 866 #define ADI_MASK4B1213_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 867 // register 13 868 #define ADI_MASK4B1213_M1H_S 28 869 #define ADI_MASK4B1213_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 870 // register 13, - only bits 871 // selected by mask M1H will be 872 // affected by access 873 #define ADI_MASK4B1213_D1H_S 24 874 #define ADI_MASK4B1213_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 875 // register 13 876 #define ADI_MASK4B1213_M1L_S 20 877 #define ADI_MASK4B1213_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 878 // register 13, - only bits 879 // selected by mask M1L will be 880 // affected by access 881 #define ADI_MASK4B1213_D1L_S 16 882 #define ADI_MASK4B1213_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 883 // register 12 884 #define ADI_MASK4B1213_M0H_S 12 885 #define ADI_MASK4B1213_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 886 // register 12, - only bits 887 // selected by mask M0H will be 888 // affected by access 889 #define ADI_MASK4B1213_D0H_S 8 890 #define ADI_MASK4B1213_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 891 // register 12 892 #define ADI_MASK4B1213_M0L_S 4 893 #define ADI_MASK4B1213_D0L_M 0x0000000F // Data for bits [3:0] in ADI 894 // register 12, - only bits 895 // selected by mask M0L will be 896 // affected by access 897 #define ADI_MASK4B1213_D0L_S 0 898 //***************************************************************************** 899 // 900 // The following are defines for the bit fields in the 901 // ADI_O_MASK4B1415 register. 902 // 903 //***************************************************************************** 904 #define ADI_MASK4B1415_M1H_M 0xF0000000 // Mask for bits [7:4] in ADI 905 // register 15 906 #define ADI_MASK4B1415_M1H_S 28 907 #define ADI_MASK4B1415_D1H_M 0x0F000000 // Data for bits [7:4] in ADI 908 // register 15, - only bits 909 // selected by mask M1H will be 910 // affected by access 911 #define ADI_MASK4B1415_D1H_S 24 912 #define ADI_MASK4B1415_M1L_M 0x00F00000 // Mask for bits [3:0] in ADI 913 // register 15 914 #define ADI_MASK4B1415_M1L_S 20 915 #define ADI_MASK4B1415_D1L_M 0x000F0000 // Data for bits [3:0] in ADI 916 // register 15, - only bits 917 // selected by mask M1L will be 918 // affected by access 919 #define ADI_MASK4B1415_D1L_S 16 920 #define ADI_MASK4B1415_M0H_M 0x0000F000 // Mask for bits [7:4] in ADI 921 // register 14 922 #define ADI_MASK4B1415_M0H_S 12 923 #define ADI_MASK4B1415_D0H_M 0x00000F00 // Data for bits [7:4] in ADI 924 // register 14, - only bits 925 // selected by mask M0H will be 926 // affected by access 927 #define ADI_MASK4B1415_D0H_S 8 928 #define ADI_MASK4B1415_M0L_M 0x000000F0 // Mask for bits [3:0] in ADI 929 // register 14 930 #define ADI_MASK4B1415_M0L_S 4 931 #define ADI_MASK4B1415_D0L_M 0x0000000F // Data for bits [3:0] in ADI 932 // register 14, - only bits 933 // selected by mask M0L will be 934 // affected by access 935 #define ADI_MASK4B1415_D0L_S 0 936 //***************************************************************************** 937 // 938 // The following are defines for the bit fields in the ADI_O_MASK8B01 register. 939 // 940 //***************************************************************************** 941 #define ADI_MASK8B01_M1_M 0xFF000000 // Mask for ADI register 1 942 #define ADI_MASK8B01_M1_S 24 943 #define ADI_MASK8B01_D1_M 0x00FF0000 // Data for ADI register 1, - only 944 // bits selected by mask M1 will be 945 // affected by access 946 #define ADI_MASK8B01_D1_S 16 947 #define ADI_MASK8B01_M0_M 0x0000FF00 // Mask for ADI register 0 948 #define ADI_MASK8B01_M0_S 8 949 #define ADI_MASK8B01_D0_M 0x000000FF // Data for ADI register 0, - only 950 // bits selected by mask M0 will be 951 // affected by access 952 #define ADI_MASK8B01_D0_S 0 953 //***************************************************************************** 954 // 955 // The following are defines for the bit fields in the ADI_O_MASK8B23 register. 956 // 957 //***************************************************************************** 958 #define ADI_MASK8B23_M1_M 0xFF000000 // Mask for ADI register 3 959 #define ADI_MASK8B23_M1_S 24 960 #define ADI_MASK8B23_D1_M 0x00FF0000 // Data for ADI register 3, - only 961 // bits selected by mask M1 will be 962 // affected by access 963 #define ADI_MASK8B23_D1_S 16 964 #define ADI_MASK8B23_M0_M 0x0000FF00 // Mask for ADI register 2 965 #define ADI_MASK8B23_M0_S 8 966 #define ADI_MASK8B23_D0_M 0x000000FF // Data for ADI register 2, - only 967 // bits selected by mask M0 will be 968 // affected by access 969 #define ADI_MASK8B23_D0_S 0 970 //***************************************************************************** 971 // 972 // The following are defines for the bit fields in the ADI_O_MASK8B45 register. 973 // 974 //***************************************************************************** 975 #define ADI_MASK8B45_M1_M 0xFF000000 // Mask for ADI register 5 976 #define ADI_MASK8B45_M1_S 24 977 #define ADI_MASK8B45_D1_M 0x00FF0000 // Data for ADI register 5, - only 978 // bits selected by mask M1 will be 979 // affected by access 980 #define ADI_MASK8B45_D1_S 16 981 #define ADI_MASK8B45_M0_M 0x0000FF00 // Mask for ADI register 4 982 #define ADI_MASK8B45_M0_S 8 983 #define ADI_MASK8B45_D0_M 0x000000FF // Data for ADI register 4, - only 984 // bits selected by mask M0 will be 985 // affected by access 986 #define ADI_MASK8B45_D0_S 0 987 //***************************************************************************** 988 // 989 // The following are defines for the bit fields in the ADI_O_MASK8B67 register. 990 // 991 //***************************************************************************** 992 #define ADI_MASK8B67_M1_M 0xFF000000 // Mask for ADI register 7 993 #define ADI_MASK8B67_M1_S 24 994 #define ADI_MASK8B67_D1_M 0x00FF0000 // Data for ADI register 7, - only 995 // bits selected by mask M1 will be 996 // affected by access 997 #define ADI_MASK8B67_D1_S 16 998 #define ADI_MASK8B67_M0_M 0x0000FF00 // Mask for ADI register 6 999 #define ADI_MASK8B67_M0_S 8 1000 #define ADI_MASK8B67_D0_M 0x000000FF // Data for ADI register 6, - only 1001 // bits selected by mask M0 will be 1002 // affected by access 1003 #define ADI_MASK8B67_D0_S 0 1004 //***************************************************************************** 1005 // 1006 // The following are defines for the bit fields in the ADI_O_MASK8B89 register. 1007 // 1008 //***************************************************************************** 1009 #define ADI_MASK8B89_M1_M 0xFF000000 // Mask for ADI register 9 1010 #define ADI_MASK8B89_M1_S 24 1011 #define ADI_MASK8B89_D1_M 0x00FF0000 // Data for ADI register 9, - only 1012 // bits selected by mask M1 will be 1013 // affected by access 1014 #define ADI_MASK8B89_D1_S 16 1015 #define ADI_MASK8B89_M0_M 0x0000FF00 // Mask for ADI register 8 1016 #define ADI_MASK8B89_M0_S 8 1017 #define ADI_MASK8B89_D0_M 0x000000FF // Data for ADI register 8, - only 1018 // bits selected by mask M0 will be 1019 // affected by access 1020 #define ADI_MASK8B89_D0_S 0 1021 //***************************************************************************** 1022 // 1023 // The following are defines for the bit fields in the 1024 // ADI_O_MASK8B1011 register. 1025 // 1026 //***************************************************************************** 1027 #define ADI_MASK8B1011_M1_M 0xFF000000 // Mask for ADI register 11 1028 #define ADI_MASK8B1011_M1_S 24 1029 #define ADI_MASK8B1011_D1_M 0x00FF0000 // Data for ADI register 11, - 1030 // only bits selected by mask M1 1031 // will be affected by access 1032 #define ADI_MASK8B1011_D1_S 16 1033 #define ADI_MASK8B1011_M0_M 0x0000FF00 // Mask for ADI register 10 1034 #define ADI_MASK8B1011_M0_S 8 1035 #define ADI_MASK8B1011_D0_M 0x000000FF // Data for ADI register 10, - 1036 // only bits selected by mask M0 1037 // will be affected by access 1038 #define ADI_MASK8B1011_D0_S 0 1039 //***************************************************************************** 1040 // 1041 // The following are defines for the bit fields in the 1042 // ADI_O_MASK8B1213 register. 1043 // 1044 //***************************************************************************** 1045 #define ADI_MASK8B1213_M1_M 0xFF000000 // Mask for ADI register 13 1046 #define ADI_MASK8B1213_M1_S 24 1047 #define ADI_MASK8B1213_D1_M 0x00FF0000 // Data for ADI register 13, - 1048 // only bits selected by mask M1 1049 // will be affected by access 1050 #define ADI_MASK8B1213_D1_S 16 1051 #define ADI_MASK8B1213_M0_M 0x0000FF00 // Mask for ADI register 12 1052 #define ADI_MASK8B1213_M0_S 8 1053 #define ADI_MASK8B1213_D0_M 0x000000FF // Data for ADI register 12, - 1054 // only bits selected by mask M0 1055 // will be affected by access 1056 #define ADI_MASK8B1213_D0_S 0 1057 //***************************************************************************** 1058 // 1059 // The following are defines for the bit fields in the 1060 // ADI_O_MASK8B1415 register. 1061 // 1062 //***************************************************************************** 1063 #define ADI_MASK8B1415_M1_M 0xFF000000 // Mask for ADI register 15 1064 #define ADI_MASK8B1415_M1_S 24 1065 #define ADI_MASK8B1415_D1_M 0x00FF0000 // Data for ADI register 15, - 1066 // only bits selected by mask M1 1067 // will be affected by access 1068 #define ADI_MASK8B1415_D1_S 16 1069 #define ADI_MASK8B1415_M0_M 0x0000FF00 // Mask for ADI register 14 1070 #define ADI_MASK8B1415_M0_S 8 1071 #define ADI_MASK8B1415_D0_M 0x000000FF // Data for ADI register 14, - 1072 // only bits selected by mask M0 1073 // will be affected by access 1074 #define ADI_MASK8B1415_D0_S 0 1075 //***************************************************************************** 1076 // 1077 // The following are defines for the bit fields in the 1078 // ADI_O_MASK16B01 register. 1079 // 1080 //***************************************************************************** 1081 #define ADI_MASK16B01_M_M 0xFFFF0000 // Mask for ADI register 0 and 1 1082 #define ADI_MASK16B01_M_S 16 1083 #define ADI_MASK16B01_D_M 0x0000FFFF // Data for ADI register at 1084 // offsets 0 and 1, - only bits 1085 // selected by mask M will be 1086 // affected by access 1087 #define ADI_MASK16B01_D_S 0 1088 //***************************************************************************** 1089 // 1090 // The following are defines for the bit fields in the 1091 // ADI_O_MASK16B23 register. 1092 // 1093 //***************************************************************************** 1094 #define ADI_MASK16B23_M_M 0xFFFF0000 // Mask for ADI register 2 and 3 1095 #define ADI_MASK16B23_M_S 16 1096 #define ADI_MASK16B23_D_M 0x0000FFFF // Data for ADI register at 1097 // offsets 2 and 3, - only bits 1098 // selected by mask M will be 1099 // affected by access 1100 #define ADI_MASK16B23_D_S 0 1101 //***************************************************************************** 1102 // 1103 // The following are defines for the bit fields in the 1104 // ADI_O_MASK16B45 register. 1105 // 1106 //***************************************************************************** 1107 #define ADI_MASK16B45_M_M 0xFFFF0000 // Mask for ADI register 4 and 5 1108 #define ADI_MASK16B45_M_S 16 1109 #define ADI_MASK16B45_D_M 0x0000FFFF // Data for ADI register at 1110 // offsets 4 and 5, - only bits 1111 // selected by mask M will be 1112 // affected by access 1113 #define ADI_MASK16B45_D_S 0 1114 //***************************************************************************** 1115 // 1116 // The following are defines for the bit fields in the 1117 // ADI_O_MASK16B67 register. 1118 // 1119 //***************************************************************************** 1120 #define ADI_MASK16B67_M_M 0xFFFF0000 // Mask for ADI register 6 and 7 1121 #define ADI_MASK16B67_M_S 16 1122 #define ADI_MASK16B67_D_M 0x0000FFFF // Data for ADI register at 1123 // offsets 6 and 7, - only bits 1124 // selected by mask M will be 1125 // affected by access 1126 #define ADI_MASK16B67_D_S 0 1127 //***************************************************************************** 1128 // 1129 // The following are defines for the bit fields in the 1130 // ADI_O_MASK16B89 register. 1131 // 1132 //***************************************************************************** 1133 #define ADI_MASK16B89_M_M 0xFFFF0000 // Mask for ADI register 8 and 9 1134 #define ADI_MASK16B89_M_S 16 1135 #define ADI_MASK16B89_D_M 0x0000FFFF // Data for ADI register at 1136 // offsets 8 and 9, - only bits 1137 // selected by mask M will be 1138 // affected by access 1139 #define ADI_MASK16B89_D_S 0 1140 //***************************************************************************** 1141 // 1142 // The following are defines for the bit fields in the 1143 // ADI_O_MASK16B1011 register. 1144 // 1145 //***************************************************************************** 1146 #define ADI_MASK16B1011_M_M 0xFFFF0000 // Mask for ADI register 10 and 11 1147 #define ADI_MASK16B1011_M_S 16 1148 #define ADI_MASK16B1011_D_M 0x0000FFFF // Data for ADI register at 1149 // offsets 10 and 11, - only bits 1150 // selected by mask M will be 1151 // affected by access 1152 #define ADI_MASK16B1011_D_S 0 1153 //***************************************************************************** 1154 // 1155 // The following are defines for the bit fields in the 1156 // ADI_O_MASK16B1213 register. 1157 // 1158 //***************************************************************************** 1159 #define ADI_MASK16B1213_M_M 0xFFFF0000 // Mask for ADI register 12 and 13 1160 #define ADI_MASK16B1213_M_S 16 1161 #define ADI_MASK16B1213_D_M 0x0000FFFF // Data for ADI register at 1162 // offsets 12 and 13, - only bits 1163 // selected by mask M will be 1164 // affected by access 1165 #define ADI_MASK16B1213_D_S 0 1166 //***************************************************************************** 1167 // 1168 // The following are defines for the bit fields in the 1169 // ADI_O_MASK16B1415 register. 1170 // 1171 //***************************************************************************** 1172 #define ADI_MASK16B1415_M_M 0xFFFF0000 // Mask for ADI register 14 and 15 1173 #define ADI_MASK16B1415_M_S 16 1174 #define ADI_MASK16B1415_D_M 0x0000FFFF // Data for ADI register at 1175 // offsets 14 and 15, - only bits 1176 // selected by mask M will be 1177 // affected by access 1178 #define ADI_MASK16B1415_D_S 0 1179 1180 #endif // __HW_ADI_H__ 1181
